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Shreesha Srinath [Sat, 19 Aug 2017 01:21:04 +0000 (18:21 -0700)]
Updates to Freedom SoCs
Richard Xia [Thu, 8 Dec 2016 20:14:17 +0000 (12:14 -0800)]
Add variable to control what program gets flashed to FPGA.
Wesley W. Terpstra [Thu, 1 Dec 2016 22:06:37 +0000 (14:06 -0800)]
README: our systems are untethered
Richard Xia [Thu, 1 Dec 2016 19:05:18 +0000 (11:05 -0800)]
Merge pull request #6 from sifive/remove-consts-vh
Remove verilog header files built from Chisel .prm file.
Richard Xia [Wed, 30 Nov 2016 23:00:50 +0000 (15:00 -0800)]
Also remove unused .prm file from Makefile.
Richard Xia [Wed, 30 Nov 2016 22:30:05 +0000 (14:30 -0800)]
Remove verilog header files built from Chisel .prm file.
Henry Styles [Wed, 30 Nov 2016 04:38:00 +0000 (20:38 -0800)]
Merge pull request #4 from sifive/fix_u500vc707devkit_dot_img
Update U500 VC707 Dev Kit BootROM image for SDBoot
Henry Styles [Wed, 30 Nov 2016 04:32:16 +0000 (20:32 -0800)]
fix U500 BootROM image for SDBoot
Olof Kindgren [Tue, 29 Nov 2016 22:22:26 +0000 (23:22 +0100)]
Use public accessible URL for submodules
SiFive [Tue, 29 Nov 2016 13:23:27 +0000 (05:23 -0800)]
Add submodules.
SiFive [Tue, 29 Nov 2016 13:23:11 +0000 (05:23 -0800)]
Initial commit.
projects / freedom-sifive.git / log