Replace "muxcover -freedecode" with "muxcover -dmux=cost"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "muxcover -freedecode"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improvements in muxcover

- Slightly under-estimate cost of decoder muxes
- Prefer larger muxes at tree root at same cost
- Don't double-count input cost for partial muxes
- Add debug log output

Missing a `clean` and `opt_expr -mux_bool` in test

Add test

Add support for partial matches to muxcover, fixes #1091

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix typo, fixes #1095

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve shregmap help message, fixes #1113

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update some .gitignore files

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix typo

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'towoe-unpacked_arrays'

Add proper test for SV-style arrays

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into towoe-unpacked_arrays

Merge pull request #1111 from acw1251/help_summary_fixes

Fixed the help summary line for a few commands

Fixed small typo in ice40_unlut help summary

Fixed the help summary line for a few commands

Fix bug in #1078, add entry to CHANGELOG

Merge pull request #1109 from YosysHQ/clifford/fix1106

Add "read_verilog -pwires" feature

Add "read_verilog -pwires" feature, closes #1106

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #1105 from YosysHQ/clifford/fixlogicinit

Improve handling of initial/default values

Unpacked array declaration using size

Allows fixed-sized array dimension specified by a single number.

This commit is based on the work from PeterCrozier
https://github.com/YosysHQ/yosys/pull/560.
But is split out of the original work.

Make tests/aiger less chatty

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add defvalue test, minor autotest fixes for .sv files

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Use input default values in hierarchy pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add defaultvalue attribute

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix handling of "logic" variables with initial value

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #1100 from bwidawsk/home

Support ~ in filename parsing

Merge pull request #1104 from whitequark/case-semantics

Clarify switch/case semantics in RTLIL

Explain exact semantics of switch and case rules in the manual.

In RTLIL::Module::check(), check process invariants.

Support filename rewrite in backends

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Support ~ for home directory

This is tested on Linux only

v2:
Wrap functioanlity in ifndef _WIN32 (eddiehung)
Find '~/' instead of '~' (cliffordwolf)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Merge pull request #1086 from udif/pr_elab_sys_tasks2

Fixed broken $error()/$info/$warning() on non-generate blocks (within always/initial blocks)

Add timescale and generated-by header to yosys-smtbmc MkVcd

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #829 from abdelrahmanhosny/master

Dockerfile for Yosys

Fixed brojen $error()/$info/$warning() on non-generate blocks
(within always/initial blocks)

Add some more comments

Merge pull request #1082 from corecode/u4k

ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k

ice40/cells_sim.v: Add support for RGB_DRV/LED_DRV_CUR for u4k

Merge pull request #1078 from YosysHQ/eddie/muxcover_costs

Allow muxcover costs to be changed

Fix spacing from spaces to tabs

Merge pull request #1079 from YosysHQ/eddie/fix_read_aiger

Fix read_aiger to really get tested, and fix some uncovered read_aiger issues

Add read_aiger to CHANGELOG

Fix spacing (entire file is wrong anyway, will fix later)

Remove unnecessary std::getline() for ASCII

Test *.aag too, by using *.aig as reference

Fix read_aiger -- create zero driver, fix init width, parse 'b'

Use ABC to convert from AIGER to Verilog

Use ABC to convert AIGER to Verilog, then sat against Yosys

Add symbols to AIGER test inputs for ABC

Allow muxcover costs to be changed

Merge pull request #1077 from YosysHQ/clifford/pr983

elaboration system tasks

Rename implicit_ports.sv test to implicit_ports.v

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fixes and cleanups in AST_TECALL handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983

Merge branch 'tux3-implicit_named_connection'

Merge pull request #1076 from thasti/centos7-build-fix

Fix pyosys-build on CentOS7

Cleanup tux3-implicit_named_connection

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys into tux3-implicit_named_connection

remove boost/log/exceptions.hpp from wrapper generator

SystemVerilog support for implicit named port connections

This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.

Merge pull request #1060 from antmicro/parsing_attr_on_port_conn

Added support for parsing attributes on port connections.

Merge pull request #1073 from whitequark/ecp5-diamond-iob

ECP5: implement most Diamond I/O buffer primitives

ECP5: implement all Diamond I/O buffer primitives.

Merge pull request #1071 from YosysHQ/eddie/fix_1070

Fix typo in opt_rmdff causing register to be incorrectly removed

Merge pull request #1072 from YosysHQ/eddie/fix_1069

Error out if no top module given before 'sim'

Missing doc for -tech xilinx in shregmap

Error out if no top module given before 'sim'

Fix typo in opt_rmdff

Merge pull request #1067 from YosysHQ/clifford/fix1065

Suppress driver-driver conflict warning for unknown cell types

Fixed memory leak.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Merge pull request #1066 from YosysHQ/clifford/fix1056

Remove yosys_banner() from python wrapper init

Major rewrite of wire selection in setundef -init

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Indent fix

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #999 from jakobwenzel/setundefInitFix

initialize more registers in setundef -init

Fix typo in fmcombine log message, fixes #1063

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Suppress driver-driver conflict warning for unknown cell types, fixes #1065

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Remove yosys_banner() from python wrapper init, fixes #1056

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #1062 from tux3/patch-1

README.md: Missing formatting for <tag>

README.md: Missing formatting for <tag>

Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_map

Execute techmap and arith_map simultaneously

Remove extra newline

Execute techmap and arith_map simultaneously

Added tests for attributes

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Only support Symbiotic EDA flavored Verific

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Added support for parsing attributes on port connections.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Fix "tee" handling of log_streams

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Enable Verific flag veri_elaborate_top_level_modules_having_interface_ports, fixes #1055

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #1057 from mmicko/fix_478

Aded one more load of .conf to support change of prefix

Aded one more load of .conf to support change of prefix

Merge pull request #1049 from YosysHQ/clifford/fix1047

 Do not use shiftmul peepopt pattern when mul result is truncated

Merge pull request #1050 from YosysHQ/clifford/wandwor

Refactored wand/wor support

Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #1048 from mmicko/fix_enable_pyosys

Moved pyosys block in Makefile

Refactor hierarchy wand/wor handling

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add actual wandwor test that is part of "make test"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'wandwor' of https://github.com/thasti/yosys into clifford/wandwor

Remove info line in 2nd load of conf file

Moved pyosys block in Makefile