Eddie Hung [Tue, 16 Apr 2019 21:53:01 +0000 (14:53 -0700)]
Fix wire numbering
Eddie Hung [Tue, 16 Apr 2019 20:44:15 +0000 (13:44 -0700)]
Do not put constants into output_bits
Eddie Hung [Tue, 16 Apr 2019 20:24:54 +0000 (13:24 -0700)]
Remove write_verilog call
Eddie Hung [Tue, 16 Apr 2019 20:16:20 +0000 (13:16 -0700)]
Fix spacing
Eddie Hung [Tue, 16 Apr 2019 20:15:53 +0000 (13:15 -0700)]
Merge branch 'xaig' into xc7mux
Eddie Hung [Tue, 16 Apr 2019 20:10:35 +0000 (13:10 -0700)]
Re-enable partsel.v test
Eddie Hung [Tue, 16 Apr 2019 20:10:13 +0000 (13:10 -0700)]
abc9 to call "setundef -zero" behaving as for abc
Eddie Hung [Tue, 16 Apr 2019 19:59:48 +0000 (12:59 -0700)]
NULL check before use
Eddie Hung [Tue, 16 Apr 2019 19:57:27 +0000 (12:57 -0700)]
WIP for box support
Eddie Hung [Tue, 16 Apr 2019 19:44:10 +0000 (12:44 -0700)]
ABC to read_box before reading netlist
Eddie Hung [Tue, 16 Apr 2019 19:43:14 +0000 (12:43 -0700)]
Make cells.box whiteboxes not blackboxes
Eddie Hung [Tue, 16 Apr 2019 19:41:56 +0000 (12:41 -0700)]
read_verilog cells_box.v before techmap
Eddie Hung [Tue, 16 Apr 2019 18:21:46 +0000 (11:21 -0700)]
synth_xilinx: before abc read +/xilinx/cells_box.v
Eddie Hung [Tue, 16 Apr 2019 18:21:03 +0000 (11:21 -0700)]
Add +/xilinx/cells_box.v containing models for ABC boxes
Eddie Hung [Tue, 16 Apr 2019 18:19:54 +0000 (11:19 -0700)]
For 'stat' do not count modules with abc_box_id
Eddie Hung [Tue, 16 Apr 2019 18:19:42 +0000 (11:19 -0700)]
Do not call abc on modules with abc_box_id attr
Eddie Hung [Tue, 16 Apr 2019 18:14:59 +0000 (11:14 -0700)]
Revert "Add abc_box_id attribute to MUXF7/F8 cells"
This reverts commit
8fbbd9b129697152c93c35831c1d50982702a3ec.
Eddie Hung [Tue, 16 Apr 2019 05:27:36 +0000 (22:27 -0700)]
Use abc_box_id
Eddie Hung [Tue, 16 Apr 2019 05:25:37 +0000 (22:25 -0700)]
Check abc_box_id attr
Eddie Hung [Tue, 16 Apr 2019 05:25:09 +0000 (22:25 -0700)]
Add abc_box_id attribute to MUXF7/F8 cells
Eddie Hung [Tue, 16 Apr 2019 05:04:20 +0000 (22:04 -0700)]
Merge branch 'xaig' into xc7mux
Eddie Hung [Tue, 16 Apr 2019 04:56:45 +0000 (21:56 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Tue, 16 Apr 2019 01:39:20 +0000 (18:39 -0700)]
Merge pull request #937 from YosysHQ/revert-932-eddie/fixdlatch
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
Eddie Hung [Tue, 16 Apr 2019 00:52:45 +0000 (17:52 -0700)]
Revert "Recognise default entry in case even if all cases covered (fix for #931)"
Eddie Hung [Mon, 15 Apr 2019 19:22:05 +0000 (12:22 -0700)]
Merge pull request #936 from YosysHQ/README-fix-quotes
README: fix some incorrect quoting
whitequark [Mon, 15 Apr 2019 14:29:46 +0000 (14:29 +0000)]
README: fix some incorrect quoting.
Eddie Hung [Sat, 13 Apr 2019 01:22:44 +0000 (18:22 -0700)]
Forgot backslashes
Eddie Hung [Sat, 13 Apr 2019 01:21:16 +0000 (18:21 -0700)]
Handle __dummy_o__ and __const[01]__ in read_aiger not abc
Eddie Hung [Sat, 13 Apr 2019 01:16:50 +0000 (18:16 -0700)]
abc to ignore __dummy_o__ and __const[01]__ when re-integrating
Eddie Hung [Sat, 13 Apr 2019 01:16:25 +0000 (18:16 -0700)]
Output __const0__ and __const1__ CIs
Eddie Hung [Sat, 13 Apr 2019 00:09:24 +0000 (17:09 -0700)]
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung [Sat, 13 Apr 2019 00:02:24 +0000 (17:02 -0700)]
Fix inout handling for -map option
Eddie Hung [Fri, 12 Apr 2019 23:31:12 +0000 (16:31 -0700)]
Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung [Fri, 12 Apr 2019 23:30:53 +0000 (16:30 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Fri, 12 Apr 2019 23:29:14 +0000 (16:29 -0700)]
Use -map instead of -symbols for aiger
Eddie Hung [Fri, 12 Apr 2019 23:17:48 +0000 (16:17 -0700)]
ci_bits and co_bits now a list, order is important for ABC
Eddie Hung [Fri, 12 Apr 2019 23:17:12 +0000 (16:17 -0700)]
Also cope with duplicated CIs
Eddie Hung [Fri, 12 Apr 2019 21:13:11 +0000 (14:13 -0700)]
WIP
Eddie Hung [Tue, 9 Apr 2019 17:09:43 +0000 (10:09 -0700)]
Comment out
Eddie Hung [Tue, 9 Apr 2019 17:06:44 +0000 (10:06 -0700)]
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
Eddie Hung [Fri, 12 Apr 2019 19:27:07 +0000 (12:27 -0700)]
Cope with an output having same name as an input (i.e. CO)
Eddie Hung [Fri, 12 Apr 2019 19:21:48 +0000 (12:21 -0700)]
Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung [Fri, 12 Apr 2019 18:52:45 +0000 (11:52 -0700)]
Merge pull request #928 from litghost/add_xc7_sim_models
Add additional cells sim models for core 7-series primitives.
Eddie Hung [Fri, 12 Apr 2019 17:36:05 +0000 (10:36 -0700)]
PI before CI
Eddie Hung [Fri, 12 Apr 2019 16:46:07 +0000 (09:46 -0700)]
Merge remote-tracking branch 'origin/master' into xc7mux
Keith Rothman [Fri, 12 Apr 2019 16:30:49 +0000 (09:30 -0700)]
Remove BUFGCTRL, BUFHCE and LUT6_2 from cells_xtra.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Clifford Wolf [Fri, 12 Apr 2019 12:57:36 +0000 (14:57 +0200)]
Merge pull request #933 from dh73/master
Fixing issues in CycloneV cell sim
Clifford Wolf [Fri, 12 Apr 2019 12:57:01 +0000 (14:57 +0200)]
Merge pull request #932 from YosysHQ/eddie/fixdlatch
Recognise default entry in case even if all cases covered (fix for #931)
Diego [Fri, 12 Apr 2019 00:59:03 +0000 (19:59 -0500)]
Fixing issues in CycloneV cell sim
Eddie Hung [Thu, 11 Apr 2019 23:21:01 +0000 (16:21 -0700)]
Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux
Eddie Hung [Thu, 11 Apr 2019 23:20:43 +0000 (16:20 -0700)]
More unused
Eddie Hung [Thu, 11 Apr 2019 23:18:45 +0000 (16:18 -0700)]
Merge remote-tracking branch 'origin/pmux2shiftx' into xc7mux
Eddie Hung [Thu, 11 Apr 2019 23:18:01 +0000 (16:18 -0700)]
Remove unused
Eddie Hung [Thu, 11 Apr 2019 23:17:09 +0000 (16:17 -0700)]
Fixes
Eddie Hung [Thu, 11 Apr 2019 22:52:04 +0000 (15:52 -0700)]
WIP
Eddie Hung [Thu, 11 Apr 2019 22:09:13 +0000 (15:09 -0700)]
Spelling fixes
Eddie Hung [Thu, 11 Apr 2019 22:03:40 +0000 (15:03 -0700)]
Add default entry to testcase
Eddie Hung [Thu, 11 Apr 2019 19:34:51 +0000 (12:34 -0700)]
Recognise default entry in case even if all cases covered (#931)
Eddie Hung [Thu, 11 Apr 2019 17:48:14 +0000 (10:48 -0700)]
Fix cells_map.v some more
Eddie Hung [Thu, 11 Apr 2019 17:08:05 +0000 (10:08 -0700)]
More fine tuning
Eddie Hung [Thu, 11 Apr 2019 17:04:58 +0000 (10:04 -0700)]
Fix cells_map.v
Eddie Hung [Thu, 11 Apr 2019 16:25:19 +0000 (09:25 -0700)]
Fix typo
Eddie Hung [Thu, 11 Apr 2019 16:13:39 +0000 (09:13 -0700)]
Juggle opt calls in synth_xilinx
Eddie Hung [Thu, 11 Apr 2019 01:07:11 +0000 (18:07 -0700)]
Merge branch 'xaig' into xc7mux
Eddie Hung [Thu, 11 Apr 2019 01:06:33 +0000 (18:06 -0700)]
Add non-input bits driven by unrecognised cells as ci_bits
Eddie Hung [Thu, 11 Apr 2019 01:05:09 +0000 (18:05 -0700)]
WIP for cells_map.v -- maybe working?
Eddie Hung [Wed, 10 Apr 2019 23:15:23 +0000 (16:15 -0700)]
Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1
Eddie Hung [Wed, 10 Apr 2019 21:51:10 +0000 (14:51 -0700)]
Fix for when B_SIGNED = 1
Eddie Hung [Wed, 10 Apr 2019 21:48:58 +0000 (14:48 -0700)]
Update doc for synth_xilinx
Eddie Hung [Wed, 10 Apr 2019 21:03:09 +0000 (14:03 -0700)]
Merge branch 'xaig' into xc7mux
Eddie Hung [Wed, 10 Apr 2019 21:02:23 +0000 (14:02 -0700)]
parse_aiger() to rename all $lut cells after "clean"
Eddie Hung [Wed, 10 Apr 2019 19:36:06 +0000 (12:36 -0700)]
ff_map.v after abc
Eddie Hung [Wed, 10 Apr 2019 16:02:42 +0000 (09:02 -0700)]
Tidy up
Eddie Hung [Wed, 10 Apr 2019 15:50:31 +0000 (08:50 -0700)]
Move map_cells to before map_luts
Eddie Hung [Wed, 10 Apr 2019 15:49:55 +0000 (08:49 -0700)]
WIP for $shiftx to wide mux
Eddie Hung [Wed, 10 Apr 2019 15:49:39 +0000 (08:49 -0700)]
Update LUT delays
Eddie Hung [Tue, 9 Apr 2019 21:33:37 +0000 (14:33 -0700)]
Add cells.lut to techlibs/xilinx/
Eddie Hung [Tue, 9 Apr 2019 21:32:39 +0000 (14:32 -0700)]
synth_xilinx to call abc with -lut +/xilinx/cells.lut
Eddie Hung [Tue, 9 Apr 2019 21:32:10 +0000 (14:32 -0700)]
Add delays to cells.box
Eddie Hung [Tue, 9 Apr 2019 21:31:31 +0000 (14:31 -0700)]
Add "-lut <file>" support to abc9
Keith Rothman [Tue, 9 Apr 2019 18:43:19 +0000 (11:43 -0700)]
Fix LUT6_2 definition.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Eddie Hung [Tue, 9 Apr 2019 18:01:46 +0000 (11:01 -0700)]
synth_xilinx with abc9 to use -box
Eddie Hung [Tue, 9 Apr 2019 17:58:58 +0000 (10:58 -0700)]
Add techlibs/xilinx/cells.box
Eddie Hung [Tue, 9 Apr 2019 17:58:06 +0000 (10:58 -0700)]
Add "-box" option to abc9
Eddie Hung [Tue, 9 Apr 2019 17:32:58 +0000 (10:32 -0700)]
Add 'setundef -zero' call prior to aigmap in abc9
Eddie Hung [Tue, 9 Apr 2019 17:09:43 +0000 (10:09 -0700)]
Comment out
Eddie Hung [Tue, 9 Apr 2019 17:06:44 +0000 (10:06 -0700)]
Add support for synth_xilinx -abc9 and ignore abc9 -dress opt
Keith Rothman [Tue, 9 Apr 2019 16:01:53 +0000 (09:01 -0700)]
Add additional cells sim models for core 7-series primatives.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Eddie Hung [Mon, 8 Apr 2019 23:46:33 +0000 (16:46 -0700)]
Fix a few typos
Eddie Hung [Mon, 8 Apr 2019 23:40:17 +0000 (16:40 -0700)]
More space fixing
Eddie Hung [Mon, 8 Apr 2019 23:37:22 +0000 (16:37 -0700)]
Fix spacing
Eddie Hung [Mon, 8 Apr 2019 23:31:59 +0000 (16:31 -0700)]
Merge branch 'master' into xaig
Clifford Wolf [Mon, 8 Apr 2019 19:14:05 +0000 (21:14 +0200)]
Merge pull request #919 from YosysHQ/multiport_transp
memory_bram: Fix multiport make_transp
David Shah [Sun, 7 Apr 2019 15:56:31 +0000 (16:56 +0100)]
memory_bram: Fix multiport make_transp
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Fri, 5 Apr 2019 15:31:49 +0000 (17:31 +0200)]
Add "read_ilang -lib"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 4 Apr 2019 16:10:10 +0000 (18:10 +0200)]
Added missing argument checking to "mutate" command
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Wed, 3 Apr 2019 13:27:41 +0000 (06:27 -0700)]
Merge pull request #913 from smunaut/fix_proc_mux
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
Sylvain Munaut [Wed, 3 Apr 2019 12:50:12 +0000 (14:50 +0200)]
proc_mux: Fix crash when trying to optimize non-existant mux to shiftx
last_mux_cell can be NULL ...
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Clifford Wolf [Wed, 3 Apr 2019 08:00:18 +0000 (10:00 +0200)]
Merge pull request #912 from YosysHQ/bram_addr_en
memory_bram: Consider read enable for address expansion register
Clifford Wolf [Wed, 3 Apr 2019 07:59:11 +0000 (09:59 +0200)]
Merge pull request #910 from ucb-bar/memupdates
Refine memory support to deal with general Verilog memory definitions.
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