Ali Saidi [Wed, 17 Jan 2007 00:06:05 +0000 (19:06 -0500)]
Modify ISA and staticInst to support a IsFirstMicroOp flag
Increment instruction count on first micro-op instead of last
src/arch/sparc/isa/decoder.isa:
Implement a twin load for ASI_LDTX_P(0xe2)
src/arch/sparc/isa/formats/mem/blockmem.isa:
set the new flag IsFirstMicroOp when needed
src/cpu/simple/atomic.cc:
Increment instruction count on first micro-op instead of last (because if we take a fault on a micro coded instruction it should be counted twice acording to legion)
src/cpu/static_inst.hh:
Add IsFirstMicroop flag to static insts
--HG--
extra : convert_revision :
02bea93d38c03bbafe4570665eb4c01c11caa2fc
Ali Saidi [Thu, 11 Jan 2007 03:19:13 +0000 (22:19 -0500)]
bug fixes to get us to 145m instructions
src/arch/sparc/intregfile.cc:
some checks to make sure that the cwp and global register flattening stuff is working. These things have caught a couple of bugs so I think it would be good to keep them around at least for now
src/arch/sparc/isa/decoder.isa:
fix smul instruction to write Y correctly
src/arch/sparc/miscregfile.cc:
legion always returns du and dl set, so we need to emulate that for now at least
--HG--
extra : convert_revision :
82f9276340888f1e43071c69504486efdcfdb3a8
Ali Saidi [Wed, 10 Jan 2007 03:20:38 +0000 (22:20 -0500)]
quiet/remove some warnings
fix implementation of cwp manipulation
implement PS0 and PS1 IMMU asis
src/arch/sparc/miscregfile.cc:
get rid of some warnings
fix implementation of setting cwp to saturate cwp since it appears the os sets it to a large value to see how many there actually are
src/arch/sparc/tlb.cc:
implement PS0 and PS1 IMMU access ASIs
src/arch/sparc/ua2005.cc:
make warning less verbose
--HG--
extra : convert_revision :
442b65dfc41ebc32b2ef0e6b80da94eee3be9cd3
Ali Saidi [Wed, 10 Jan 2007 03:16:49 +0000 (22:16 -0500)]
add memory mapped disk device
configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
add configuration for memory mapped disk
src/dev/sparc/SConscript:
add memory mapped disk to sconscript
--HG--
extra : convert_revision :
d8df4a455cf48000042d0ff93a274985f4dbe905
Ali Saidi [Mon, 8 Jan 2007 22:11:10 +0000 (17:11 -0500)]
change when legion-lock causes the simulation to die. It now happens after two consuctive differences since we compare stuff
at slightly different times interrupts are seen the cycle before they happen in m5 so the pc gets changed early.
--HG--
extra : convert_revision :
f237363eababb2aad67e5b41670cf40be048a042
Ali Saidi [Mon, 8 Jan 2007 22:09:48 +0000 (17:09 -0500)]
fix softint and partially implement hstick interrupts need to figure out how to do the acutal interrupting still
src/arch/sparc/miscregfile.cc:
fix softint and fprs in miscregfile
--HG--
extra : convert_revision :
cf98bd9c172e20f328f18e07dd05f63f37f14c87
Ali Saidi [Fri, 5 Jan 2007 20:04:17 +0000 (15:04 -0500)]
set the softint appropriately on an timer compare interrupt
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.cc:
there is no interrupt_level_0 interrupt, so start the list at 0x40 so the adding is done correctly
src/arch/sparc/faults.hh:
correct protection defines
src/arch/sparc/ua2005.cc:
set the softint appropriately on an timer compare interrupt
--HG--
extra : convert_revision :
f41c10ec78db973b3f856c70b58a17f83b60bbe2
Ali Saidi [Fri, 5 Jan 2007 01:22:56 +0000 (20:22 -0500)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
e8ac13e1222796ab362fabb9b19694682538da29
Ali Saidi [Fri, 5 Jan 2007 01:22:45 +0000 (20:22 -0500)]
Fix stick compare to work correctly and set checkInterrupts to true at the appropriate time
turn warnings into dprintfs
src/arch/sparc/miscregfile.cc:
turn dprintfn into dprintfs
--HG--
extra : convert_revision :
cd313e9037c8f040d837de4c7ddbcf98534e60ad
Nathan Binkert [Wed, 3 Jan 2007 18:16:22 +0000 (10:16 -0800)]
set __name__ in the root m5 script to __m5_main__ so we can
tell if the script is run from m5 as the m5 script
--HG--
extra : convert_revision :
06f646cbb8c82444ef345115aa49324a4d3a2c9f
Nathan Binkert [Wed, 3 Jan 2007 18:13:45 +0000 (10:13 -0800)]
Formatting
--HG--
extra : convert_revision :
bf1eae73995f772a4343c8ebcb254818eeb5d949
Nathan Binkert [Wed, 3 Jan 2007 18:12:55 +0000 (10:12 -0800)]
Add 'Time' as a parameter type that can accept various
formats for time (strings, datetime objects, etc.)
Advance system time to 1/1/2009
Clean up time management code a little bit
--HG--
extra : convert_revision :
28ebecc7ea6b12f4345c77a9a6b4bdf2e752c4f8
Kevin Lim [Sat, 30 Dec 2006 18:21:25 +0000 (13:21 -0500)]
Fix up previous commit to proper logic.
src/cpu/o3/commit_impl.hh:
Oops, changed the logic a little bit. Fix it up to how it used to be.
--HG--
extra : convert_revision :
df7f69b0997207b611374c3c92880f3a405e88be
Nathan Binkert [Sat, 30 Dec 2006 00:58:08 +0000 (16:58 -0800)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into iceaxe.:/Volumes/work/m5/incoming
--HG--
extra : convert_revision :
dad5311afaaf40c1378017514c8b3f73852f13f5
Nathan Binkert [Sat, 30 Dec 2006 00:57:45 +0000 (16:57 -0800)]
Formatting
--HG--
extra : convert_revision :
f5a940a8b9aaba0703781b398cf29be581907c21
Ali Saidi [Wed, 27 Dec 2006 19:38:22 +0000 (14:38 -0500)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
afd4266bd494bb8f127c06985f343219ded4f637
Ali Saidi [Wed, 27 Dec 2006 19:38:07 +0000 (14:38 -0500)]
Bug fixes in the TLB
Make our replacement algorithm same as legion (although not same as the spec)
itb should be 64 entries not 48
src/arch/sparc/tlb.cc:
Bug fixes in the TLB
Make our replacement algorithm same as legion (although not same as the spec)
src/arch/sparc/tlb.hh:
Make our replacement algorithm same as legion (although not same as the spec)
src/python/m5/objects/SparcTLB.py:
itb should be 64 entries too
--HG--
extra : convert_revision :
1b5cb3597091e3cfe293e94f6f2219b1e621c35f
Ali Saidi [Wed, 27 Dec 2006 19:35:23 +0000 (14:35 -0500)]
Compare legion and m5 tlbs for differences
Only print faults instructions that aren't traps or faulting loads
src/cpu/exetrace.cc:
Compare the legion and m5 tlbs and printout any differences
Only show differences if the instruction isn't a trap and isn't a memory
operation that changes the trap level (a fault)
src/cpu/m5legion_interface.h:
update the m5<->legion interface to add tlb data
--HG--
extra : convert_revision :
6963b64ca1012604e6b1d3c5e0e5f5282fd0164e
Ali Saidi [Wed, 27 Dec 2006 19:32:26 +0000 (14:32 -0500)]
Change MemoryAccess dprintfs to print the data as well
--HG--
extra : convert_revision :
51336fffa5e51a810ad2f6eb29b91c1bfd67824b
Nathan Binkert [Wed, 27 Dec 2006 18:52:25 +0000 (10:52 -0800)]
No need to use NULL, just use 0
The result of operator= cannot be an l-value
--HG--
extra : convert_revision :
df97a57f466e3498bd5a29638cb9912c7f3e1bd4
Kevin Lim [Tue, 26 Dec 2006 06:43:18 +0000 (01:43 -0500)]
Remove some #if FULL_SYSTEMs so MP stuff works even in SE mode.
--HG--
extra : convert_revision :
5c334ec806305451b3883c7fd0ed9cd695c038bc
Nathan Binkert [Sun, 24 Dec 2006 23:15:12 +0000 (15:15 -0800)]
Make sure that all of the bits in the result are set
to some value.
--HG--
extra : convert_revision :
1f1700fd77531cbb8cfad7f04ce2b573fcdefdab
Nathan Binkert [Sun, 24 Dec 2006 22:06:56 +0000 (14:06 -0800)]
remove some output formatting stuff that we don't use
--HG--
extra : convert_revision :
367917499d3d7aebd0a91dad28c915bc85def624
Nathan Binkert [Sat, 23 Dec 2006 05:51:19 +0000 (21:51 -0800)]
Add options for setting the kernel to run and the
script to run
--HG--
extra : convert_revision :
32ad8e08ca74edf042d8606ca4876cbe1193e932
Nathan Binkert [Fri, 22 Dec 2006 06:41:08 +0000 (22:41 -0800)]
Fix copyright
--HG--
extra : convert_revision :
8ad7824885a5c4da80175c47ba5288aab55b06ca
Nathan Binkert [Fri, 22 Dec 2006 06:38:50 +0000 (22:38 -0800)]
Expose the C++ event queue to python via the python function
m5.internal.event.create(). It takes a python object and a
Tick and calls process() when the Tick occurs.
--HG--
extra : convert_revision :
5e4c9728982b206163ff51e6850a1497d85ad7a3
Nathan Binkert [Fri, 22 Dec 2006 06:34:19 +0000 (22:34 -0800)]
style
--HG--
extra : convert_revision :
6bbaaa88a608081eebf706ff30293f38729415aa
Nathan Binkert [Thu, 21 Dec 2006 23:58:38 +0000 (15:58 -0800)]
Create a wrapper function to more easily add swig stuff to the build
--HG--
extra : convert_revision :
3aaf540a9e314a88a8945579398f0d79aa85d5cf
Nathan Binkert [Thu, 21 Dec 2006 23:49:16 +0000 (15:49 -0800)]
move the swig initialization calls from src/sim/main.cc to
src/python/swig/init.cc so that it's not as easy to forget
about it when you add a new swig module.
--HG--
extra : convert_revision :
5cc4ec0838e636aa761901effb8986de58d23e03
Nathan Binkert [Thu, 21 Dec 2006 06:20:11 +0000 (22:20 -0800)]
don't use (*activeThreads).begin(), use activeThreads->blah().
Also don't call (*activeThreads).end() over and over. Just
call activeThreads->end() once and save the result.
Make sure we always check that there are elements in the list
before we grab the first one.
--HG--
extra : convert_revision :
d769d8ed52da99532d57a9bbc93e92ddf22b7e58
Nathan Binkert [Thu, 21 Dec 2006 05:46:39 +0000 (21:46 -0800)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into iceaxe.:/Volumes/work/m5/incoming
--HG--
extra : convert_revision :
c1724538f27091e16ca495c8fdf2df06f55f7668
Nathan Binkert [Thu, 21 Dec 2006 05:46:16 +0000 (21:46 -0800)]
<scold> Make sure that variables are always initalized! </scold>
--HG--
extra : convert_revision :
1e946d9b1e1def36f9b8a73986dabf1b77096327
Steve Reinhardt [Tue, 19 Dec 2006 07:11:48 +0000 (02:11 -0500)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
--HG--
extra : convert_revision :
4bd4f8bb8e48e09562a2d9ae6eb7d061be973c5e
Ali Saidi [Tue, 19 Dec 2006 07:11:47 +0000 (02:11 -0500)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
fa8ce7149973245a73bb562b9378db13be647a14
Ali Saidi [Tue, 19 Dec 2006 07:11:33 +0000 (02:11 -0500)]
fix twinx loads a little bit
bugfixes and demap implementation in tlb
ignore some more differencs for one cycle
src/arch/sparc/isa/formats/mem/blockmem.isa:
twinx has 2 micro-ops
src/arch/sparc/isa/formats/mem/util.isa:
fix the fault check for twinx
src/arch/sparc/tlb.cc:
tlb bugfixes and write demapping code
src/cpu/exetrace.cc:
don't halt on a couple more instruction (ldx, stx) when things differ
beacuse of the way tlb faults are handled in legion.
--HG--
extra : convert_revision :
1e156dead6ebd58b257213625ed63c3793ef4b71
Steve Reinhardt [Tue, 19 Dec 2006 07:07:52 +0000 (23:07 -0800)]
Streamline Cache/Tags interface: get rid of redundant functions,
don't regenerate address from block in cache so that tags can
turn around and use address to look up block again.
--HG--
extra : convert_revision :
171018aa6e331d98399c4e5ef24e173c95eaca28
Steve Reinhardt [Tue, 19 Dec 2006 05:53:06 +0000 (21:53 -0800)]
No need to template prefetcher on cache TagStore type.
--HG--
rename : src/mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher.cc
extra : convert_revision :
56c0b51e424a3a6590332dba4866e69a1ad19598
Steve Reinhardt [Tue, 19 Dec 2006 04:47:12 +0000 (20:47 -0800)]
Get rid of generic CacheTags object (fold back into Cache).
--HG--
extra : convert_revision :
8769bd8cc358ab3cbbdbbcd909b2e0f1515e09da
Nathan Binkert [Mon, 18 Dec 2006 22:08:42 +0000 (14:08 -0800)]
Fix unittest compiles
--HG--
extra : convert_revision :
1163437081e1f1eab3f4512d04317dc94a673b9b
Nathan Binkert [Mon, 18 Dec 2006 22:07:52 +0000 (14:07 -0800)]
cast chars to int when we want to print integers so we get a number
instead of a character
--HG--
extra : convert_revision :
7bfa88ba23ad057b751eb01a80416d9f72cfe81a
Ali Saidi [Mon, 18 Dec 2006 08:37:52 +0000 (03:37 -0500)]
move the twinx loads to the correct opcode and add asis 0x24 and 0x27
Make the TLB ok to translate QUAD_LDD
src/arch/sparc/isa/decoder.isa:
move the twinx loads to the correct opcode.
src/arch/sparc/tlb.cc:
Make QUAD_LDD asi ok to execute
--HG--
extra : convert_revision :
2a44d1c9e4edb627079fc05776c28d918c8508ce
Nathan Binkert [Mon, 18 Dec 2006 02:58:50 +0000 (18:58 -0800)]
Nate's utility for compiling m5
--HG--
extra : convert_revision :
84b21f667736dfe07891323dcc810437ccb3c7c0
Nathan Binkert [Mon, 18 Dec 2006 02:58:05 +0000 (18:58 -0800)]
Utilities for doing a format check for some elements of proper
m5 style and fixing whitespace. For whitespace, any tabs in
leading whitespace on a line are converted to spaces, and any
trailing whitespace is removed.
--HG--
extra : convert_revision :
d0591663c028a388635fc71c6c1d31f700748cf6
Gabe Black [Sun, 17 Dec 2006 16:16:04 +0000 (11:16 -0500)]
Compilation fixes.
--HG--
extra : convert_revision :
4932ab507580e0c9f7012398e71921ce58fc3c4e
Gabe Black [Sun, 17 Dec 2006 16:15:37 +0000 (11:15 -0500)]
Added in the extended twin load format
src/arch/sparc/isa/decoder.isa:
Added the extended twin load instructions
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added stuff to implement the extended twin loads. This created alot of duplication which I'll deal with later.
--HG--
extra : convert_revision :
5d8bdaacbfe83d21d3a396ce30ace90aeefc54d8
Gabe Black [Sat, 16 Dec 2006 17:55:55 +0000 (12:55 -0500)]
Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/sparcfs
--HG--
extra : convert_revision :
c8718b3df72b8c951c24742e8ce517a93bc23fe9
Gabe Black [Sat, 16 Dec 2006 17:55:15 +0000 (12:55 -0500)]
Merge zizzer:/bk/sparcfs/
into zower.eecs.umich.edu:/eecshome/m5/sparcfs
--HG--
extra : convert_revision :
2764b356ef01d1fcb6ed272e4ef96179cd651d4e
Gabe Black [Sat, 16 Dec 2006 17:54:28 +0000 (12:54 -0500)]
Support for twin loads.
src/arch/sparc/isa/decoder.isa:
Changed the names of the twin loads to match the 2005 spec. They still use the old format though.
src/arch/sparc/isa/formats/mem/blockmem.isa:
Added code to generate twin loads
src/arch/sparc/isa/formats/mem/util.isa:
Added an alignment check for twin loads
src/arch/sparc/isa/operands.isa:
Comment explaining twin load operands.
--HG--
extra : convert_revision :
ad42821a97dcda17744875b1e5dc00a9642e59b7
Gabe Black [Sat, 16 Dec 2006 17:53:01 +0000 (12:53 -0500)]
Compiler error fix.
--HG--
extra : convert_revision :
39e2638a10bf3e821e8f3d4d8c664008c98fc921
Lisa Hsu [Fri, 15 Dec 2006 23:07:39 +0000 (18:07 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
a6a40a3bc2e07bc7828de08fa2ce1c847105483d
Lisa Hsu [Fri, 15 Dec 2006 23:02:23 +0000 (18:02 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
68e9bb607fbeb1ed0ea4192411e804dc8e6ddd95
Lisa Hsu [Fri, 15 Dec 2006 22:58:20 +0000 (17:58 -0500)]
small change to eliminate address range overlap.
--HG--
extra : convert_revision :
c8309a8774265a707c87c4f516bec1f81aff4a79
Lisa Hsu [Fri, 15 Dec 2006 22:55:47 +0000 (17:55 -0500)]
little fixes i noticed while searching for reason for address range issues (but these weren't the cause of the problem).
RangeSize as a function takes a start address, and a SIZE, and will make the range (start, start+size-1) for you.
src/cpu/memtest/memtest.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/lsq.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/simple/atomic.hh:
src/cpu/simple/timing.hh:
Fix RangeSize arguments
src/dev/alpha/tsunami_cchip.cc:
src/dev/alpha/tsunami_io.cc:
src/dev/alpha/tsunami_pchip.cc:
src/dev/baddev.cc:
pioSize indicates SIZE, not a mask
--HG--
extra : convert_revision :
d385521fcfe58f8dffc8622260937e668a47a948
Lisa Hsu [Fri, 15 Dec 2006 18:27:53 +0000 (13:27 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
2f11b5f9fa6356cbf9f98c8cd7d4f6fbfaf9d24d
Lisa Hsu [Fri, 15 Dec 2006 18:06:37 +0000 (13:06 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision :
92a865a90a7c3e251ed1443f79640f761b359c1d
Lisa Hsu [Fri, 15 Dec 2006 18:05:46 +0000 (13:05 -0500)]
some small general fixes to make everythign work nicely with other ISAs, now we can merge back with newmem.
exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
mmaped_ipr.hh:
fix for build
miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/sparc/miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/mips/mmaped_ipr.hh:
fix for build
src/cpu/exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
--HG--
extra : convert_revision :
c5b9d56ab99018a91d04de47ba1d5ca7768590bb
Lisa Hsu [Fri, 15 Dec 2006 18:01:06 +0000 (13:01 -0500)]
loadstore.isa:
this privilegedString is never used
--HG--
extra : convert_revision :
5e6881d467792b670e0009cee8d5e96bc7a79a95
Lisa Hsu [Fri, 15 Dec 2006 17:58:02 +0000 (12:58 -0500)]
tlb.cc:
fix namespace indentations
src/arch/alpha/tlb.cc:
fix namespace indentations
--HG--
extra : convert_revision :
327d5a1568ba60cab1c1ae4bb3963ea78dfe0176
Ali Saidi [Fri, 15 Dec 2006 06:49:41 +0000 (01:49 -0500)]
Use my range_map to speed up findPort() in the bus. The snoop code could still use some work.
--HG--
extra : convert_revision :
ba0a68bd378d68e4ebd80a101b965d36c8be1db9
Ali Saidi [Fri, 15 Dec 2006 06:48:09 +0000 (01:48 -0500)]
Optimized the TLB translations with some caching
--HG--
extra : convert_revision :
f79f863393f918ff9363b2c261f8c0dfec64312e
Ali Saidi [Fri, 15 Dec 2006 00:01:21 +0000 (19:01 -0500)]
flesh out twinx asis
fix TICK register reads
reduce the number of readmiscreg accesses,
implement tsb pointer stuff
src/arch/sparc/asi.cc:
flesh out twinx asis
src/arch/sparc/miscregfile.cc:
fix TICK register reads
src/arch/sparc/tlb.cc:
reduce the number of readmiscreg accesses,
implement tsb pointer stuff
--HG--
extra : convert_revision :
1995c3b04b7743c6122cbf8ded7c4d5de48fa3c8
Steve Reinhardt [Thu, 14 Dec 2006 06:04:36 +0000 (22:04 -0800)]
Split CachePort class into CpuSidePort and MemSidePort
and push those into derived Cache template class to
eliminate a few layers of virtual functions and
conditionals ("if (isCpuSide) { ... }" etc.).
--HG--
extra : convert_revision :
cb1b88246c95b36aa0cf26d534127d3714ddb774
Lisa Hsu [Wed, 13 Dec 2006 22:52:24 +0000 (17:52 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
8cf3e824e4892249b12ed0fd92bb310748b18fa2
Lisa Hsu [Wed, 13 Dec 2006 22:51:28 +0000 (17:51 -0500)]
fix MiscRegFile::readRegWithEffect, which neglected the MISCREGS.
--HG--
extra : convert_revision :
4fdffe01b8e63e24b97a2e4194c747e6cf5e25ba
Lisa Hsu [Wed, 13 Dec 2006 19:33:59 +0000 (14:33 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
82733f9c7bf833cf6bbfbd2aad292f69f52d21bc
Lisa Hsu [Wed, 13 Dec 2006 19:33:32 +0000 (14:33 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
c6d174716641f0b8286b8478bcb9053b3eec54e3
Lisa Hsu [Wed, 13 Dec 2006 02:19:51 +0000 (21:19 -0500)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
--HG--
extra : convert_revision :
6e58629b1e51f1fc493a89f16c3f2e676dc5d191
Kevin Lim [Tue, 12 Dec 2006 22:55:50 +0000 (17:55 -0500)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress
--HG--
extra : convert_revision :
d420ee86454b72b0e5d3a98bac3b496f172c1788
Ali Saidi [Tue, 12 Dec 2006 22:55:27 +0000 (17:55 -0500)]
Fix bugs in tlbmap (and thus rangemap since the code is nearly identical)
Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing)
Fix tcc instruction igoner in legion-lock stuff to be correct in all cases
Have console interrupts warn rather than panicing until we figure out what to do with interrupts
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
add a magic miscreg which reads all the bits the tlb needs in one go
src/arch/sparc/tlb.cc:
initialized the context type and id to reasonable values and handle block init stores
src/arch/sparc/tlb_map.hh:
fix bug in tlb map code
src/base/range_map.hh:
fix bug in rangemap code and add range_multimap
(these are probably useful for bus range stuff)
src/cpu/exetrace.cc:
fixup tcc ignore code to be correct
src/dev/sparc/t1000.cc:
make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out
src/unittest/rangemaptest.cc:
fix up the rangemap unit test to catch the missing case
--HG--
extra : convert_revision :
70604a8b5d0553aa0b0bd7649f775a0cfa8267a5
Kevin Lim [Tue, 12 Dec 2006 22:35:46 +0000 (17:35 -0500)]
Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit).
This fixes a minor bug when multiple FU completions come back out of order (due to the order in which the FUs are freed up), and the oldest redirect isn't recorded properly. The eon benchmark should run now.
src/cpu/o3/iew_impl.hh:
Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit).
--HG--
extra : convert_revision :
b7d202dee1754539ed814f0fac59adb8c6328ee1
Steve Reinhardt [Tue, 12 Dec 2006 17:58:40 +0000 (09:58 -0800)]
Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
--HG--
extra : convert_revision :
b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
Steve Reinhardt [Tue, 12 Dec 2006 17:54:59 +0000 (09:54 -0800)]
If no tests are specified for regression, just build the binaries
(instead of complaining and exiting).
--HG--
extra : convert_revision :
24ac0bab7fd92d9e74c80847a667f0affcd0473d
Steve Reinhardt [Tue, 12 Dec 2006 07:21:03 +0000 (02:21 -0500)]
Get rid of unused lock code.
--HG--
extra : convert_revision :
a8030132268662ca54f487b8d32d09ba224317a8
Kevin Lim [Tue, 12 Dec 2006 04:51:21 +0000 (23:51 -0500)]
Fix up in case a req hasn't yet been generated for this instruction (if there was a fault prior to translation).
--HG--
extra : convert_revision :
43f4ea5e6a234cc6071006eab72135c11b8523c8
Kevin Lim [Tue, 12 Dec 2006 04:47:30 +0000 (23:47 -0500)]
Fix for fetch to use the icache's block size to generate proper access size.
--HG--
extra : convert_revision :
0f292233ac05b584f527c32f80e3ca3d40a6a2c1
Steve Reinhardt [Sun, 10 Dec 2006 07:05:33 +0000 (02:05 -0500)]
Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3
--HG--
extra : convert_revision :
c961d1bf2acaae6807870b78f444a4a606be65cc
Steve Reinhardt [Sun, 10 Dec 2006 07:04:53 +0000 (02:04 -0500)]
Reorder CacheTags members for better cache performance.
--HG--
extra : convert_revision :
cac6e9d447675805e3fcc4342e3bfdbef179fbf5
Steve Reinhardt [Sun, 10 Dec 2006 06:52:18 +0000 (01:52 -0500)]
Get rid of dummy 'hello world' outputs.
--HG--
extra : convert_revision :
e03634b5ec6b3c855c463618968984b5df7782f9
Steve Reinhardt [Sun, 10 Dec 2006 06:50:12 +0000 (01:50 -0500)]
Delete parser reference outputs so that test will no longer be run.
Runtimes are way too long with current inputs.
--HG--
extra : convert_revision :
19323308b40fb7de00c77ee552e39ca6558804b8
Steve Reinhardt [Sun, 10 Dec 2006 06:42:31 +0000 (01:42 -0500)]
Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache3
--HG--
extra : convert_revision :
7c78ae3298645aed2179ed4f2aa361619406f9de
Steve Reinhardt [Sun, 10 Dec 2006 06:42:16 +0000 (01:42 -0500)]
Add '-j' option directly to regress script (passed to scons).
--HG--
extra : convert_revision :
9776806b24da70b815280e47d2d5ec8674c82669
Steve Reinhardt [Sun, 10 Dec 2006 06:05:30 +0000 (22:05 -0800)]
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2
--HG--
extra : convert_revision :
e1ed5c8edb95e99200b4d26317f55f71338a96df
Ali Saidi [Sat, 9 Dec 2006 23:27:54 +0000 (18:27 -0500)]
fix lisa's hand merge
--HG--
extra : convert_revision :
d25604156ae0b2cf29d92fb960b8f5d77427985b
Ali Saidi [Sat, 9 Dec 2006 23:00:49 +0000 (18:00 -0500)]
Merge zizzer:/bk/sparcfs
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
c51fd95f7acd7cffb3ea705d7216772f0a801844
Ali Saidi [Sat, 9 Dec 2006 23:00:40 +0000 (18:00 -0500)]
Allocate the correct number of global registers
Fix fault formating and code for traps
fix a couple of bugs in the decoder
Cleanup/fix page table entry code
Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents
Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data
src/arch/sparc/faults.cc:
Fix fault formating and code for traps
src/arch/sparc/intregfile.hh:
allocate the correct number of global registers
src/arch/sparc/isa/decoder.isa:
fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate
src/arch/sparc/pagetable.hh:
cleanup/fix page table code
src/arch/sparc/tlb.cc:
implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents
src/arch/sparc/tlb.hh:
add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging
src/cpu/exetrace.cc:
dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.
--HG--
extra : convert_revision :
d7d771900f6f25219f3dc6a6e51986d342a32e03
Lisa Hsu [Fri, 8 Dec 2006 20:07:26 +0000 (15:07 -0500)]
Merge zizzer:/bk/sparcfs
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5
src/arch/sparc/ua2005.cc:
hand merge
--HG--
extra : convert_revision :
5157fa5d7053cb93f73241c63871eaae6f58b8a6
Lisa Hsu [Fri, 8 Dec 2006 19:37:31 +0000 (14:37 -0500)]
mostly implemented SOFTINT relevant interrupt stuff.
src/arch/sparc/interrupts.hh:
add in thread_context.hh to get access to tc.
get rid of stubs that don't make sense right now.
implement checking and get softint interrupts
src/arch/sparc/miscregfile.cc:
softint should be OR-ed on a write.
src/arch/sparc/miscregfile.hh:
add some enums for state fields for easy access to bitmasks of HPSTATE and PSTATE regs.
src/arch/sparc/ua2005.cc:
implement writing SOFTINT, PSTATE, PIL, and HPSTATE properly, add helpful info to panic for bad reg write.
--HG--
extra : convert_revision :
d12d1147b508121075ee9be4599693554d4b9eae
Ali Saidi [Thu, 7 Dec 2006 23:50:33 +0000 (18:50 -0500)]
get legion/m5 to first tlb miss fault
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
add sparc error asi
src/arch/sparc/faults.cc:
put a panic in if TL == MaxTL
src/arch/sparc/isa/decoder.isa:
Hpstate needs to be updated on a done too
src/arch/sparc/miscregfile.cc:
warn istead of panicing of fprs/fsr accesses
src/arch/sparc/tlb.cc:
add sparc error register code that just does nothing
fix a couple of other tlb bugs
src/arch/sparc/ua2005.cc:
fix implementation of HPSTATE write
src/cpu/exetrace.cc:
let exectrate mess up a couple of times before dying
src/python/m5/objects/T1000.py:
add l2 error status register fake devices
--HG--
extra : convert_revision :
ed5dfdfb28633bf36e5ae07d244f7510a02874ca
Steve Reinhardt [Thu, 7 Dec 2006 19:41:56 +0000 (14:41 -0500)]
Change detault regression build from opt to fast.
--HG--
extra : convert_revision :
b6db0254b73a97ab6e3685c90cc9cd30ea274d4f
Ali Saidi [Thu, 7 Dec 2006 00:25:53 +0000 (19:25 -0500)]
Handle access to ASI_QUEUE
Add function for interrupt ASIs
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/asi.cc:
src/arch/sparc/asi.hh:
Add function for interrupt ASIs
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
Add QUEUE asi/misc registers
src/arch/sparc/regfile.cc:
add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/tlb.cc:
Handle access to ASI_QUEUE
--HG--
extra : convert_revision :
7a14450485816e6ee3bc8c80b462a13e1edf0ba0
Ali Saidi [Wed, 6 Dec 2006 19:29:10 +0000 (14:29 -0500)]
Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts
getting touched.
configs/common/FSConfig.py:
Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs
src/arch/isa_parser.py:
we should readmiscregwitheffect not readmiscreg
src/arch/sparc/asi.cc:
Fix AsiIsNucleus spelling with respect to header file
Add ASI_LSU_CONTROL_REG to AsiSiMmu
src/arch/sparc/asi.hh:
Fix spelling of two ASIs
src/arch/sparc/isa/decoder.isa:
switch back to defaults letting the isa_parser insert readMiscRegWithEffect
src/arch/sparc/isa/formats/mem/util.isa:
Flesh out priviledgedString with hypervisor checks
Make load alternate set the flags correctly
src/arch/sparc/miscregfile.cc:
insert some forgotten break statements
src/arch/sparc/miscregfile.hh:
Add some comments to make it easier to find which misc register is which number
src/arch/sparc/tlb.cc:
flesh out the tlb memory mapped registers a lot more
src/base/traceflags.py:
add an IPR traceflag
src/mem/request.hh:
Fix a bad assert() in request
--HG--
extra : convert_revision :
1e11aa004e8f42c156e224c1d30d49479ebeed28
Kevin Lim [Wed, 6 Dec 2006 19:23:31 +0000 (14:23 -0500)]
Fix for MIPS_SE/m5.fast compile.
--HG--
extra : convert_revision :
dbb893250974ac6db7b6c1ba67263fd35098ca43
Kevin Lim [Tue, 5 Dec 2006 16:12:18 +0000 (11:12 -0500)]
Override default SConscript options and only build the SimpleCPUs.
--HG--
extra : convert_revision :
cfcfb787d8442cb76ed766aa5bc947636f067209
Steve Reinhardt [Tue, 5 Dec 2006 15:24:13 +0000 (07:24 -0800)]
Merge zizzer.eecs.umich.edu:bk/newmem-cache2
into vm1.(none):/home/stever/bk/newmem-cache2
--HG--
extra : convert_revision :
0a7d17460f17c96fe869124f54f9c92409495003
Steve Reinhardt [Tue, 5 Dec 2006 15:23:20 +0000 (10:23 -0500)]
Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2
--HG--
extra : convert_revision :
a5569cef10ab22da1865e368f0bb5e7532772227
Steve Reinhardt [Tue, 5 Dec 2006 15:18:35 +0000 (10:18 -0500)]
Merge zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-cache2
--HG--
extra : convert_revision :
ca78bf2fc1ddefd56b98a90eaffab57d93026626
Steve Reinhardt [Tue, 5 Dec 2006 15:16:36 +0000 (07:16 -0800)]
Don't compress data on writebacks unless it's actually necessary.
--HG--
extra : convert_revision :
7a068e28f9ea2f6aab57be7133b47bda72d10302
Steve Reinhardt [Tue, 5 Dec 2006 05:35:48 +0000 (21:35 -0800)]
Merge vm1.(none):/home/stever/bk/newmem-head
into vm1.(none):/home/stever/bk/newmem-cache2
--HG--
extra : convert_revision :
e456687d940c833d8255a88633555778480f7825
Ali Saidi [Tue, 5 Dec 2006 01:29:55 +0000 (20:29 -0500)]
forgot to commit miscreg file
--HG--
extra : convert_revision :
c2ede9efbf7b264c32d5565d3f0fc0601c4cd63b
Gabe Black [Tue, 5 Dec 2006 00:56:04 +0000 (19:56 -0500)]
Merge zizzer:/bk/sparcfs
into zower.eecs.umich.edu:/eecshome/m5/newmemmid
--HG--
extra : convert_revision :
45d9599dd883e10c283812c1c241c20323f44cec