sim: Generalize the arrayParamOut and arrayParamIn functions.

These had been written specifically for the vector, list, set, and C
style array types. This change reworks them to share an implementation,
and to work with more general types. The arrayParamOut method requires
std::begin() and std::end() to accept that type, and the arrayParamIn
method requires either insert or push_back, or the type to be an array.

Also fix up a couple of files which accidentally depended on includes in
the serialize headers which are no longer necessary.

Change-Id: I6ec4fe3bb900603bbb4e35c4efa620c249942452
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36277
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: L1/L2 hit/miss tracking for MOESI_AMD_BASE/GPU_VIPER

L1 and L2 access tracking was not fully implemented.
This patch adds the missing tracking actions, and corrects
several errors for the ones that were there.

Change-Id: I69a59283274c08e94b6650ab5f586cbfe5432503
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33915
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

mem-ruby: L3 hit/miss tracking to MOESI_AMD_BASE-dir

L3 access tracking added to the directory controller.

This commit adds L3 hit/miss tracking to the controller.
Hit/miss status is decided when the tag array of the
L3 Cache is checked for the first time for any given request.

Change-Id: Icac122f59509d79135265fb38b112d3f47419b6f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33314
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Fix garnet network interface stats

Fixing a bug in garnet network interface where flit source delay is
computed using both tick and cycle.

Change-Id: If21a985f371a818611d13e9cd5ce344dbcf5fb2b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36416
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Matthew Poremba <matthew.poremba@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Update my email address.

Change-Id: Ibbed316125274b742dbcda62f114855176b922e8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36382
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Use absolute path for VirtIO9PDiod default root

VirtIO9PDiod model requires an absolute path as its parameter. So we
should change the default root path to absolute path as well.

Change-Id: I68a2ae1115e84ed61055298b06b2d0b4bd6410b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36381
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Fix FastmodelCluster cpu initialization

We should create the thread and the interrupt controller of fastmodel by
calling the create function explicitly.

Change-Id: I269440e144e83fa0a31d8cdf285fed31642f4f73
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36380
Reviewed-by: Earl Ou <shunhsingou@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Fix a few accidental transitive includes.

Some files depend on definitions from files that they weren't including
themselves. They were working accidentally by getting those definitions
transitively through other, unrelated headers.

Change-Id: I50c919a4eb6c4484d4ee6b7f4fe02f075132964d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36282
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Implement optParamIn using paramIn.

This means only paramIn needs to be specialized, and then optParamIn
will be as well for free. It also removes some duplicate implementation.

Change-Id: Id124a05d04e1c0897121d0e13dd46efe90e8eed0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36276
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Use getTlb in BaseMMU to reduce boilerplate

Change-Id: I22dcdf0769e854c252788d415d46da113cb8c60a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35735
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Replace any getDTBPtr/getITBPtr usage

The getMMUPtr should be used instead

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I8f09b0dc9844764fbe1a04b34dd963730c91f531
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34978
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Remove unused demapInstPage and demapDataPage

Change-Id: Iecc2ee8d91bfd3caf38e5f27e9689b7e0d488ed5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34977
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: BaseCPU using ArchMMU instead of ArchDTB/ArchITB

With this commit we replace every TLB pointer stored in the
cpu model with a BaseMMU pointer.

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I4932a32f68582b25cd252b5420b54d6a40ee15b8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34976
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-kvm, arch-x86: Fix KVM on Intel platforms

This is the minimal set of changes from the patch that's been floating
around for a few years originally by Mike Upton.

See http://reviews.gem5.org/r/2613/ and
https://gem5-review.googlesource.com/c/public/gem5/+/7361

The change to the tssDesc is the minimal change to get KVM working on
Intel platforms. However, the other changes seem prudent to add.

Tested on both Intel (i7-7700) and AMD (EPYC 7451) platforms.

Change-Id: I000c7ba102ba161c2bb5e224bf826216cf0ff87a
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12278
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Adding a SRAM in VExpress_GEM5_V1

This is added in order to match the RS1 memory map

JIRA: https://gem5.atlassian.net/browse/GEM5-768

Change-Id: I51e7aeafe1468a68fe7a3d78c7a6c405114df88f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34375
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Raise an exception when scons is run a Python2 environment

As gem5 has started to use Python2 incompatible features, compiling
gem5 in a Python2 environment results in an error.

This commit addresses this issue by raising an Exception when scons
is run in a Python2 environment, and adding a few pointers on how to
install Python3 and on how to use scons in a Python3 environment. The
solution works in a system where both Python2 and Python3 are
installed.

JIRA: https://gem5.atlassian.net/browse/GEM5-797

Change-Id: I98d4a39f586f39d9253ab2517b77e86c5ed19466
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36157
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Minor updates to CONTRIBUTING.md

This brings the file slightly more up to date

Change-Id: I1ed3300ec3c4980ed22c6a6fb950fa724897906b
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36255
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Wrap __attribute__((aligned())) in a macro in compiler.hh.

This attribute is gcc specific (also implemented by clang for
compatibility), and so should be behind a level of abstraction to make
using different compilers easier.

Change-Id: I7495f011f617268dd7a589dc0bcf1b3b7f515046
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35976
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Use compiler.hh macros when available.

Some places were hand coding __attribute__s when macros in compiler.hh
were available to do that job. Using the macros helps abstract away
compiler specific details and should be used when possible.

Change-Id: I94befebcfde2d673e874e9959588f69781bd9021
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35975
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implement ArmPMU DTB generation

This has been implemented by following Linux documentation:

Documentation/devicetree/bindings/arm/pmu.txt

Change-Id: I22583eed3792d5828f9c260e952ec5e8cf9e118b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35476
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev: Use generateFdtProperty in the PioDevice

Change-Id: I2126bf84e0648fe76570f9645179f90bdf79eb41
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35398
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Use generateFdtProperty in the GenericTimer

Change-Id: I4115d14ba65685627b51b0e5438fe5a3ed9328bc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35397
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Automate FdtProperty generation with ArmInterruptPin

Change-Id: I1963bd139d8abd8988d5ceedaf85c74279546078
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35396
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm, fastmodel: Rewrite Gic.interruptCells

The affinity number (aka PPI partition) is used differently
in GICv2 and GICv3. In GICv2 it is ORed to the triggering type
(3rd cell), whereas it is encoded in the 4th cell in GICv3

Change-Id: I36e45d4ec5fb39befa1a271b531dfed2d8e56c10
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36235
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Define ArmInterruptType

This is a scoped enum meant to be used mainly in the python world
for DTB autogeneration. By making an ArmInterruptPin self aware of
its own type, we can use it in the C++ world when modelling devices.

For example if a device spec is enforcing a specific triggering behaviour,
its gem5 implementation can query the interrupt type and panic if its
expectations are not met. In this way we are sure what the Linux kernel
sees in the DTB is in sync with how the model really behaves

Change-Id: I66ae3cfbc7b1ed94804f1f882c12eb31f70840da
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35395
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Make GPU_VIPER config python3 friendly

There is no xrange in python3. This will be required when eventually
20.2 is released.

Change-Id: I3a0da6353b70e6e17ce1f77d6177d48059e32487
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35855
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: python3 compatibility for apu_se

This patch changes xrange to range, as the former doesn't exist in
python3.

Change-Id: Ibe2c1fb073194e3e0713bb1718f2e323f7c4e397
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36159
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Update GCN dockerfile for python3

This patch installs python3 in the GCN dockerfile, due to python3
being required starting in 20.2.

Python2 (python-yaml) is still required in order to compile rocBLAS

Change-Id: I1a6f1707e076e8ca499804119447a8d1f237ffd4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36158
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim,python: Flip logic on loopback listeners

People are bitten by allowing external connections to gem5 runs too often
(it happend to me again today). This change flips the logic so the
default is to only allow localhost connections.

Change-Id: If9233f5ca383721017b30b5837a26c5042d925fd
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36175
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Rework how PCI BARs are set up in python and C++.

In python, the BARs had been configured using three arrays and a scalar
parameter. The arrays tracked the BAR value in the config, whether the
BAR was for a "legacy" IO range, and the size of the BAR, and the
scalar parameter was an offset for the "legacy" IO addresses to map
into the host physical address space. The nature of a BAR was implied
by its raw config space value, with each of the control bits (IO vs.
memory, 64 bit, reserved bits) encoded directly in the value.

Now, the BARs are represented by objects which have different types
depending on what type of BAR they are. There's one for IO, one for
memory, one for the upper 32 bits of a 64 bit BAR (so indices work
out), and one for legacy IO ranges. Each type has parameters which
are appropriate for it, and they're parameters are all grouped together
as a unit instead of being spread across all the previous values.
The legacy IO offset has been removed, since these addresses can be
offset like any other IO address. They can be represented naturally
in the config using their typical IO port numbers, and still be turned
into an address that gem5 will handle correctly in the back end.

Unfortunately, this exposes a problem in the config system where
a VectorParam can't be overwritten successfully one element at a time,
at least when dealing with SimObject classes. It might work with
actual SimObjects in a config, but I haven't tried it. If you were
to do that to, for instance, update the BARs for x86 so that they
used legacy IO ports for the IDE controller, it would complain that
you were trying to instantiate orphaned nodes. Replacing the whole
VectorParam with a new list of BAR objects seems to work, so that's
what's implemented in this change.

On the C++ side, BARs in the config space are treated as flat values
on reads, and are stored in the config structure associated with each
PCI device. On writes, the value is first passed to the BAR object,
and it has a chance to mask any bits which are fixed in hardware and
update its idea of what range it corresponds to in memory.

When sending AddrRanges up to the parent bus to set up routing, the
BARs generate each AddrRange if and only if their type has been
enabled in the config space command register. The BAR object which
represents the upper 32 bits of a 64 bit BAR does not claim to be
IO or memory, and so doesn't contribute a range. It communicates with
the BAR which represents the lower 32 bits, so that that BAR has the
whole base address.

Since the IO or memory BAR enable bits in the command register are now
handled by the PCI device base class, the IDE controller no longer has
to handle that manually. It does still need to keep track of whether
the bus master functionality has been enabled though, which it can
check when those registers are accessed.

There was already a mechanism for decoding addresses based on BARs
in the PCI device base class, but it was overly complicated and not
used consistently across devices. It's been consolidated, and used in
most places where it makes sense.

Finally, a few unnecessary values have been dropped from the base PCI
device's and IDE controller's checkpoint output. These were just local
copies of information already in the BARs, which in turn are already
stored along with the data in the device's config space.

Change-Id: I16d5f8cdf86d7a2d02a6b04d1f9e1b3eb1dd189d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35516
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute,mem-ruby: Properly create/handle WriteCompletePkts

There is a flow of packets as so:
WriteResp -> WriteReq -> WriteCompleteResp

These packets share some variables, in particular senderState and a
status vector.

One issue was the WriteResp packet decremented the status vector, which
was used by the WriteCompleteResp packets to determine when to handle
the global memory response. This could lead to multiple
WriteCompleteResp packets attempting to handle the global memory
response.

Because of that, the WriteCompleteResp packets needed to handle the
status vector. this patch moves WriteCompleteResp packet handling back
into ComputeUnit::DataPort::processMemRespEvent from
ComputeUnit::DataPort::recvTimingResp. This helps remove some redundant
code.

This patch has the WriteResp packet return without doing any status
vector handling, and without deleting the senderState, which had
previously caused a segfault.

Another issue was WriteCompleteResp packets weren't being issued for
each active lane, as the coalesced request was being issued too early.
In order to fix that, we have to ensure every active lane puts their
request into their applicable coalesced request before issuing the
coalesced request. Because of that change, we change the issuing of
CoalescedRequests from GPUCoalescer::coalescePacket to
GPUCoalescer::completeIssue.

That change involves adding a new variable to store the
CoalescedRequests that are created in the calls to coalescePacket. This
variable is a map from instruction sequence number to coalesced
requests.

Additionally, the WriteCompleteResp packet was attempting to access
physical memory in hitCallback while not having any data, which
caused a crash. This can be resolved either by not allowing
WriteCompleteResp packets to access memory, or by copying the data
from the WriteReq packet. This patch denies WriteCompleteResp packets
memory access in hitCallback.

Finally, in VIPERCoalescer::writeCompleteCallback there was a map
that held the WriteComplete packets, but no packets were ever being
removed. This patch removes packets that match the address that was
passed in to the function.

Change-Id: I9a064a0def2bf6c513f5295596c56b1b652b0ca4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33656
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Remove dangling reference to bus port in devices.py

Change-Id: I3f7b65a9e6d4ae88acc474bb0e3a55f28c3cd09b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35755
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Clean up some #ifs in _format_string.

These were checking for gcc version 3, well below the minimum version we
support, and were hard wired to be enabled anyway. This change gets rid
of the check and the dead code on the hard wired off branch.

Also, this change cleans up the style in the surviving code and
simplifies it slightly.

Change-Id: I8df73a378f478413c111a4dea962450a37fb4092
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35977
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Standardize the way create() constructs SimObjects.

The create() method on Params structs usually instantiate SimObjects
using a constructor which takes the Params struct as a parameter
somehow. There has been a lot of needless variation in how that was
done, making it annoying to pass Params down to base classes. Some of
the different forms were:

const Params &
Params &
Params *
const Params *
Params const*

This change goes through and fixes up every constructor and every
create() method to use the const Params & form. We use a reference
because the Params struct should never be null. We use const because
neither the create method nor the consuming object should modify the
record of the parameters as they came in from the config. That would
make consuming them not idempotent, and make it impossible to tell what
the actual simulation configuration was since it would change from any
user visible form (config script, config.ini, dot pdf output).

Change-Id: I77453cba52fdcfd5f4eec92dfb0bddb5a9945f31
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35938
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: Add support for comma-separated inputs of testlib argparser

Currently, the --isa, --variant and --length options of testlib
do not support comma-separated inputs. This commit adds the
support for such an input for those options.

The argument parser now supports specifying the parameters multiple
times as well as specifying multiple options at a time.

JIRA: https://gem5.atlassian.net/jira/software/c/projects/GEM5/issues/GEM5-770

Change-Id: I3c276a9b9d9c6b0b802ecf8e7f1f9a3dfafe45d1
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34198
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

cpu: Remove automatic overriding of numThreads in SE on O3.

On the O3 CPU, when the number of threads on the CPU (SMT) is too low to
hold all the old style CPU workload items, then it would increase the
number of threads to match. There are three problems with this.

1. This behavior was only implemented on O3.
2. It could silently hide a bug in the config where the number of
   workload items was accidentally too big.
3. It makes the DerivO3CPUParams struct tamper with itself in the
   create() method, which means not even config.ini will accurately
   reflect the actual config of the system.

Change-Id: I0aab70d4b98093f7f14156ca437e763f031049ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35937
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implement Armv8.2-LPA

This is enabled by setting the ArmSystem.phys_addr_range64 to 52.
This will automatically set the ID_AA64MMFR0_EL1.PARange to 0b0110
which encodes the presence of Armv8.2-LPA

Change-Id: If9b36e26cd2a72e55c8e929a632b7b50d909b282
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35956
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Implement Armv8.2-LVA

Change-Id: I1b489a3629b2376e03e79b158631cb1d0cacc17e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35955
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Use the new M5_WEAK macro to hide [[gnu::weak]].

Other compilers may need to support that macro in other ways.

Change-Id: If6ee05ce69c1bfd24108cf0785fac2d7bc259f0a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35940
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

base: Add an M5_WEAK macro to compiler.hh.

On gnu compatible systems, this will be implemented with the
[[gnu::weak]] attribute.

Change-Id: I1add373d648bbca24feab63420a9d87363646b6a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35939
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

fastmodel: Update to c++14, and add some missing consts.

During the review for the CortexR52 model, a comment pointed out where
two consts can be added. Also we switched gem5 over to c++14, but the
project files for these other wrappers were still set to c++11.

Change-Id: I5fecdc896b0290deadcd0f55ea1dfe3806a98177
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35857
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Remove a call to reduce() from code_formatter.py.

The built in reduce method is no longer available in python 3. Besides
that, this particular bit of code is simpler and easier to read if
reduce is replaced with the also built in sum() method.

Change-Id: I6daca42494ea0534721dfcfb1f6058517cd482d9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35941
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Change how O3 handles requests for SMT in full system.

Currently, when the numThreads parameter is set to something larger than
1 in full system mode, the O3 CPU will just silently change it back down
again to 1. This could be confusing to the user since it won't be
immediately apparent, even when looking at config.ini, that their config
isn't being respected.

This change moves that check into the CPU constructor, where CPU
behavior probably should be rather than the create() method which should
just build the object, and also turns it into an error.

Change-Id: I627ff8702b5e8aaad8839aa8d52524690be25619
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35936
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Remove the "SingleThreaded" fetch policy from the O3 CPU.

The fetch policy is only meaningful for SMT simulations. The
"SingleThreaded" value is a placeholder which is the default, and is
only supposed to be used in non-SMT simulations.

Rather than have this enum value and have special checks for it in
various places in O3, we can just eliminate it and set the default,
which is still only meaningful in SMT simulations, be an SMT fetch
policy.

The DerivO3CPUParams::create() function would forcefully change the
the fetch policy from "SingleThreaded" to "RoundRobin" anyway if there
were more than one thread, so that can be the actual default instead of
the shadow effective default.

Change-Id: I458fda00b5bcc246b0957e6c937eab0c5b4563c3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35935
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Remove an extra file in src/cpu

Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Change-Id: Iacbf202bc4c4e701b8c6d3a7eaae77d15ca5f397
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35895
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: allow qualifiers in SLICC functions

All parameters in functions defined within SLICC are const& by default
(except for the implicit types, e.g. TBE). This allow us to specify
if we want to pass parameters as & or const&. Default behavior is
maintained.

A use case is to allow refactoring of common code in actions that
enqueue messages. Messages can be passed as a non-const ref. to
to functions with common initialization. E.g.:

void initRequestMsg(RequestMsg & out_msg) {
  // Common msg init code
}

action(sendRequest1, ...) {
  enqueue(...) {
    initRequestMsg(out_msg);
    // Request1 specific code
  }
}

action(sendRequest2, ...) {
  enqueue(...) {
    initRequestMsg(out_msg);
    // Request2 specific code
  }
}

Change-Id: Ic6a18169a661b3e36710b2a9f8a0e6bc5fce40f8
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31259
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: more specialized address to node mapping

Added mapAddressToDownstreamMachine that may be used by the protocols
to map an address to different target donwstream controller of the same
type.

These functions do not use the global mapping provided by the network
and map addresses to one of the controllers specified in the
downstream_destinations parameter.

This change facilitates reusing the same cache state-machine/controllers
to model different levels of the cache hierarchy.

Change-Id: I9a202e9461e0d2f16ed232ff8b60bbde2d15570d
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31415
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Expose MessageBuffer methods

SLICC interface for checking the capacity of MessageBuffers

Change-Id: I28e2d22a405d33fcbe6a183dffc31bd936fa26c4
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31271
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: add addressOffset util

Returns the offset of an address with respect to a base address.
Looks unnecessary, but SLICC doesn't support casting and the '-'
operator for Addr types, so the alternative to this would be to add
more some helpers like 'addrToUint64' and 'uint64ToInt'.

Change-Id: I90480cec4c8b2e6bb9706f8b94ed33abe3c93e78
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31270
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Add a wrapper for the CortexR52.

There has been some testing of this wrapper, but some components are
missing. It's not currently possible to read or set Misc registers,
64 bit integer registers, flattened integer registers, or vector
registers. In some cases that's because no mapping from gem5 indexes
to IRIS resource names has been set up, but in some cases, since R52
is 32 bit, no mapping *can* be set up, and we need to figure out what
to do with requests for 64 bit only state.

Change-Id: I2d650a7c1765b39f25058727502c96e6de5aa26b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35635
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a copyright to gem5img.py.

This script was ported to python from a bash script by me back in 2011.
The original file didn't have a copyright, but since I made significant
modifications to it (porting it to python, improving its features), at
least those modifications should have become copyright Google.

Change-Id: Ia70bb1e6be5b188537bcf6899ba5884b359dbe18
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35875
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs,tests: Update configs to use compatible SE workloads.

If there's no more compatible workload than the base SEWorkload class it
will fall back to that for now.

Change-Id: Id27172c3074a7976823a891878ab9eecf6246c47
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33901
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Use finditer in the (Sub)OperandList classes.

This method returns an iterator which goes through all the
non-overlapping matches for the given RE, without having to hand code
that same behavior with the more basic "search" method.

Change-Id: I4c4d95cfc8f72125566222aebb56604c3e9e2b03
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35817
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Pull the (Sub)OperandList classes into their own file.

Another step in breaking down the isa parser into more manageable parts.

Change-Id: I0c5e70fe481bd17c0069b768129731e99a93ed0d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35816
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Create ReplacementPolicy namespace

Encapsulate the replacement policy classes in their own namespace.

As a side effect these classes have been renamed to drop the RP
suffix in the C++ code.

Change-Id: Ibb65dfb584a1413492fcf11833cf91a859cbff4e
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35795
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: detailed transaction latency profiling

Add incomingTransactionStart/End and outgoingTransactionStart/End
functions that can be called from the protocol to profile events
that initiate a transaction locally (e.g. an incoming request) and
remotely (e.g. outgoing requests). The generated stats will include
histograms of the latency for completing each type of transaction.

This assumes assumes the protocol uses different trigger events for
initiating incoming and outgoing transactions.

Change-Id: Ib528641b9676c68907b5989b6a09bfe91373f9c9
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31421
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: expose transition info to actions

SLICC compiler generates the curTransitionEvent and
curTransitionNextState functions, which allows actions to check which
event triggered the current transition and what's the next state.

Change-Id: I79c8c4f2839633b7fb3b23cbbdbb32f25db90eab
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31420
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: change MessageBuffer randomization param

There are cases in which we need to prevent randomization for a
specific buffer when enabled at the RubySystem level (e.g. a internal
trigger queue that requires zero latency enqueue, while other buffers
can be randomized).

This changes the randomization parameter to support enabling and
disabling randomization regardless of the RubySystem setting.

Change-Id: If7520153cc5864897fa42e8911a6f8acbcf01db5
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31419
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: sequencer callback for unique writes

A controller may complete a write without obtaining a full copy of
the line. This patch adds a specific callback for this purpose that
prevents reads to be coalesced with a write on a potentially incomplete
line.

Change-Id: I3775f81699f38e406fee28f92c9c8e06deb3d528
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31269
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bradford Beckmann <bradford.beckmann@gmail.com>

mem-ruby: move AddrRange propagation to RubyPort

Doing the master address range notification from the RubyPort.
This allows us the DMASequencer to be replaced by Sequencer in future
protocols.

Change-Id: I95edb54b39a8adf0cac5caf2b58e4a2efb573f56
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31268
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Sequencer can be used without cache

Moved the dcache check to the LLSC functions that use it.
This allows a Sequencer to be coupled with a gem5 object
that does not need a cache (as long as it doesn't issue
LLSC instructions).

Also, icache was not used at all so it was removed.

Change-Id: I04bd2711f8d0a7dfc952cff8e0020d2d1881cae1
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31267
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bradford Beckmann <bradford.beckmann@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: int to Cycle converter

Change-Id: I493b16a0bdd01a4cef4891e273a376ebe9509fe8
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31266
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: support for template types in structs

Templated types can now be used within structures defined in SLICC.
Usage is similar to the TBETable: the templated type must have all
possible methods in it's SLICC definition. Eg.:

structure(Map, desc="Template map definition") {
    MachineID lookup(Addr);
    MachineID lookup(int);
}

structure(SomeType, desc="Some other struct definition") {
    MachineID addrMap, template="<Addr,MachineID>";
    MachineID intMap, template="<int,MachineID>";
}

Change-Id: I02a621cea5e4a89302762334651c6534c6574e9d
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31264
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Reviewed-by: Bradford Beckmann <bradford.beckmann@gmail.com>
Maintainer: Bradford Beckmann <bradford.beckmann@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: added function to check addr range

respondsTo checks if a controller address ranges includes a given
address.

Change-Id: I9a320011d93e7fd8df1ad3bda75c85d314261a99
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31263
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bradford Beckmann <bradford.beckmann@gmail.com>

mem-ruby: missing method in NetDest interface

Change-Id: Ibf651c37c50174186daebebc06aa115e6bc2ed33
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31262
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Bradford Beckmann <bradford.beckmann@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: added %(mod) operator to SLICC

Change-Id: I9d1a10824ced3723d13e2843ad739ced72e476ce
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31260
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Minor cleanup of imports in isa_parser.py.

The with statement and print function are no longer in the future, and
the "inspect" module is not used. Also alphabetize the imports.

Change-Id: I35f2b7b0f7495cb9ca79d2cbe05f020560ec3593
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35280
Reviewed-by: Steve Reinhardt <stever@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Split utility methods/variables out of the ISA parser.

Change-Id: Ifbff4bc6633cd11f98b02ba1291a91c3ad189285
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35279
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Split the operand types out of the ISA parser.

These conceptually go together and don't depend on any other parts of
the parser.

Change-Id: Ia8bff0d0ec210bdeeb080808968faf9528ee03dd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35278
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Move the ISA parser into a package.

This will make splitting the parser into components easier, since it
will keep help keep everything together and organized.

Change-Id: I737641e124b6da8b1b18a49de9110c8424d8cc4f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35277
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Change how IO port devices are structured in the PC platform.

Before, for historical reasons, the PCI host device was the default
responder on the IO bus, meaning that when there was any type of
transaction which didn't have a device to go to, it would end up
looking like a PCI config transaction. It's very unlikely that this is
what it actually was, and what would happen would be arbitrary and
probably not helpful.

Also, there was no device in place to respond to accesses in x86's IO
port address space. On a real system, these accesses just return junk
and are otherwise legal. On systems where there would be physical bus
wires they would probably return whatever the last data on the bus was.

This would have been helpful when the platform was first being set up
because it would make it obvious when the OS tried to access a device
that wasn't implemented, but there were a few cases where it would
purposefully fiddle with ports with nothing on them. These had one off
backing devices in the config which would handle the accesses
harmlessly, but if the OS changed and tried to access other ports, the
configs would need to be updated.

Now, the PCI host is just another device on the bus. It claims all of
the PCI config space addresses, so any config access, even ones which
don't go with a device, will go to it, and it can respond with all 1s
like it's supposed to.

In it's place, the default responder is now a bus. On that bus is
a device which responds to the entire IO port address range with 0s.
The default on *that* bus is a device which will mark any accesses
as bad.

With this setup, accesses which don't go to a device, including a
device on the IO port address space, will go to the IO bus's default
port. There, if the access was an IO access, it will go to the device
which replies successfully with all 0s. If not, it's marked as an
error.

The device which backs the entire IO address space doesn't conflict
with the actual IO devices, since the access will only go towards it
if it's otherwise unclaimed, and the devices on the default bus don't
participate in routing on the higher level IO bus.

Change-Id: Ie02ad7165dfad3ee6f4a762e2f01f7f1b8225168
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35515
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

stats: Output new-world stats before legacy stats

Now that global stats have been converted to new-style stats, it's
desirable to output them before legacy stats. This ensures that global
statistics (e.g., host_seconds) show up first in the stat file.

Change-Id: Ib099d0152a6612ebbadd234c27f2f3448aef1260
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35617
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim, stats: Move global stats to Root

Global stats are currently exposed using the legacy stat system (i.e.,
without a parent group). This change moves global stats from
stat_control.cc to a group that gets exported from the Root object.

The implementation adds the Root::Stats class which has a single
global instance. This instance is exposed to the rest of the simulator
using the global rootStats symbol. The intention is that objects that
need global statistics in formulas access them through the rootStats
object.

The global names simSeconds, simTicks, simFreq, and hostSeconds are
now references to their respective members in the rootStats object.

Change-Id: I267b5244a0bcca93dd2dcf03388e7085bdd79c9e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35616
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Simplify Ruby prefetcher's filter access functions

The signatures request many things that do not need to be passed
around.

Change-Id: If780e848b19056c9213092b6fc8673bd4f37b65f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24534
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Use CircularQueue for prefetcher's non unit filter

Ruby prefetcher's non-unit filter is a circular queue, so use the class
created for this functionality.

This changes the behavior, since previously iterating through the
filter was completely arbitrary, and now it iterates from the
beginning of the queue to the end when accessing and updating
the filter's contents.

Change-Id: I3148efcbef00da0c8f6cf2dee7fb86f6c2ddb27d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24533
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Use CircularQueue for prefetcher's unit filter

Ruby prefetcher's unit filter is a circular queue, so use the class
created for this functionality.

This changes the behavior, since previously iterating through the
filter was completely arbitrary, and now it iterates from the
beginning of the queue to the end when accessing and updating
the filter's contents.

Change-Id: I834be88a33580d5857c38e9bae8b289c5a6250b9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24532
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Build the operand REs in the isa_parser on demand.

These regular expressions search code snippets to find places where
operands are used. Rather than build them explicitly at the end of
processing the operands{{}} construct, wait until they're first going to
be used. That way, we'll be able to define operands in as many places as
we want, as long as we've done all we're going to do before the first
instructions are defined.

This will pave the way to defining operands in regular python in let
blocks, and then possibly outside of the parser altogether, perhaps into
scons where having lots of output files for individual instructions will
be easier to manage. For now, this just lets you define multiple
operands blocks which is not all that exciting on its own :)

Change-Id: I1179092316c1c0ac2613810bfd236a32235502fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35237
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Steve Reinhardt <stever@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: fix include dependency

Removed include dependency between WriteMask and RubySystem.

Change-Id: I3e81267341e3875b1bb0fc3cb39f1a308e383dfd
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31258
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: additional WriteMask methods

Change-Id: Ib5d5f892075b38f46d1d802c043853f56e19ea12
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31257
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Network can use custom data msg size

The size for network data messages can be set using a configuration
parameter. This is necessary so line transfers may be split in multiple
messages at the protocol level.

Change-Id: I86a272de597b04a898071db412b921cbe1651ef0
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31256
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Allow same-cycle enqueue

Messages may be enqueued and be ready in the same cycle.

Using this feature may introduce nondeterminism in the protocol and
should be used in specific cases. A case study is to avoid needing an
additional cycle for internal protocol triggers (e.g. the All_Acks
event in src/mem/ruby/protocol/MOESI_CMP_directory-L2cache.sm).
To mitigate modeling mistakes, the 'allow_zero_latency' parameter must
be set for a MessageBuffer where this behavior is acceptable.

This changes also updates the Consumer to schedule events according to
this new behavior. The original implementation would not schedule a new
wakeup event if the wakeup for the Consumer had already been executed
in that cycle.

Additional authors:
- Tuan Ta <tuan.ta2@arm.com>

Change-Id: Ib194e7b4b4ee4b06da1baea17c0eb743f650dfdd
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31255
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: MessageBuffer capacity check

Trip assert if call enqueue on a full message buffer.

Change-Id: I842183d8bf2c681787f1b6ac23c95825095ad05d
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31254
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>

mem-cache: Encapsulate CacheBlk's status

Encapsulate this variable to facilitate polymorphism.

- The status enum was renamed to CoherenceBits, since it
  lists the coherence bits supported by the CacheBlk.
- status was made protected and renamed to coherence since
  it contains the coherence bits.
- Functions to set, clear and get the coherence bits were
  created.
- To set a status bit, the block must be validated first.
  This guarantees a constant flow and helps catching bugs.

As a side effect, some of the modified files contained long
lines, which had to be split.

Change-Id: I558cc51ac685d30b6bf298c78f86a6e24ff06973
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34960
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Isolate compression bit

The compression bit does not belong with the coherence bits.

Change-Id: I6e9f201a9961b8c6051ba599f051a444d585f0e4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35700
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Isolate prefetching bit

Previously the prefetching bit was among the status bits;
yet, it has no correlation with the other bits. It has
been isolated as a single boolean, with a respective getter
and setter.

Change-Id: Ibe76e1196ca17a7c9ab9bda2216186707427cb64
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35699
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Create a tagged entry class

The TaggedEntry class inherits from the ReplaceableEntry
class. Its purpose is to define a replaceable entry with
tagging attributes.

It has been created as a separate class because both the
replacement policies and the AbstractCacheEntry use
ReplaceableEntry, and do not need the tagging information
to perform their operations.

Change-Id: I24e87c865fc21c79dea7e488507a8cafc5223b39
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35698
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Debug with blk's information instead of its state.

The print() function has been defined to facilitate debugging
regarding a block's metadata. Use it instead of accessing the
coherence bits directly.

Change-Id: Iba41f4ac067561970621a4bba809e1b315b0210d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35697
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add missing StridePrefetcher invalidation

A call to the entry's parent's invalidate function was missing.
Since an entry was only invalidated right before being used,
previous behavior was not breaking anything.

Change-Id: Ibbf31a0099600a8f6be70b3426bac9fcd1e5c749
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35696
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

stats: Make Stats::Group::mergeStatGroup public

The stat system currently assumes that the decision to merge groups is
done at construction time. This makes it hard to implement global
statistics that live in a single global group.

This change adds some error checking to mergeStatGroup and marks it as
a public method.

Change-Id: I6a42f48545c5ccfcd0672bae66a5bc86bb042f13
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35615
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Default ArmSystem to AArch64

Change-Id: I4dad29086c0b3e50bd2011363cb23625811b4b27
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35775
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Simplify the IntOp format slightly.

Change-Id: I693e56a04827287712e001cf99620085ab09b8ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35236
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Clean up some code in base.isa.

This includes the filterDoubles function which adds code to combine 32
bit values into doubles or 64 bit values for floating point, and the
splitOutImm function which detects if the code that implements an
instruction has a register and immediate variant, and generates code for
each.

Change-Id: I5524b9acd6e610b51fd91fe70276c34c23be9f85
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35235
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add a mechanism for finding an compatible SE workload.

This makes it possible to pick an SEWorkload generically at the config
level and not in C++ after the structure of the simulation has already
been set.

Change-Id: I7e52beb5a4d45aa43192e1ba4de6c5aab8b43d84
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33900
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Add IrisMMU model

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: Ida4ec76df5f6192e34a5b3fc6d002c473d48b387
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35415
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Add generic BaseMMU

This is an abstract class encapsulating the ITB and DTB
(Instruction and Data TLBs)

JIRA: https://gem5.atlassian.net/browse/GEM5-790

Change-Id: I7c8fa2ada319e631564182075da1aaff517ec212
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34975
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Replace call to `tmpnam()` by a deterministic one

According to the documentation, the use of tmpnam() should be
avoided.

This commit generates a temporary filename by concat-ing the
object name with an index that is internally tracked, the index
is increased until a filename that is not being used is found.

JIRA: https://gem5.atlassian.net/browse/GEM5-206

Change-Id: Ibfe604d741b6b7d7b02fc051add217f95f81d05e
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35195
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Add recursion for DTB entry generation inside BaseCPU

Change-Id: Ice93b67ee44a1228120f8a63ad5b9d952f813c70
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35556
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Add recursion for DTB entry generation inside ArmISA

In order to generate the ArmPMU's DTB entry, we have to enable recursion
from the ArmISA.

This commit follows this mailing list entry:
https://www.mail-archive.com/gem5-users@gem5.org/msg18401.html

Change-Id: I73012755f0f8c8d4d17278793cf16cb1e8b011df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35555
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Encapsulate CacheBlk's srcRequestorId

Encapsulate this variable to facilitate polymorphism.

- requestorId was renamed to _requestorId and was privatized.
- The requestor ID should only be modified on insertion and
  invalidation; thus, its setter is not public.

Change-Id: I5bab21a6c21e9d912fb5194bb44ff785d44999f4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34959
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Encapsulate CacheBlk's tickInserted

Encapsulate this variable to facilitate polymorphism.

- tickInserted was renamed to _tickInserted and was privatized.
- The insertion tick should always be set to the current tick,
  and only on insertion; thus, its setter is not public and
  does not take arguments.
- An additional function was created to get the age since of
  the block relative to its insertion tick.
- There is no current need for a getter.

Change-Id: I81d4009abec5e9633e10f1e851e3a524553c98a4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34958
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>