git.libre-soc.org Git

aarch64: Use RTL builtins for [su]mull_n intrinsics

Rewrite [su]mull_n Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-01-19 Jonathan Wright <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add [su]mull_n
builtin generator macros.
* config/aarch64/aarch64-simd.md (aarch64_<su>mull_n<mode>):
Define.
* config/aarch64/arm_neon.h (vmull_n_s16): Use RTL builtin
instead of inline asm.
(vmull_n_s32): Likewise.
(vmull_n_u16): Likewise.
(vmull_n_u32): Likewise.

aarch64: Reimplement vabdl_high* intrinsics using builtins

This patch reimplements the vabdl_high intrinsics using builtins.
It slightly cleans up the RTL pattern (the mode iterators) but nothing
interesting apart from that.

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (sabdl2, uabdl2):
Define builtins.
* config/aarch64/aarch64-simd.md (aarch64_<sur>abdl2<mode>_3):
Rename to...
(aarch64_<sur>abdl2<mode>): ... This.
(<sur>sadv16qi): Adjust use of above.
* config/aarch64/arm_neon.h (vabdl_high_s8): Reimplement using
builtin.
(vabdl_high_s16): Likewise.
(vabdl_high_s32): Likewise.
(vabdl_high_u8): Likewise.
(vabdl_high_u16): Likewise.
(vabdl_high_u32): Likewise.

aarch64: Re-implement vabal_high* intrinsics using builtins

This patch reimplements the vabal_high* intrinsics using RTL builtins.
It's straightforward, defining new unspecs and a new pattern.

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (sabal2): Define
builtin.
(uabal2): Likewise.
* config/aarch64/aarch64-simd.md (aarch64_<sur>abal2<mode>): New
pattern.
* config/aarch64/aarch64.md (unspec): Add UNSPEC_SABAL2 and
UNSPEC_UABAL2.
* config/aarch64/arm_neon.h (vabal_high_s8): Reimplement using
builtin.
(vabal_high_s16): Likewise.
(vabal_high_s32): Likewise.
(vabal_high_u8): Likewise.
(vabal_high_u16): Likewise.
(vabal_high_u32): Likewise.
* config/aarch64/iterators.md (ABAL2): New mode iterator.
(sur): Handle UNSPEC_SABAL2, UNSPEC_UABAL2.

aarch64: Reimplement vabal* intrinsics using builtins

This patch reimplements the vabal intrinsics with builtins.
The RTL pattern is cleaned up to emit the right .8b suffixes for the
inputs (though .16b is also accepted)
and iterate over the right modes. The pattern's only other use is
through the sadv16qi expander, which is adjusted.

I've verified that the codegen for sadv16qi is not worse off.

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (sabal): Define
builtin.
(uabal): Likewise.
* config/aarch64/aarch64-simd.md (aarch64_<sur>abal<mode>_4):
Rename to...
(aarch64_<sur>abal<mode>): ... This
(<sur>sadv16qi): Adust use of the above.
* config/aarch64/arm_neon.h (vabal_s8): Reimplement using
builtin.
(vabal_s16): Likewise.
(vabal_s32): Likewise.
(vabal_u8): Likewise.
(vabal_u16): Likewise.
(vabal_u32): Likewise.

aarch64: Reimplement vaddlv* intrinsics using builtins

This patch reimplements the vaddlv* intrinsics using builtins.
The vaddlv_s32 and vaddlv_u32 intrinsics actually perform a pairwise
SADDLP/UADDLP instead of a SADDLV/UADDLV but because they only use
two elements it has the same semantics.

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (saddlv, uaddlv):
Define builtins.
* config/aarch64/aarch64-simd.md (aarch64_<su>addlv<mode>):
Define.
* config/aarch64/arm_neon.h (vaddlv_s8): Reimplement using
builtin.
(vaddlv_s16): Likewise.
(vaddlv_u8): Likewise.
(vaddlv_u16): Likewise.
(vaddlvq_s8): Likewise.
(vaddlvq_s16): Likewise.
(vaddlvq_s32): Likewise.
(vaddlvq_u8): Likewise.
(vaddlvq_u16): Likewise.
(vaddlvq_u32): Likewise.
(vaddlv_s32): Likewise.
(vaddlv_u32): Likewise.
* config/aarch64/iterators.md (VDQV_L): New mode iterator.
(unspec): Add UNSPEC_SADDLV, UNSPEC_UADDLV.
(Vwstype): New mode attribute.
(Vwsuf): Likewise.
(VWIDE_S): Likewise.
(USADDLV): New int iterator.
(su): Handle UNSPEC_SADDLV, UNSPEC_UADDLV.

gcc/testsuite/ChangeLog:

* gcc.target/aarch64/simd/vaddlv_1.c: New test.

aarch64: Use RTL builtins for [su]mlsl_lane[q] intrinsics

Rewrite [su]mlsl_lane[q] Neon intrinsics to use RTL builtins rather
than inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-01-28 Jonathan Wright <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add [su]mlsl_lane[q]
builtin generator macros.
* config/aarch64/aarch64-simd.md (aarch64_vec_<su>mlsl_lane<Qlane>):
Define.
* config/aarch64/arm_neon.h (vmlsl_lane_s16): Use RTL builtin
instead of inline asm.
(vmlsl_lane_s32): Likewise.
(vmlsl_lane_u16): Likewise.
(vmlsl_lane_u32): Likewise.
(vmlsl_laneq_s16): Likewise.
(vmlsl_laneq_s32): Likewise.
(vmlsl_laneq_u16): Likewise.
(vmlsl_laneq_u32): Likewise.

change unit of --param max-gcse-memory to kB

This changes it from bytes to kB since its value is limited to
2147483648.

2021-01-29 Richard Biener <rguenther@suse.de>

* doc/invoke.texi (--param max-gcse-memory): Document unit
of size.
* gcse.c (gcse_or_cprop_is_too_expensive): Adjust.
* params.opt (--param max-gcse-memory): Adjust default and
document unit of size.

rtl-optimization/98863 - fix PRE/CPROP memory usage check

This fixes overflow of the memory usage estimate in turn failing
to disable itself on WRF with LTO, causing a few GBs worth of
memory peak.

2021-01-29 Richard Biener <rguenther@suse.de>

PR rtl-optimization/98863
* gcse.c (gcse_or_cprop_is_too_expensive): Use unsigned
HOST_WIDE_INT for the memory estimate.

tree-optimization/97627 - Avoid computing niters for fake edges

This avoids computing niters information for fake edges.

2021-01-29 Bin Cheng <bin.cheng@linux.alibaba.com>
Richard Biener <rguenther@suse.de>

PR tree-optimization/97627
* tree-ssa-loop-niter.c (number_of_iterations_exit_assumptions):
Do not analyze fake edges.

* g++.dg/pr97627.C: New testcase.

rtl-optimization/98144 - tame REE memory usage

This changes the REE dataflow to change the explicit all-ones
starting solution to be implicit via a visited flag, removing
the need to initially start with fully populated bitmaps for
all basic-blocks. That reduces peak memory use when compiling
the RTL checking enabled insn-extract.c testcase from PR98144
from 6GB to less than 2GB.

2021-01-29 Richard Biener <rguenther@suse.de>

PR rtl-optimization/98144
* df.h (df_mir_bb_info): Add con_visited member.
* df-problems.c (df_mir_alloc): Initialize con_visited,
do not fully populate IN and OUT.
(df_mir_reset): Likewise.
(df_mir_confluence_0): Set con_visited.
(df_mir_confluence_n): Properly handle implicitely
fully populated IN and OUT as designated by con_visited
and update con_visited accordingly.

arm: Fix up -mcpu=iwmmxt ICEs [PR98849]

The
https://gcc.gnu.org/r11-6707-g7432f255b70811dafaf325d94036ac580891de69
https://gcc.gnu.org/r11-6708-gbfab355012ca0f5219da8beb04f2fdaf757d34b7
changes moved the vashl/vashr/vlshr expanders from neon.md to vec-common.md
and changed their condition from TARGET_NEON to ARM_HAVE_<MODE>_ARITH,
so that they apply also for TARGET_HAVE_MVE.  But, the ARM_HAVE_<MODE>_ARITH
macros are sometimes true also for TARGET_REALLY_IWMMXT, which at least
from quick skimming of former iwmmxt*.md doesn't have such instructions,
so it seems incorrect to enable them for iwmmxt.  Furthermore, even if it
had them, iwmmxt doesn't support any way to broadcast values in those
modes (vec_duplicate and vec_init optabs) and the middle end relies on
if the vector x vector shift/rotate patterns are supported it can emit
vector x scalar shift/rotate by broadcasting the shift amount to a vector.

As the TARGET_NEON vs. TARGET_REALLY_IWMMXT vs. TARGET_HAVE_MVE never seem
to be enabled together, I think we can just write it the following way.

Note, seems iwmmxt actually does support vector x scalar shifts, but doesn't
really enable the optabs that would tell the middle-end code that it does
(and neon and mve don't seem to support those).  I'll defer that to anybody
that cares about iwmmxt (if any).

2021-01-29  Jakub Jelinek  <jakub@redhat.com>

PR target/98849
* config/arm/vec-common.md (mve_vshlq_<supf><mode>,
vashl<mode>3, vashr<mode>3, vlshr<mode>3): Add
&& !TARGET_REALLY_IWMMXT to conditions.

* gcc.c-torture/compile/pr98849.c: New test.

expand: Fix up find_bb_boundaries [PR98331]

When expansion emits some control flow insns etc. inside of a former GIMPLE
basic block, find_bb_boundaries needs to split it into multiple basic
blocks.
The code needs to ignore debug insns in decisions how many splits to do or
where in between some non-debug insns the split should be done, but it can
decide where to put debug insns if they can be kept and otherwise throws
them away (they can't stay outside of basic blocks).
On the following testcase, we end up in the bb from expander with
control flow insn
debug insns
barrier
some other insn
(the some other insn is effectively dead after __builtin_unreachable and
we'll optimize that out later).
Without debug insns, we'd do the split when encountering some other insn
and split after PREV_INSN (some other insn), i.e. after barrier (and the
splitting code then moves the barrier in between basic blocks).
But if there are debug insns, we actually split before the first debug insn
that appeared after the control flow insn, so after control flow insn,
and get a basic block that starts with debug insns and then has a barrier
in the middle that nothing moves it out of the bb. This leads to ICEs and
even if it wouldn't, different behavior from -g0.
The reason for treating debug insns that way is a different case, e.g.
control flow insn
debug insns
some other insn
or even
control flow insn
barrier
debug insns
some other insn
where splitting before the first such debug insn allows us to keep them
while otherwise we would have to drop them on the floor, and in those
situations we behave the same with -g0 and -g.

So, the following patch fixes it by resetting debug_insn not just when
splitting the blocks (it is set only after seeing a control flow insn and
before splitting for it if needed), but also when seeing a barrier,
which effectively means we always throw away debug insns after a control
flow insn and before following barrier if any, but there is no way around
that, control flow insn must be the last in the bb (BB_END) and BARRIER
after it, debug insns aren't allowed outside of bb.
We still handle the other cases fine (when there is no barrier or when
debug insns appear only after the barrier).

2021-01-29 Jakub Jelinek <jakub@redhat.com>

PR debug/98331
* cfgbuild.c (find_bb_boundaries): Reset debug_insn when seeing
a BARRIER.

* gcc.dg/pr98331.c: New test.

testsuite: Run vec_insert case on P8 and P9 with option specified

Move run_test and TEST_VEC_INSERT_ALL to header file for share usage.

gcc/testsuite/ChangeLog:

2021-01-29 Xionghu Luo <luoxhu@linux.ibm.com>

* gcc.target/powerpc/pr79251.p8.c: Move TEST_VEC_INSERT_ALL
to ...
* gcc.target/powerpc/pr79251.h: ...this.
* gcc.target/powerpc/pr79251.p9.c: Likewise.
* gcc.target/powerpc/pr79251-run.c: Move run_test to pr79251.h.
Rename to...
* gcc.target/powerpc/pr79251-run.p8.c: ...this.
* gcc.target/powerpc/pr79251-run.p9.c: New test.

c++: Fix infinite looping with invalid operator [PR96137]

My r11-86 adjusted cp_parser_class_name to do

-  scope = parser->scope;
+  scope = parser->scope ? parser->scope : parser->context->object_type;
   if (scope == error_mark_node)
     return error_mark_node;

but that caused endless looping in cp_parser_type_specifier_seq (the
while (true) loop) in this invalid test, because we never set a parser
error, therefore cp_parser_type_specifier returned error_mark_node
instead of NULL_TREE, and we never issued the "expected type-specifier"
error.

At first I thought I'd just add cp_parser_simulate_error right before
the return, but that regresses crash81.C -- we'd emit multiple errors
for "T::X".  So the next best thing seemed to revert to pre-r11-86
behavior: return early when parser->scope is bad, otherwise proceed to
get the parser error.

gcc/cp/ChangeLog:

PR c++/96137
* parser.c (cp_parser_class_name): If parser->scope is
error_mark_node, return it, otherwise continue.

gcc/testsuite/ChangeLog:

PR c++/96137
* g++.dg/parse/error63.C: New test.

Daily bump.

gccgo driver: always act as though -g is passed

The go1 compiler always turns on debugging, to support Go stack traces
and functions like runtime.Callers.  With the recent switch to turn on
DWARF 5 by default, this caused failures with some versions of gas,
such as 2.35.1, because the assembly code would assume DWARF 5 but the
driver would not pass --gdwarf-5 to gas.  gas would then give an
error: "file number less than one".

This change avoids that problem by having the gccgo driver spec add a
-g option to the command line if no other -g option is present.  The
newly added -g option is passed to the assembler as --gdwarf-5.

* gospec.c (lang_specific_driver): Add -g if no debugging options
were passed.

c++: Fix -Weffc++ in templates [PR98841]

We emit a bogus warning on the following testcase, suggesting that the
operator should return *this even when it does that already.
The problem is that normally cp_build_indirect_ref_1 ensures that *this
is folded as current_class_ref, but in templates (if return type is
non-dependent, otherwise check_return_expr doesn't check it) it didn't
go through cp_build_indirect_ref_1, but just built another INDIRECT_REF.
Which means it then doesn't compare pointer-equal to current_class_ref.

The following patch fixes it by doing in build_x_indirect_ref for
*this what cp_build_indirect_ref_1 would do.

2021-01-28 Jakub Jelinek <jakub@redhat.com>

PR c++/98841
* typeck.c (build_x_indirect_ref): For *this, return current_class_ref.

* g++.dg/warn/effc5.C: New test.

tree: Don't reuse types if TYPE_USER_ALIGN differ [PR94775]

A year ago I submitted this patch:

~~
Here we trip on the TYPE_USER_ALIGN (t) assert in strip_typedefs: it
gets "const d[0]" with TYPE_USER_ALIGN=0 but the result built by
build_cplus_array_type is "const char[0]" with TYPE_USER_ALIGN=1.

When we strip_typedefs the element of the array "const d", we see it's
a typedef_variant_p, so we look at its DECL_ORIGINAL_TYPE, which is
char, but we need to add the const qualifier, so we call
cp_build_qualified_type -> build_qualified_type
where get_qualified_type checks to see if we already have such a type
by walking the variants list, which in this case is:

  char -> c -> const char -> const char -> d -> const d

Because check_base_type only checks TYPE_ALIGN and not TYPE_USER_ALIGN,
we choose the first const char, which has TYPE_USER_ALIGN set.  If the
element type of an array has TYPE_USER_ALIGN, the array type gets it too.

So we can make check_base_type stricter.  I was afraid that it might make
us reuse types less often, but measuring showed that we build the same
amount of types with and without the patch, while bootstrapping.
~~

However, the patch broke a few tests on STRICT_ALIGNMENT platforms and
had to be reverted.  This is another try.  The original patch is kept
unchanged, but I added the finalize_type_size hunk that ought to fix the
STRICT_ALIGNMENT issues.

The problem is that finalize_type_size can clear TYPE_USER_ALIGN on the
main variant of a type, but doesn't clear it on any of the variants.
Then we end up with types which share the same TYPE_MAIN_VARIANT, but
their TYPE_CANONICAL differs and then the usual "canonical types differ
for identical types" follows.

I've created alignas19.C to exercise this scenario.  What happens is:
- when parsing the class S we create a type S in xref_tag,
- we see alignas(8) so common_handle_aligned_attribute sets T_U_A in S,
- we parse the member function fn and build_memfn_type creates a copy
  of S to add const; this variant has T_U_A set,
- we finish_struct S which calls layout_class_type -> finish_record_type
  -> finalize_size_type where we reset T_U_A in S (but const S keeps it),
- finish_non_static_data_member for arr calls maybe_dummy_object with
  type = S,
- maybe_dummy_object calls same_type_ignoring_top_level_qualifiers_p
  to check if S and TREE_TYPE (current_class_ref), which is const S,
  are the same,
- same_type_ignoring_top_level_qualifiers_p creates cv-unqualified
  versions of the passed types.  Previously we'd use our main variant
  S when stripping "const S" of const, but since the T_U_A flags don't
  match (check_base_type), we create a new variant S'.  Then we crash in
  comptypes because S and S' have the same TYPE_MAIN_VARIANT but
  different TYPE_CANONICALs.

With my patch we'll clear T_U_A for S's variants too, and then instead
of S' we'll just use S.

gcc/ChangeLog:

PR c++/94775
* stor-layout.c (finalize_type_size): If we reset TYPE_USER_ALIGN in
the main variant, maybe reset it in its variants too.
* tree.c (check_base_type): Return true only if TYPE_USER_ALIGN match.
(check_aligned_type): Check if TYPE_USER_ALIGN match.

gcc/testsuite/ChangeLog:

PR c++/94775
* g++.dg/cpp0x/alignas19.C: New test.
* g++.dg/warn/Warray-bounds15.C: New test.

libstdc++: Fix copyright dates for simd headers and tests

libstdc++-v3/ChangeLog:

* include/experimental/bits/numeric_traits.h: Update copyright
dates.
* include/experimental/bits/simd.h: Likewise.
* include/experimental/bits/simd_builtin.h: Likewise.
* include/experimental/bits/simd_converter.h: Likewise.
* include/experimental/bits/simd_detail.h: Likewise.
* include/experimental/bits/simd_fixed_size.h: Likewise.
* include/experimental/bits/simd_math.h: Likewise.
* include/experimental/bits/simd_neon.h: Likewise.
* include/experimental/bits/simd_ppc.h: Likewise.
* include/experimental/bits/simd_scalar.h: Likewise.
* include/experimental/bits/simd_x86.h: Likewise.
* include/experimental/bits/simd_x86_conversions.h: Likewise.
* include/experimental/simd: Likewise.
* testsuite/experimental/simd/*: Likewise.

arm: Adjust cost of vector of constant zero

Neon vector comparisons have a dedicated version when comparing with
constant zero: it means its cost is free.

Adjust the cost in arm_rtx_costs_internal accordingly, for Neon only,
since MVE does not support this.

2021-01-28 Christophe Lyon <christophe.lyon@linaro.org>

gcc/
PR target/98730
* config/arm/arm.c (arm_rtx_costs_internal): Adjust cost of vector
of constant zero for comparisons.

gcc/testsuite/
PR target/98730
* gcc.target/arm/simd/vceqzq_p64.c: Update expected result.

testsuite: Fix up a testcase to find the right ISO_Fortran_binding.h.

gcc/testsuite/ChangeLog:

* gfortran.dg/ISO_Fortran_binding_18.c: Include
../../../libgfortran/ISO_Fortran_binding.h rather than
ISO_Fortran_binding.h.

Map long double built-ins correctly with IEEE 128-bit long double.

The PowerPC has two different 128-bit long double types, one that uses a pair
of doubles to get more mantissa range, and the other using the IEEE 128-bit
754R binary floating point format.  The pair of doubles has been used as the
traditional format, and we are in the process of moving to allow an
implementation to switch to using IEEE 128-bit floating point.  The GLIBC and
LIBSTDC++ libraries have been modified to have functions using the two
different formats in their libraries with different names.

This patch goes through all of the built-in functions that either take long
double arguments or return long double, and changes the name from the
traditional name to the IEEE 128-bit name.  The minimum GLIBC version to
support IEEE 128-bit floating point is 2.32.

The names changed are:

    * <name>l is usually mapped to __<name>ieee128;
    * <extra>printf is mapped to __<extra>printfieee128; (and)
    * <extra>scanf is mapped to __isoc99_<extra>scanfieee128.

A few functions have different mappings:

    * dreml => __remainderieee128;
    * gammal => __lgammaieee128;
    * gammal_r => __lgammaieee128_r;
    * lgammal_r => __lgammaieee128_r;
    * nexttoward => __nexttoward_to_ieee128;
    * nexttowardf => __nexttowardf_to_ieee128;
    * nexttowardl => __nexttowardl_to_ieee128;
    * pow10l => __exp10ieee128;
    * scalbl => __scalbieee128;
    * significandl => __significandieee128; (and)
    * sincosl => __sincosieee128.

gcc/
2021-01-28  Michael Meissner  <meissner@linux.ibm.com>

* config/rs6000/rs6000.c (rs6000_mangle_decl_assembler_name): Add
support for mapping built-in function names for long double
built-in functions if long double is IEEE 128-bit.

gcc/testsuite/
2021-01-28  Michael Meissner  <meissner@linux.ibm.com>

* gcc.target/powerpc/float128-longdouble-math.c: New test.
* gcc.target/powerpc/float128-longdouble-stdio.c: New test.
* gcc.target/powerpc/float128-math.c: Adjust test for new name
being generated.  Add support for running test on power10.  Add
support for running if long double defaults to 64-bits.

c++: Fix up handling of register ... asm ("...") vars in templates [PR33661, PR98847]

As the testcase shows, for vars appearing in templates, we don't attach
the asm spec string to the pattern decls, nor pass it back to cp_finish_decl
during instantiation.

The following patch does that.

2021-01-28 Jakub Jelinek <jakub@redhat.com>

PR c++/33661
PR c++/98847
* decl.c (cp_finish_decl): For register vars with asmspec in templates
call set_user_assembler_name and set DECL_HARD_REGISTER.
* pt.c (tsubst_expr): When instantiating DECL_HARD_REGISTER vars,
pass asmspec_tree to cp_finish_decl.

* g++.target/i386/pr98847.C: New test.

aarch64: Use RTL builtins for [su]mlsl_n intrinsics

Rewrite [su]mlsl_n Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-01-27 Jonathan Wright <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add [su]mlsl_n
builtin generator macros.
* config/aarch64/aarch64-simd.md (aarch64_<su>mlsl_n<mode>):
Define.
* config/aarch64/arm_neon.h (vmlsl_n_s16): Use RTL builtin
instead of inline asm.
(vmlsl_n_s32): Likewise.
(vmlsl_n_u16): Likewise.
(vmlsl_n_u32): Likewise.

aarch64: Fix gcc.target/aarch64/narrow_high-intrinsics.c testism

Pushing to fix recently-updated assembly generation

gcc/testsuite/

* gcc.target/aarch64/narrow_high-intrinsics.c: Fix shrn2 scan.

aarch64: Use RTL builtins for [su]mlal_n intrinsics

Rewrite [su]mlal_n Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-01-26 Jonathan Wright <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add [su]mlal_n
builtin generator macros.
* config/aarch64/aarch64-simd.md (aarch64_<su>mlal_n<mode>):
Define.
* config/aarch64/arm_neon.h (vmlal_n_s16): Use RTL builtin
instead of inline asm.
(vmlal_n_s32): Likewise.
(vmlal_n_u16): Likewise.
(vmlal_n_u32): Likewise.

c++: header unit template alias merging [PR 98770]

Typedefs are streamed by streaming the underlying type, and then
recreating the typedef.  But this breaks checking a duplicate is the
same as the original when it is a template alias -- we end up checking
a template alias (eg __void_t) against the underlying type (void).
And those are not the same template alias.  This stops pretendig that
the underlying type is the typedef for that checking and tells
is_matching_decl 'you have a typedef', so it knows what to do.  (We do
not want to recreate the typedef of the duplicate, because that whole
set of nodes is going to go away.)

PR c++/98770
gcc/cp/
* module.cc (trees_out::decl_value): Swap is_typedef & TYPE_NAME
check order.
(trees_in::decl_value): Do typedef frobbing only when installing
a new typedef, adjust is_matching_decl call.  Swap is_typedef
& TYPE_NAME check.
(trees_in::is_matching_decl): Add is_typedef parm. Adjust variable
names and deal with typedef checking.
gcc/testsuite/
* g++.dg/modules/pr98770_a.C: New.
* g++.dg/modules/pr98770_b.C: New.

aarch64: Reimplement vshrn_high_n* intrinsics using builtins

This patch reimplements the vshrn_high_n* intrinsics that generate the
SHRN2 instruction.
It is a vec_concat of the narrowing shift with the bottom part of the
destination register, so we need a little-endian and a big-endian version and an expander to
pick between them.

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (shrn2): Define
builtin.
* config/aarch64/aarch64-simd.md (aarch64_shrn2<mode>_insn_le):
Define.
(aarch64_shrn2<mode>_insn_be): Likewise.
(aarch64_shrn2<mode>): Likewise.
* config/aarch64/arm_neon.h (vshrn_high_n_s16): Reimlplement
using builtins.
(vshrn_high_n_s32): Likewise.
(vshrn_high_n_s64): Likewise.
(vshrn_high_n_u16): Likewise.
(vshrn_high_n_u32): Likewise.
(vshrn_high_n_u64): Likewise.

aarch64: Reimplement vshrn_n* intrinsics using builtins

This patch reimplements the vshrn_n* intrinsics to use RTL builtins.
These perform a narrowing right shift.

Although the intrinsic generates the half-width mode (e.g. V8HI ->
V8QI), the new pattern generates a full 128-bit mode (V8HI -> V16QI) by representing the
fill-with-zeroes semantics of the SHRN instruction. The narrower (V8QI) result is extracted with a
lowpart subreg.
I found this allows the RTL optimisers to do a better job at optimising
redundant moves away in frequently-occurring SHRN+SRHN2 pairs, like in:
uint8x16_t
foo (uint16x8_t in1, uint16x8_t in2)
{
  uint8x8_t tmp = vshrn_n_u16 (in2, 7);
  uint8x16_t tmp2 = vshrn_high_n_u16 (tmp, in1, 4);
  return tmp2;
}

gcc/ChangeLog:

* config/aarch64/aarch64-simd-builtins.def (shrn): Define
builtin.
* config/aarch64/aarch64-simd.md (aarch64_shrn<mode>_insn_le):
Define.
(aarch64_shrn<mode>_insn_be): Likewise.
(aarch64_shrn<mode>): Likewise.
* config/aarch64/arm_neon.h (vshrn_n_s16): Reimplement using
builtins.
(vshrn_n_s32): Likewise.
(vshrn_n_s64): Likewise.
(vshrn_n_u16): Likewise.
(vshrn_n_u32): Likewise.
(vshrn_n_u64): Likewise.
* config/aarch64/iterators.md (vn_mode): New mode attribute.

Fix LTO bootstrap on Windows

The latest fix introduced a comparison of executables and this cannot
directly work on Windows because they are timestamped. Moreover nobody
sets $(exeext) at top level, at least on MinGW, so you get weird behavior
because some tools add the implicit .exe suffix and others do not.

contrib/
PR lto/85574
* compare-lto: Deal with PE-COFF executables specifically.

PR fortran/86470 - ICE with OpenMP, class(*) allocatable

gfc_call_malloc should malloc an area of size 1 if no size given.

gcc/fortran/ChangeLog:

PR fortran/86470
* trans.c (gfc_call_malloc): Allocate area of size 1 if passed
size is NULL (as documented).

gcc/testsuite/ChangeLog:

PR fortran/86470
* gfortran.dg/gomp/pr86470.f90: New test.

c++: Some C++20 and C++23 option help fixes

I've noticed we still refer to C++20 as draft standard, and there is a pasto
in C++23 description.

2021-01-28 Jakub Jelinek <jakub@redhat.com>

* c.opt (-std=c++2a, -std=c++20, -std=gnu++2a, -std=gnu++20): Remove
draft from description.
(-std=c++2b): Fix a pasto, 2020 -> 2023.

rtl-optimization/80960 - avoid creating garbage RTL in DSE

The following avoids repeatedly turning VALUE RTXen into
sth useful and re-applying a constant offset through get_addr
via DSE check_mem_read_rtx.  Instead perform this once for
all stores to be visited in check_mem_read_rtx.  This avoids
allocating 1.6GB of garbage PLUS RTXen on the PR80960
testcase, fixing the memory usage regression from old GCC.

2021-01-27  Richard Biener  <rguenther@suse.de>

PR rtl-optimization/80960
* dse.c (check_mem_read_rtx): Call get_addr on the
offsetted address.

rs6000: Fix vec insert ilp32 ICE and test failures [PR98799]

UNSPEC_SI_FROM_SF is not supported when TARGET_DIRECT_MOVE_64BIT
is false for -m32, don't generate VIEW_CONVERT_EXPR(ARRAY_REF) for
variable vector insert.  Remove rs6000_expand_vector_set_var helper
function, adjust the p8 and p9 definitions position and make them
static.

The previous commit r11-6858 missed check m32, This patch is tested pass
on P7BE{m32,m64}/P8BE{m32,m64}/P8LE/P9LE with
RUNTESTFLAGS="--target_board =unix'{-m32,-m64}'" for BE targets.

gcc/ChangeLog:

2021-01-27  Xionghu Luo  <luoxhu@linux.ibm.com>
    David Edelsohn  <dje.gcc@gmail.com>

PR target/98799
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
Don't generate VIEW_CONVERT_EXPR for fcode ALTIVEC_BUILTIN_VEC_INSERT
when -m32.
* config/rs6000/rs6000-protos.h (rs6000_expand_vector_set_var):
Delete.
* config/rs6000/rs6000.c (rs6000_expand_vector_set): Remove the
wrapper call rs6000_expand_vector_set_var for cleanup.  Call
rs6000_expand_vector_set_var_p9 and rs6000_expand_vector_set_var_p8
directly.
(rs6000_expand_vector_set_var): Delete.
(rs6000_expand_vector_set_var_p9): Make static.
(rs6000_expand_vector_set_var_p8): Make static.

gcc/testsuite/ChangeLog:

2021-01-27  Xionghu Luo  <luoxhu@linux.ibm.com>

PR target/98827
* gcc.target/powerpc/fold-vec-insert-char-p8.c: Adjust ilp32.
* gcc.target/powerpc/fold-vec-insert-char-p9.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-double.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-float-p8.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-float-p9.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-int-p8.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-int-p9.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-longlong.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-short-p8.c: Likewise.
* gcc.target/powerpc/fold-vec-insert-short-p9.c: Likewise.
* gcc.target/powerpc/pr79251.p8.c: Likewise.
* gcc.target/powerpc/pr79251.p9.c: Likewise.
* gcc.target/powerpc/vsx-builtin-7.c: Likewise.
* gcc.target/powerpc/pr79251-run.c: Build and run with vsx
option.

RISC-V: Fix -march option parsing when extension exists.

This patch fixes -march option parsing when `p` extension exists,
e.g., -march=rv64imafdcp should produce

.attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c2p0_p"

rather than

.attribute arch, "rv64i2p0_m2p0_a2p0_f2p0_d2p0_c_p"

gcc/ChangeLog:

* common/config/riscv/riscv-common.c
(riscv_subset_list::parsing_subset_version): Fix -march option parsing
when `p` extension exists.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/attribute-18.c: New test.

Daily bump.

Fix strides for C descriptors with stride > 2.

libgfortran/ChangeLog:

* runtime/ISO_Fortran_binding.c (CFI_establish): fixed
strides for rank >2 arrays.

gcc/testsuite/ChangeLog:

* gfortran.dg/ISO_Fortran_binding_18.c: New test.
* gfortran.dg/ISO_Fortran_binding_18.f90: New test.

[PR97684] IRA: Recalculate pseudo classes if we added new pseduos since last calculation before updating equiv regs

update_equiv_regs can use reg classes of pseudos and they are set up in
register pressure sensitive scheduling and loop invariant motion and in
live range shrinking. This info can become obsolete if we add new pseudos
since the last set up. Recalculate it again if the new pseudos were
added.

gcc/ChangeLog:

PR rtl-optimization/97684
* ira.c (ira): Call ira_set_pseudo_classes before
update_equiv_regs when it is necessary.

gcc/testsuite/ChangeLog:

PR rtl-optimization/97684
* gcc.target/i386/pr97684.c: New.

c++: Dependent using enum [PR97874]

The handling of dependent scopes and unsuitable scopes in lookup_using_decl
was a bit convoluted; I tweaked it for a while and then eventually
reorganized much of the function to hopefully be clearer. Along the way I
noticed a couple of ways we were mishandling inherited constructors.

The local binding for a dependent using is the USING_DECL.

Implement instantiation of a dependent USING_DECL at function scope.

gcc/cp/ChangeLog:

PR c++/97874
* name-lookup.c (lookup_using_decl): Clean up handling
of dependency and inherited constructors.
(finish_nonmember_using_decl): Handle DECL_DEPENDENT_P.
* pt.c (tsubst_expr): Handle DECL_DEPENDENT_P.

gcc/testsuite/ChangeLog:

PR c++/97874
* g++.dg/lookup/using4.C: No error in C++20.
* g++.dg/cpp0x/decltype37.C: Adjust message.
* g++.dg/template/crash75.C: Adjust message.
* g++.dg/template/crash76.C: Adjust message.
* g++.dg/cpp0x/inh-ctor36.C: New test.
* g++.dg/cpp1z/inh-ctor39.C: New test.
* g++.dg/cpp2a/using-enum-7.C: New test.

aarch64: Fix up *aarch64_bfxilsi_uxtw [PR98853]

The https://gcc.gnu.org/legacy-ml/gcc-patches/2018-07/msg01895.html
patch that introduced this pattern claimed:
Would generate:

combine_balanced_int:
        bfxil   w0, w1, 0, 16
        uxtw    x0, w0
        ret

But with this patch generates:

combine_balanced_int:
        bfxil   w0, w1, 0, 16
        ret
and it is indeed what it should generate, but it doesn't do that,
it emits bfxil  x0, x1, 0, 16
instead which doesn't zero extend from 32 to 64 bits, but preserves
the bits from the destination register.

2021-01-27  Jakub Jelinek  <jakub@redhat.com>

PR target/98853
* config/aarch64/aarch64.md (*aarch64_bfxilsi_uxtw): Use
%w0, %w1 and %2 instead of %0, %1 and %2.

* gcc.c-torture/execute/pr98853-1.c: New test.
* gcc.c-torture/execute/pr98853-2.c: New test.

Combine patterns for p10 load-cmpi fusion

This patch adds the first batch of patterns to support p10 fusion. These
will allow combine to create a single insn for a pair of instructions
that power10 can fuse and execute. These particular fusion pairs have the
requirement that only cr0 can be used when fusing a load with a compare
immediate of -1/0/1 (if signed) or 0/1 (if unsigned), so we want combine
to put that requirement in, and if it doesn't work out the splitter
can change it back into 2 insns so scheduling can move them apart.

The patterns are generated by a script genfusion.pl and live in new file
fusion.md. This script will be expanded to generate more patterns for
fusion.

This also adds option -mpower10-fusion which defaults on for power10 and
will gate all these fusion patterns. In addition I have added an
undocumented option -mpower10-fusion-ld-cmpi (which may be removed later)
that just controls the load+compare-immediate patterns. I have made
these default on for power10 but they are not disallowed for earlier
processors because it is still valid code. This allows us to test the
correctness of fusion code generation by turning it on explicitly.

gcc/ChangeLog:

* config/rs6000/genfusion.pl: New script to generate
define_insn_and_split patterns so combine can arrange fused
instructions next to each other.
* config/rs6000/fusion.md: New file, generated fused instruction
patterns for combine.
* config/rs6000/predicates.md (const_m1_to_1_operand): New predicate.
(non_update_memory_operand): New predicate.
* config/rs6000/rs6000-cpus.def: Add OPTION_MASK_P10_FUSION and
OPTION_MASK_P10_FUSION_LD_CMPI to ISA_3_1_MASKS_SERVER and
POWERPC_MASKS.
* config/rs6000/rs6000-protos.h (address_is_non_pfx_d_or_x): Add
prototype.
* config/rs6000/rs6000.c (rs6000_option_override_internal):
Automatically set OPTION_MASK_P10_FUSION and
OPTION_MASK_P10_FUSION_LD_CMPI if target is power10.
(rs600_opt_masks): Allow -mpower10-fusion
in function attributes.
(address_is_non_pfx_d_or_x): New function.
* config/rs6000/rs6000.h: Add MASK_P10_FUSION.
* config/rs6000/rs6000.md: Include fusion.md.
* config/rs6000/rs6000.opt: Add -mpower10-fusion
and -mpower10-fusion-ld-cmpi.
* config/rs6000/t-rs6000: Add dependencies involving fusion.md.

libstdc++: Regenerate libstdc++ HTML docs

libstdc++-v3/ChangeLog:

* doc/xml/manual/status_cxx2017.xml: Replace invalid entity.
* doc/html/*: Regenerate.

aarch64: Use RTL builtins for [su]mlal intrinsics

Rewrite [su]mlal Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-01-26 Jonathan Wright <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add [su]mlal
builtin generator macros.
* config/aarch64/aarch64-simd.md (*aarch64_<su>mlal<mode>):
Rename to...
(aarch64_<su>mlal<mode>): This.
* config/aarch64/arm_neon.h (vmlal_s8): Use RTL builtin
instead of inline asm.
(vmlal_s16): Likewise.
(vmlal_s32): Likewise.
(vmlal_u8): Likewise.
(vmlal_u16): Likewise.
(vmlal_u32): Likewise.

libstdc++: Use printf to print control characters

Bash and GNU echo do not interpret backslash escapes by default, so use
printf when printing \n or \t in strings.

libstdc++-v3/ChangeLog:

* testsuite/experimental/simd/generate_makefile.sh: Use printf
instead of echo when printing escape characters.

libstdc++: Add simd testsuite

Add a new check-simd target to the testsuite. The new target creates a
subdirectory, generates the necessary Makefiles, and spawns submakes to
build and run the tests. Running this testsuite with defaults on my
machine takes half of the time the dejagnu testsuite required to only
determine whether to run tests. Since the simd testsuite integrated in
dejagnu increased the time of the whole libstdc++ testsuite by ~100%
this approach is a compromise for speed while not sacrificing coverage
too much. Since the test driver is invoked individually per test
executable from a Makefile, make's jobserver (-j) trivially parallelizes
testing.

Testing different flags and with simulator (or remote execution) is
possible. E.g. `make check-simd DRIVEROPTS=-q
target_list="unix{-m64,-m32}{-march=sandybridge,-march=skylake-avx512}{,-
ffast-math}"`
runs the testsuite 8 times in different subdirectories, using 8
different combinations of compiler flags, only outputs failing tests
(-q), and prints all summaries at the end. It skips most ABI tags by
default unless --run-expensive is passed to DRIVEROPTS or
GCC_TEST_RUN_EXPENSIVE is not empty.

To use a simulator, the CHECK_SIMD_CONFIG variable needs to point to a
shell script which calls `define_target <name> <flags> <simulator>` and
set target_list as needed. E.g.:
case "$target_triplet" in
x86_64-*)
  target_list="unix{-march=sandybridge,-march=skylake-avx512}
  ;;
powerpc64le-*)
  define_target power8 "-static -mcpu=power8" "/usr/bin/qemu-ppc64le -cpu
power8"
  define_target power9 -mcpu=power9 "$HOME/bin/run_on_gcc135"
  target_list="power8 power9{,-ffast-math}"
  ;;
esac

libstdc++-v3/ChangeLog:

* scripts/check_simd: New file. This script is called from the
the check-simd target. It determines a set of compiler flags and
simulator setups for calling generate_makefile.sh and passes the
information back to the check-simd target, which recurses to the
generated Makefiles.
* scripts/create_testsuite_files: Remove files below simd/tests/
from testsuite_files and place them in testsuite_files_simd.
* testsuite/Makefile.am: Add testsuite_files_simd. Add
check-simd target.
* testsuite/Makefile.in: Regenerate.
* testsuite/experimental/simd/driver.sh: New file. This script
compiles and runs a given simd test, logging its output and
status. It uses the timeout command to implement compile and
test timeouts.
* testsuite/experimental/simd/generate_makefile.sh: New file.
This script generates a Makefile which uses driver.sh to compile
and run the tests and collect the logs into a single log file.
* testsuite/experimental/simd/tests/abs.cc: New file. Tests
abs(simd).
* testsuite/experimental/simd/tests/algorithms.cc: New file.
Tests min/max(simd, simd).
* testsuite/experimental/simd/tests/bits/conversions.h: New
file. Contains functions to support tests involving conversions.
* testsuite/experimental/simd/tests/bits/make_vec.h: New file.
Support functions make_mask and make_vec.
* testsuite/experimental/simd/tests/bits/mathreference.h: New
file. Support functions to supply precomputed math function
reference data.
* testsuite/experimental/simd/tests/bits/metahelpers.h: New
file. Support code for SFINAE testing.
* testsuite/experimental/simd/tests/bits/simd_view.h: New file.
* testsuite/experimental/simd/tests/bits/test_values.h: New
file. Test functions to easily drive a test with simd objects
initialized from a given list of values and a range of random
values.
* testsuite/experimental/simd/tests/bits/ulp.h: New file.
Support code to determine the ULP distance of simd objects.
* testsuite/experimental/simd/tests/bits/verify.h: New file.
Test framework for COMPARE'ing simd objects and instantiating
the test templates with value_type and ABI tag.
* testsuite/experimental/simd/tests/broadcast.cc: New file. Test
simd broadcasts.
* testsuite/experimental/simd/tests/casts.cc: New file. Test
simd casts.
* testsuite/experimental/simd/tests/fpclassify.cc: New file.
Test floating-point classification functions.
* testsuite/experimental/simd/tests/frexp.cc: New file. Test
frexp(simd).
* testsuite/experimental/simd/tests/generator.cc: New file. Test
simd generator constructor.
* testsuite/experimental/simd/tests/hypot3_fma.cc: New file.
Test 3-arg hypot(simd,simd,simd) and fma(simd,simd,sim).
* testsuite/experimental/simd/tests/integer_operators.cc: New
file. Test integer operators.
* testsuite/experimental/simd/tests/ldexp_scalbn_scalbln_modf.cc:
New file. Test ldexp(simd), scalbn(simd), scalbln(simd), and
modf(simd).
* testsuite/experimental/simd/tests/loadstore.cc: New file. Test
(converting) simd loads and stores.
* testsuite/experimental/simd/tests/logarithm.cc: New file. Test
log*(simd).
* testsuite/experimental/simd/tests/mask_broadcast.cc: New file.
Test simd_mask broadcasts.
* testsuite/experimental/simd/tests/mask_conversions.cc: New
file. Test simd_mask conversions.
* testsuite/experimental/simd/tests/mask_implicit_cvt.cc: New
file. Test simd_mask implicit conversions.
* testsuite/experimental/simd/tests/mask_loadstore.cc: New file.
Test simd_mask loads and stores.
* testsuite/experimental/simd/tests/mask_operator_cvt.cc: New
file. Test simd_mask operators convert as specified.
* testsuite/experimental/simd/tests/mask_operators.cc: New file.
Test simd_mask compares, subscripts, and negation.
* testsuite/experimental/simd/tests/mask_reductions.cc: New
file. Test simd_mask reductions.
* testsuite/experimental/simd/tests/math_1arg.cc: New file. Test
1-arg math functions on simd.
* testsuite/experimental/simd/tests/math_2arg.cc: New file. Test
2-arg math functions on simd.
* testsuite/experimental/simd/tests/operator_cvt.cc: New file.
Test implicit conversions on simd binary operators behave as
specified.
* testsuite/experimental/simd/tests/operators.cc: New file. Test
simd compares, subscripts, not, unary minus, plus, minus,
multiplies, divides, increment, and decrement.
* testsuite/experimental/simd/tests/reductions.cc: New file.
Test reduce(simd).
* testsuite/experimental/simd/tests/remqo.cc: New file. Test
remqo(simd).
* testsuite/experimental/simd/tests/simd.cc: New file. Basic
sanity checks of simd types.
* testsuite/experimental/simd/tests/sincos.cc: New file. Test
sin(simd) and cos(simd).
* testsuite/experimental/simd/tests/split_concat.cc: New file.
Test split(simd) and concat(simd, simd).
* testsuite/experimental/simd/tests/splits.cc: New file. Test
split(simd_mask).
* testsuite/experimental/simd/tests/trigonometric.cc: New file.
Test remaining trigonometric functions on simd.
* testsuite/experimental/simd/tests/trunc_ceil_floor.cc: New
file. Test trunc(simd), ceil(simd), and floor(simd).
* testsuite/experimental/simd/tests/where.cc: New file. Test
masked operations using where.

libstdc++: Add std::experimental::simd from the Parallelism TS 2

Adds <experimental/simd>.

This implements the simd and simd_mask class templates via
[[gnu::vector_size(N)]] data members. It implements overloads for all of
<cmath> for simd. Explicit vectorization of the <cmath> functions is not
finished.

The majority of functions are marked as [[gnu::always_inline]] to enable
quasi-ODR-conforming linking of TUs with different -m flags.
Performance optimization was done for x86_64. ARM, Aarch64, and POWER
rely on the compiler to recognize reduction, conversion, and shuffle
patterns.

Besides verification using many different machine flages, the code was
also verified with different fast-math flags.

libstdc++-v3/ChangeLog:

* doc/xml/manual/status_cxx2017.xml: Add implementation status
of the Parallelism TS 2. Document implementation-defined types
and behavior.
* include/Makefile.am: Add new headers.
* include/Makefile.in: Regenerate.
* include/experimental/simd: New file. New header for
Parallelism TS 2.
* include/experimental/bits/numeric_traits.h: New file.
Implementation of P1841R1 using internal naming. Addition of
missing IEC559 functionality query.
* include/experimental/bits/simd.h: New file. Definition of the
public simd interfaces and general implementation helpers.
* include/experimental/bits/simd_builtin.h: New file.
Implementation of the _VecBuiltin simd_abi.
* include/experimental/bits/simd_converter.h: New file. Generic
simd conversions.
* include/experimental/bits/simd_detail.h: New file. Internal
macros for the simd implementation.
* include/experimental/bits/simd_fixed_size.h: New file. Simd
fixed_size ABI specific implementations.
* include/experimental/bits/simd_math.h: New file. Math
overloads for simd.
* include/experimental/bits/simd_neon.h: New file. Simd NEON
specific implementations.
* include/experimental/bits/simd_ppc.h: New file. Implement bit
shifts to avoid invalid results for integral types smaller than
int.
* include/experimental/bits/simd_scalar.h: New file. Simd scalar
ABI specific implementations.
* include/experimental/bits/simd_x86.h: New file. Simd x86
specific implementations.
* include/experimental/bits/simd_x86_conversions.h: New file.
x86 specific conversion optimizations. The conversion patterns
work around missing conversion patterns in the compiler and
should be removed as soon as PR85048 is resolved.
* testsuite/experimental/simd/standard_abi_usable.cc: New file.
Test that all (not all fixed_size<N>, though) standard simd and
simd_mask types are usable.
* testsuite/experimental/simd/standard_abi_usable_2.cc: New
file. As above but with -ffast-math.
* testsuite/libstdc++-dg/conformance.exp: Don't build simd tests
from the standard test loop. Instead use
check_vect_support_and_set_flags to build simd tests with the
relevant machine flags.

tree-optimization/98854 - avoid some PHI BB vectorization

This avoids cases of PHI node vectorization that just causes us
to insert vector CTORs inside loops for values only required
outside of the loop.

2021-01-27 Richard Biener <rguenther@suse.de>

PR tree-optimization/98854
* tree-vect-slp.c (vect_build_slp_tree_2): Also build
PHIs from scalars when the number of CTORs matches the
number of children.

* gcc.dg/vect/bb-slp-pr98854.c: New testcase.

aarch64: Use RTL builtins for integer mls_n intrinsics

Rewrite integer mls_n Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-01-15 Jonathan Wright <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add mls_n builtin
generator macro.
* config/aarch64/aarch64-simd.md (*aarch64_mls_elt_merge<mode>):
Rename to...
(aarch64_mls_n<mode>): This.
* config/aarch64/arm_neon.h (vmls_n_s16): Use RTL builtin
instead of asm.
(vmls_n_s32): Likewise.
(vmls_n_u16): Likewise.
(vmls_n_u32): Likewise.
(vmlsq_n_s16): Likewise.
(vmlsq_n_s32): Likewise.
(vmlsq_n_u16): Likewise.
(vmlsq_n_u32): Likewise.

aarch64: Use RTL builtins for integer mls intrinsics

Rewrite integer mls Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.

gcc/Changelog:

2021-01-11 Jonathan Wright <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add mls builtin
generator macro.
* config/aarch64/arm_neon.h (vmls_s8): Use RTL builtin rather
than asm.
(vmls_s16): Likewise.
(vmls_s32): Likewise.
(vmls_u8): Likewise.
(vmls_u16): Likewise.
(vmls_u32): Likewise.
(vmlsq_s8): Likewise.
(vmlsq_s16): Likewise.
(vmlsq_s32): Likewise.
(vmlsq_u8): Likewise.
(vmlsq_u16): Likewise.
(vmlsq_u32): Likewise.

libstdc++: Optimize std::string_view::find [PR 66414]

This reuses the code from std::string::find, which was improved by
r244225, but string_view was not changed to match.

libstdc++-v3/ChangeLog:

PR libstdc++/66414
* include/bits/string_view.tcc
(basic_string_view::find(const CharT*, size_type, size_type)):
Optimize.

aarch64: Use RTL builtins for integer mla_n intrinsics

Rewrite integer mla_n Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.

gcc/ChangeLog:

2021-01-15 Jonathan Wright <jonathan.wright@arm.com>

* config/aarch64/aarch64-simd-builtins.def: Add mla_n builtin
generator macro.
* config/aarch64/aarch64-simd.md (*aarch64_mla_elt_merge<mode>):
Rename to...
(aarch64_mla_n<mode>): This.
* config/aarch64/arm_neon.h (vmla_n_s16): Use RTL builtin
instead of asm.
(vmla_n_s32): Likewise.
(vmla_n_u16): Likewise.
(vmla_n_u32): Likewise.
(vmlaq_n_s16): Likewise.
(vmlaq_n_s32): Likewise.
(vmlaq_n_u16): Likewise.
(vmlaq_n_u32): Likewise.

libstdc++: Add string contains member functions for C++2b

This implements WG21 P1679R3, adding contains member functions to
basic_string_view and basic_string.

libstdc++-v3/ChangeLog:

* include/bits/basic_string.h (basic_string::contains): New
member functions.
* include/std/string_view (basic_string_view::contains):
Likewise.
* include/std/version (__cpp_lib_string_contains): Define.
* testsuite/21_strings/basic_string/operations/starts_with/char/1.cc:
Remove trailing whitespace.
* testsuite/21_strings/basic_string/operations/starts_with/wchar_t/1.cc:
Likewise.
* testsuite/21_strings/basic_string/operations/contains/char/1.cc: New test.
* testsuite/21_strings/basic_string/operations/contains/wchar_t/1.cc: New test.
* testsuite/21_strings/basic_string_view/operations/contains/char/1.cc: New test.
* testsuite/21_strings/basic_string_view/operations/contains/char/2.cc: New test.
* testsuite/21_strings/basic_string_view/operations/contains/wchar_t/1.cc: New test.

Fortran: Fix ICE due to elemental procedure pointers [PR93924/5].

2021-01-27 Paul Thomas <pault@gcc.gnu.org>

gcc/fortran
PR fortran/93924
PR fortran/93925
* trans-expr.c (gfc_conv_procedure_call): Suppress the call to
gfc_conv_intrinsic_to_class for unlimited polymorphic procedure
pointers.
(gfc_trans_assignment_1): Similarly suppress class assignment
for class valued procedure pointers.

gcc/testsuite/
PR fortran/93924
PR fortran/93925
* gfortran.dg/proc_ptr_52.f90 : New test.

libgcc, i386: Add .note.GNU-stack sections to the ms sse/avx sav/res

On Linux, GCC emits .note.GNU-stack sections when compiling code to mark
the code as not needing or needing executable stack, missing section means
unknown.  But assembly files need to be marked manually.  We already
mark various *.S files in libgcc manually, but the
avx_resms64f.o
avx_resms64fx.o
avx_resms64.o
avx_resms64x.o
avx_savms64f.o
avx_savms64.o
sse_resms64f.o
sse_resms64fx.o
sse_resms64.o
sse_resms64x.o
sse_savms64f.o
sse_savms64.o
files aren't marked, so when something links it in, it will require
executable stack.  Nothing in the assembly requires executable stack though.

2021-01-27  Jakub Jelinek  <jakub@redhat.com>

* config/i386/savms64.h: Add .note.GNU-stack section on Linux.
* config/i386/savms64f.h: Likewise.
* config/i386/resms64.h: Likewise.
* config/i386/resms64f.h: Likewise.
* config/i386/resms64x.h: Likewise.
* config/i386/resms64fx.h: Likewise.

Fix ICE for [PR target/98833].

And replace __builtin_ia32_pcmpeqb128 with operator == in libcpp.

gcc/ChangeLog:

PR target/98833
* config/i386/sse.md (sse2_gt<mode>3): Drop !TARGET_XOP in condition.
(*sse2_eq<mode>3): Ditto.

gcc/testsuite/ChangeLog:

PR target/98833
* gcc.target/i386/pr98833.c: New test.

libcpp/

PR target/98833
* lex.c (search_line_sse2): Replace builtins with == operator.

testsuite: Fix TBAA in {sse,avx}*and*p[sd]*.c tests

This patch drops the no-strict-aliasing hack in m128-check.h and instead
ensures the tests read objects with the right dynamic type.

2021-01-27 Jakub Jelinek <jakub@redhat.com>

* gcc.target/i386/m128-check.h (CHECK_EXP): Remove
optimize ("no-strict-aliasing") attribute.
* gcc.target/i386/sse-andnps-1.c (TEST): Copy e into float[4]
array to avoid violating TBAA.
* gcc.target/i386/sse2-andpd-1.c (TEST): Copy e.d into double[2]
array to avoid violating TBAA.
* gcc.target/i386/sse-andps-1.c (TEST): Copy e.f into float[4]
array to avoid violating TBAA.
* gcc.target/i386/sse2-andnpd-1.c (TEST): Copy e into double[2]
array to avoid violating TBAA.

Fortran: Fix ICE due to elemental procedure pointers [PR98472].

2021-01-27 Paul Thomas <pault@gcc.gnu.org>

gcc/fortran
PR fortran/98472
* trans-array.c (gfc_conv_expr_descriptor): Include elemental
procedure pointers in the assert under the comment 'elemental
function' and eliminate the second, spurious assert.

gcc/testsuite/
PR fortran/98472
* gfortran.dg/elemental_function_5.f90 : New test.

Rename PROP_trees to PROP_gimple

PROP_trees actually means GIMPLE IL, rather than GENERIC, so better
not to confuse users.

2021-01-27 Jakub Jelinek <jakub@redhat.com>

* tree-pass.h (PROP_trees): Rename to ...
(PROP_gimple): ... this.
* cfgexpand.c (pass_data_expand): Replace PROP_trees with PROP_gimple.
* passes.c (execute_function_dump, execute_function_todo,
execute_one_ipa_transform_pass, execute_one_pass): Likewise.
* varpool.c (ctor_for_folding): Likewise.

varpool: Restore GENERIC TREE_READONLY automatic var optimization [PR7260]

In 4.8 and earlier we used to fold the following to 0 during GENERIC folding,
but we don't do that anymore because ctor_for_folding etc. has been turned into a
GIMPLE centric API, but as the testcase shows, it is invoked even during
GENERIC folding and there the automatic vars still should have meaningful
initializers. I've verified that the C++ FE drops TREE_READONLY on
automatic vars with const qualified types if they require non-constant
(runtime) initialization.

2021-01-27 Jakub Jelinek <jakub@redhat.com>

PR tree-optimization/97260
* varpool.c: Include tree-pass.h.
(ctor_for_folding): In GENERIC return DECL_INITIAL for TREE_READONLY
non-TREE_SIDE_EFFECTS automatic variables.

* gcc.dg/tree-ssa/pr97260.c: New test.

Daily bump.

c++: Add support for -std=c++23

Derived from the changes that added C++2a support in 2017.
r8-3237-g026a79f70cf33f836ea5275eda72d4870a3041e5

No C++23 features are added here.
Use of -std=c++23 sets __cplusplus to 202100L.

$ g++ -std=c++23 -dM -E -x c++ - < /dev/null | grep cplusplus
#define __cplusplus 202100L

gcc/
* doc/cpp.texi (__cplusplus): Document value for -std=c++23
or -std=gnu++23.
* doc/invoke.texi: Document -std=c++23 and -std=gnu++23.
* dwarf2out.c (highest_c_language): Recognise C++20 and C++23.
(gen_compile_unit_die): Recognise C++23.

gcc/c-family/
* c-common.h (cxx_dialect): Add cxx23 as a dialect.
* c.opt: Add options for -std=c++23, std=c++2b, -std=gnu++23
and -std=gnu++2b
* c-opts.c (set_std_cxx23): New.
(c_common_handle_option): Set options when -std=c++23 is enabled.
(c_common_post_options): Adjust comments.
(set_std_cxx20): Likewise.

gcc/testsuite/
* lib/target-supports.exp (check_effective_target_c++2a):
Check for C++2a or C++23.
(check_effective_target_c++20_down): New.
(check_effective_target_c++23_only): New.
(check_effective_target_c++23): New.
* g++.dg/cpp23/cplusplus.C: New.

libcpp/
* include/cpplib.h (c_lang): Add CXX23 and GNUCXX23.
* init.c (lang_defaults): Add rows for CXX23 and GNUCXX23.
(cpp_init_builtins): Set __cplusplus to 202100L for C++23.

c++: Invisible refs are not restrict [PR97474]

In this testcase, we refer to the a parameter through a reference in its own
member, which we asserted couldn't happen by marking the parameter as
'restrict'. This assumption could also be broken if the address escapes
from the constructor.

gcc/cp/ChangeLog:

PR c++/97474
* call.c (type_passed_as): Don't mark invisiref restrict.

gcc/testsuite/ChangeLog:

PR c++/97474
* g++.dg/torture/pr97474.C: New test.

c++: constexpr and empty fields [PR97566]

In the discussion of PR98463, Jakub pointed out that in C++17 and up,
cxx_fold_indirect_ref_1 could use the field we build for an empty base.  I
tried implementing that, but it broke one of the tuple tests, so I did some
more digging.

To start with, I generalized the PR98463 patch to handle the case where we
do have a field, for an empty base or [[no_unique_address]] member.  This is
enough also for the no-field case because the member of the empty base must
itself be an empty field; if it weren't, the base would not be empty.

I looked for related PRs and found 97566, which was also fixed by the patch.
After some poking around to figure out why, I noticed that the testcase had
been breaking because E, though an empty class, has an ABI nvsize of one
byte, and we were giving the [[no_unique_address]] FIELD_DECL that
DECL_SIZE, whereas in build_base_field_1 empty base fields always get
DECL_SIZE zero, and various places were relying on that to recognize empty
fields.  So I adjusted both the size and the checking.  When I adjusted
check_bases I wondered if we were correctly handling bases with only empty
data members, but it appears we do.

I'm deferring the cxx_fold_indirect_ref_1 change until stage 1, as I don't
think it actually fixes anything.

gcc/cp/ChangeLog:

PR c++/97566
PR c++/98463
* class.c (layout_class_type): An empty field gets size 0.
(is_empty_field): New.
(check_bases): Check it.
* cp-tree.h (is_empty_field): Declare it.
* constexpr.c (cxx_eval_store_expression): Check it.
(cx_check_missing_mem_inits): Likewise.
* init.c (perform_member_init): Likewise.
* typeck2.c (process_init_constructor_record): Likewise.

gcc/testsuite/ChangeLog:

PR c++/97566
* g++.dg/cpp2a/no_unique_address10.C: New test.
* g++.dg/cpp2a/no_unique_address9.C: New test.

testsuite: Fix TBAA in sse*and*p[sd]*.c tests

This patch drops the no-strict-aliasing hack in m128-check.h and instead
ensures the tests read objects with the right dynamic type.

2021-01-26 Jakub Jelinek <jakub@redhat.com>

* gcc.target/powerpc/m128-check.h (CHECK_EXP): Remove
optimize ("no-strict-aliasing") attribute.
* gcc.target/powerpc/sse-andnps-1.c (TEST): Copy e into float[4]
array to avoid violating TBAA.
* gcc.target/powerpc/sse2-andpd-1.c (TEST): Copy e.d into double[2]
array to avoid violating TBAA.
* gcc.target/powerpc/sse-andps-1.c (TEST): Copy e.f into float[4]
array to avoid violating TBAA.
* gcc.target/powerpc/sse2-andnpd-1.c (TEST): Copy e into double[2]
array to avoid violating TBAA.

Fix PR ada/98228

This is the profiled bootstrap failure for s390x/Linux on the mainline,
which has been introduced by the modref pass but actually exposing an
existing issue in the maybe_pad_type function that is visible on s390x.

The issue is too weak a test for the addressability of the inner component.

gcc/ada/
Marius Hillenbrand <mhillen@linux.ibm.com>

PR ada/98228
* gcc-interface/utils.c (maybe_pad_type): Test the size of the new
packable type instead of its alignment for addressability's sake.

dwarf2asm: Fix bootstrap on powerpc*-*-* [PR98839]

My recent dwarf2asm.c patch broke powerpc*-*-* bootstrap, while most target
define POINTER_SIZE to (cond ? cst1 : cst2) or constant, rs6000 defines
it to a variable, and the arbitrarily chosen type of that variable determines
whether we get warnings on comparison of that against signed or unsigned
ints.

Fixed by adding a cast.

2021-01-26 Jakub Jelinek <jakub@redhat.com>

PR bootstrap/98839
* dwarf2asm.c (dw2_assemble_integer): Cast DWARF2_ADDR_SIZE to int
in comparison.

aarch64: Tighten up checks for ubfix [PR98681]

The testcase in the patch doesn't assemble, because the instruction requires
that the penultimate operand (lsb) range is [0, 32] (or [0, 64]) and the last
operand's range is [1, 32 - lsb] (or [1, 64 - lsb]).
The INTVAL (shft_amnt) < GET_MODE_BITSIZE (mode) will accept the lsb operand
to be in range [MIN, 32] (or [MIN, 64]) and then we invoke UB in the
compiler and sometimes it will make it through.
The patch changes all the INTVAL uses in that function to UINTVAL,
which isn't strictly necessary, but can be done (e.g. after the
UINTVAL (shft_amnt) < GET_MODE_BITSIZE (mode) check we know it is not
negative and thus INTVAL (shft_amnt) and UINTVAL (shft_amnt) then behave the
same.  But, I had to add INTVAL (mask) > 0 check in that case, otherwise we
risk (hypothetically) emitting instruction that doesn't assemble.
The problem is with masks that have the MSB bit set, while the instruction
can handle those, e.g.
ubfiz w1, w0, 13, 19
will do
(w0 << 13) & 0xffffe000
in RTL we represent SImode constants with MSB set as negative HOST_WIDE_INT,
so it will actually be HOST_WIDE_INT_C (0xffffffffffffe000), and
the instruction uses %P3 to print the last operand, which calls
asm_fprintf (f, "%u", popcount_hwi (INTVAL (x)))
to print that.  But that will not print 19, but 51 instead, will include
there also all the copies of the sign bit.
Not supporting those masks with MSB set isn't a big loss though, they really
shouldn't appear normally, as both GIMPLE and RTL optimizations should
optimize those away (one isn't masking any bits off with such masks, so
just w0 << 13 will do too).

2021-01-26  Jakub Jelinek  <jakub@redhat.com>

PR target/98681
* config/aarch64/aarch64.c (aarch64_mask_and_shift_for_ubfiz_p):
Use UINTVAL (shft_amnt) and UINTVAL (mask) instead of INTVAL (shft_amnt)
and INTVAL (mask).  Add && INTVAL (mask) > 0 condition.

* gcc.c-torture/execute/pr98681.c: New test.

Fix dumping of VEC_WIDEN_{PLUS,MINUS}_{LO,HI}_EXPR

This avoids dumping them as <<< ??? >>>.

2021-01-26 Richard Biener <rguenther@suse.de>

* gimple-pretty-print.c (dump_binary_rhs): Handle
VEC_WIDEN_{PLUS,MINUS}_{LO,HI}_EXPR.

middle-end/98726 - fix VECTOR_CST element access

This fixes VECTOR_CST element access with POLY_INT elements and
allows to produce dump files of the PR98726 testcase without
ICEing.

2021-01-26 Richard Biener <rguenther@suse.de>

PR middle-end/98726
* tree.h (vector_cst_int_elt): Remove.
* tree.c (vector_cst_int_elt): Use poly_wide_int for computations,
make static.

liblsan: build missing lsan_posix.cpp file

libsanitizer/ChangeLog:

PR sanitizer/98828
* lsan/Makefile.am: Add missing lsan_posix.cpp file.
* lsan/Makefile.in: Likewise.

libgcov: improve profile reproducibility

libgcc/ChangeLog:

PR gcov-profile/98739
* libgcov.h (gcov_topn_add_value): Do not train when
we have a merged profile with a negative number of total
value.

Commit test case for PR 67539.

gcc/testsuite/ChangeLog:

PR fortran/67539
* gfortran.dg/elemental_assignment_1.f90: New test.

testsuite/g++.dg/modules/modules.exp: Janitorial fixes

gcc/testsuite/ChangeLog:

* g++.dg/modules/modules.exp: Remove unused CXX_MODULE_PATH;
add previously missing space in '$ident link'.

amdgcn: Allow V64DFmode min/max reductions

I don't know why these were disabled. There're no direct min/max DPP
instructions for this mode, but the "use moves" strategy works fine.

gcc/ChangeLog:

* config/gcn/gcn.c (gcn_expand_reduc_scalar): Use move instructions
for V64DFmode min/max reductions.

d: Merge upstream dmd 609c3ce2d, phobos 3dd5df686

D front-end changes:

- Contracts for pre- and postconditions are now implicitly "this"
   const, so that state can no longer be altered in these functions.

- Inside a constructor scope, assigning to aggregate declaration
   members is done by considering the first assignment as initialization
   and subsequent assignments as modifications of the constructed
   object.  For const/immutable fields the initialization is accepted in
   the constructor but subsequent modifications are not.  However this
   rule did not apply when inside a constructor scope there is a call to
   a different constructor.  This been changed so it is now an error
   when there's a double initialization of immutable fields inside a
   constructor.

Phobos changes:

- Don't run unit-tests for unsupported clocks in std.datetime.  The
   phobos and phobos_shared tests now add -fversion=Linux_Pre_2639 if
   required.

- Deprecate public extern(C) bindings for getline and getdelim in
   std.stdio.  The correct module for bindings is core.sys.posix.stdio.

Reviewed-on: https://github.com/dlang/dmd/pull/12153
     https://github.com/dlang/phobos/pull/7768

gcc/d/ChangeLog:

* dmd/MERGE: Merge upstream dmd 609c3ce2d.
* d-compiler.cc (Compiler::loadModule): Rename to ...
(Compiler::onParseModule): ... this.
(Compiler::onImport): New function.
* d-lang.cc (d_parse_file): Remove call to Compiler::loadModule.

libphobos/ChangeLog:

* src/MERGE: Merge upstream phobos 3dd5df686.
* testsuite/libphobos.phobos/phobos.exp: Add compiler flag
-fversion=Linux_Pre_2639 if target is linux_pre_2639.
* testsuite/libphobos.phobos_shared/phobos_shared.exp: Likewise.

testsuite: Fix up pr98807.c on i686-linux [PR98807]

The new testcase FAILs on i686-linux with:
gcc/testsuite/gcc.dg/pr98807.c: In function 'foo0':
gcc/testsuite/gcc.dg/pr98807.c:20:1: warning: SSE vector return without SSE enabled changes the ABI [-Wpsabi]
gcc/testsuite/gcc.dg/pr98807.c:19:1: note: the ABI for passing parameters with 16-byte alignment has changed in GCC 4.6
gcc/testsuite/gcc.dg/pr98807.c:19:1: warning: SSE vector argument without SSE enabled changes the ABI [-Wpsabi]
FAIL: gcc.dg/pr98807.c (test for excess errors)

Adding usual testcase treatment for such cases.

2021-01-26 Jakub Jelinek <jakub@redhat.com>

PR middle-end/98807
* gcc.dg/pr98807.c: Add -Wno-psabi -w to dg-options.

dwarf2asm: Fix up -gdwarf-64 for 32-bit targets

For the 32-bit targets the limitations of the object
file format (e.g. 32-bit ELF) will not allow > 2GiB debug info anyway,
and as I've just tested, e.g. on x86_64 with -m32 -gdwarf64 will not work
even on tiny testcases:
as: pr64716.o: unsupported relocation type: 0x1
pr64716.s: Assembler messages:
pr64716.s:6013: Error: cannot represent relocation type BFD_RELOC_64
as: pr64716.o: unsupported relocation type: 0x1
pr64716.s:6015: Error: cannot represent relocation type BFD_RELOC_64
as: pr64716.o: unsupported relocation type: 0x1
pr64716.s:6017: Error: cannot represent relocation type BFD_RELOC_64
So yes, we can either do a sorry, error, or could just avoid 64-bit
relocations (depending on endianity instead of emitting
.quad expression_that_needs_relocation
emit
.long expression_that_needs_relocation, 0
or
.long 0, expression_that_needs_relocation

This patch implements that last option, dunno if we need also configure tests
for that or not, maybe some 32-bit targets use 64-bit ELF and can handle such
relocations.

> 64bit relocs are not required here? That is, can one with
> dwarf64 choose 32bit forms for select offsets (like could
> dwz exploit this?)?

I guess it depends on whether for 32-bit target and -gdwarf64, when
calling dw2_assemble_integer with non-CONST_INT argument we only
need positive values or might need negative ones too.
Because positive ones can be easily emulated through that
.long expression, 0
or
.long 0, expression
depending on endianity, but I'm afraid there is no way to emit
0 or -1 depending on the sign of expression, when it needs relocations.
Looking through dw2_asm_output_delta calls, at least the vast majority
of the calls seem to guarantee being positive, not 100% sure about
one case in .debug_line views, but I'd hope it is ok too.
In most cases, the deltas are between two labels where the first one
in the arguments is later in the same section than the other one,
or where the second argument is the start of a section or another section
base.

2021-01-26 Jakub Jelinek <jakub@redhat.com>

* dwarf2asm.c (dw2_assemble_integer): Handle size twice as large
as DWARF2_ADDR_SIZE if x is not a scalar int by emitting it as
two halves, one with x and the other with const0_rtx, ordered
depending on endianity.

skip asan-poisoning of discarded vars

GNAT may create temporaries to hold return values of function calls.
If such a temporary is created as part of a dynamic initializer of a
variable in a unit other than the one being compiled, the initializer
is dropped, including the temporary and its binding block.

Don't issue asan mark calls for such variables, they are gone.

for gcc/ChangeLog

* gimplify.c (gimplify_decl_expr): Skip asan marking calls for
temporaries not seen in binding block, and not about to be
added as gimple variables.

for gcc/testsuite/ChangeLog

* gnat.dg/asan1.adb: New test.
* gnat.dg/asan1_pkg.ads: New additional source.

Daily bump.

PR fortran/70070 - ICE on initializing character data beyond min/max bound

Check for initialization of substrings beyond bounds in DATA statements.

gcc/fortran/ChangeLog:

PR fortran/70070
* data.c (create_character_initializer): Check substring indices
against bounds.
(gfc_assign_data_value): Catch error returned from
create_character_initializer.

gcc/testsuite/ChangeLog:

PR fortran/70070
* gfortran.dg/pr70070.f90: New test.

PR c++/98646 - spurious -Wnonnull calling a member on the result of static_cast

gcc/c-family/ChangeLog:

PR c++/98646
* c-common.c (check_nonnull_arg): Adjust warning text.

gcc/cp/ChangeLog:

PR c++/98646
* cvt.c (cp_fold_convert): Propagate TREE_NO_WARNING.

gcc/ChangeLog:

PR c++/98646
* tree-ssa-ccp.c (pass_post_ipa_warn::execute): Adjust warning text.

gcc/testsuite/ChangeLog:

PR c++/98646
* g++.dg/warn/Wnonnull5.C: Adjust text of an expected warning.
* g++.dg/warn/Wnonnull10.C: New test.
* g++.dg/warn/Wnonnull9.C: New test.

Commit test case for PR 96386.

gcc/testsuite/ChangeLog:

* gfortran.dg/associate_57.f90: New test.

Add test case for PR 96843.

gcc/testsuite/ChangeLog:

PR fortran/96843
* gfortran.dg/interface_assignment_7.f90: New test.

libgomp: Add documentation for omp_fulfill_event runtime function

2021-01-25 Kwok Cheung Yeung <kcy@codesourcery.com>

libgomp/
* libgomp.texi (omp_fulfill_event): New entry.

Fix wrong format for fprintf.

gcc/ChangeLog:

* value-prof.c (get_nth_most_common_value): Use %s instead
of %qs string.

c++: [[no_unique_address]] in empty base [PR98463]

In this testcase, cxx_eval_store_expression got confused trying to build up
CONSTRUCTORs for initializing a subobject because the subobject is a member
of an empty base. In C++14 mode and below we don't build FIELD_DECLs for
empty bases, so the CONSTRUCTOR skipped the empty base, and treated the
member as a member of the derived class, which breaks.

Fixed by recognizing this situation and giving up on trying to build a
CONSTRUCTOR for the inner target at that point; since it doesn't have any
data, we don't need to actually store anything.

gcc/cp/ChangeLog:

PR c++/98463
* constexpr.c (get_or_insert_ctor_field): Add check.
(cxx_eval_store_expression): Handle discontinuity of refs.

gcc/testsuite/ChangeLog:

PR c++/98463
* g++.dg/cpp2a/no_unique_address8.C: New test.

gcc/fortran/intrinsic.texi: Fix typos

gcc/fortran/ChangeLog:

* intrinsic.texi (CO_BROADCAST, CO_MIN, CO_REDUCE, CO_SUM): Fix typos.

configure: Add workaround for buggy binutils 2.35 [PR98811]

binutils since https://sourceware.org/bugzilla/show_bug.cgi?id=25612
changes from March last year until the
https://sourceware.org/pipermail/binutils/2020-August/112684.html
fix in early August emits incorrect .debug_info when assembling files
with --gdwarf-5.  Instead of emitting proper DWARF 5 .debug_info header,
it emits DWARF 4 .debug_info header with 5 as the dwarf version instead of
4.  This results e.g. in libgcc.a (morestack.o) having garbage in its
.debug_info sections and e.g. libbacktrace during pretty much all libgo
tests fails miserably.

The following patch adds a workaround for that, don't set
HAVE_AS_GDWARF_5_DEBUG_FLAG if readelf can't read the .debug_info back.

Built tested on x86_64-linux against both binutils 2.35 (buggy ones) and
latest binutils trunk, the former with the patch now has DWARF 3
.debug_line and DWARF 2 .debug_info in morestack.o, while the latter
as before correct DWARF 5 .debug_line and .debug_info.

2021-01-25  Jakub Jelinek  <jakub@redhat.com>

PR debug/98811
* configure.ac (HAVE_AS_GDWARF_5_DEBUG_FLAG): Only define if
readelf -wi is able to read the emitted .debug_info back.
* configure: Regenerated.

Enable -fprofile-reproducible=parallel-runs for profiledbootstrap.

ChangeLog:

PR gcov-profile/98739
* Makefile.in: Enable -fprofile-reproducible=parallel-runs
for profiledbootstrap.

Restore profile reproducibility.

gcc/ChangeLog:

PR gcov-profile/98739
* common.opt: Add missing sign symbol.
* value-prof.c (get_nth_most_common_value): Restore handling
of PROFILE_REPRODUCIBILITY_PARALLEL_RUNS and
PROFILE_REPRODUCIBILITY_MULTITHREADED.

libgcc/ChangeLog:

PR gcov-profile/98739
* libgcov-merge.c (__gcov_merge_topn): Mark when merging
ends with a dropped counter.
* libgcov.h (gcov_topn_add_value): Add return value.

middle-end/98807 - more vector_element_bits fixes

This simplifies vector_element_bits further, avoiding any mode
dependence and instead relying on boolean vector construction
to populate element precision accordingly.

2021-01-25 Richard Biener <rguenther@suse.de>

PR middle-end/98807
* tree.c (vector_element_bits): Always use precision of
the element type for boolean vectors.

* gcc.dg/pr98807.c: New testcase.

RTEMS: Fix default linker script

We have to use ENDFILE_SPEC for the default linker script and not
STARTFILE_SPEC, since STARTFILE_SPEC is place before the user provided
library search paths.

gcc/

* config/rtems.h (STARTFILE_SPEC): Remove qnolinkcmds.
(ENDFILE_SPEC): Evaluate qnolinkcmds.

Fix internal error on extension with interface at -O2

This is a regression present on the mainline, 10 and 9 branches, in the
form of an internal error with the Ada compiler when a covariant-only
thunk is inlined into its caller.

gcc/ada/
* gcc-interface/trans.c (make_covariant_thunk): Set the DECL_CONTEXT
of the parameters and do not set TREE_PUBLIC on the thunk.
(maybe_make_gnu_thunk): Pass the alias to the covariant thunk.
* gcc-interface/utils.c (finish_subprog_decl): Set the DECL_CONTEXT
of the parameters here...
(begin_subprog_body): ...instead of here.

gcc/testsuite/
* gnat.dg/thunk2.adb, gnat.dg/thunk2.ads: New test.
* gnat.dg/thunk2_pkg.ads: New helper.

Fortran: Fix deferred character lengths in array constructors [PR98517].

2021-01-25 Steve Kargl <kargl@gcc.gnu.org>

gcc/fortran
PR fortran/98517
* resolve.c (resolve_charlen): Check that length expression is
present before testing for scalar/integer..

gcc/testsuite/
PR fortran/98517
* gfortran.dg/charlen_18.f90 : New test.

RTEMS: Fix GCC specification

The use of -nostdlib and -nodefaultlibs disables the processing of
LIB_SPEC (%L) as specified by LINK_COMMAND_SPEC and thus disables the
default linker script for RTEMS.  Move the linker script to
STARTFILE_SPEC which is controlled by -nostdlib and -nostartfiles.  This
fits better since the linker script defines the platform start file
provided by the board support package in RTEMS.

gcc/

* config/rtems.h (STARTFILE_SPEC): Remove nostdlib and
nostartfiles handling since this is already done by
LINK_COMMAND_SPEC.  Evaluate qnolinkcmds.
(ENDFILE_SPEC): Remove nostdlib and nostartfiles handling since this
is already done by LINK_COMMAND_SPEC.
(LIB_SPECS): Remove nostdlib and nodefaultlibs handling since
this is already done by LINK_COMMAND_SPEC.  Remove qnolinkcmds
evaluation.

fold: Fix up strn{case,}cmp folding [PR98771]

As mentioned in the PR, the compiler behaves differently during strncmp
and strncasecmp folding between 32-bit and 64-bit hosts targeting 64-bit
target.  I think that is highly undesirable.

The culprit is the host_size_t_cst_p predicate that is used by
fold_const_call, which punts if the target size_t constants don't fit into
host size_t.  This patch gets rid of that behavior, instead it punts the
same when it doesn't fit into uhwi.

The predicate was used for strncmp and strncasecmp folding and for bcmp, memcmp and
memchr folding.
The constant is in all cases compared to 0, we can do that whether it fits
into size_t or unsigned HOST_WIDE_INT, then it is used in s2 <= s0 or
s2 <= s1 comparisons where s0 and s1 already have uhwi type and represent
the sizes of the objects.
The important difference is for strn{,case}cmp folding, we pass that s2
value as the last argument to the host functions comparing the c_getstr
results.  If s2 fits into size_t, then my patch makes no difference,
but if it is larger, we know the 2 c_getstr objects need to fit into the
host address space, so larger s2 should just act essentially as strcmp
or strcasecmp; as none of those objects can occupy 100% of the address
space, using MIN (SIZE_MAX, s2) achieves that.

2021-01-25  Jakub Jelinek  <jakub@redhat.com>

PR testsuite/98771
* fold-const-call.c (host_size_t_cst_p): Renamed to ...
(size_t_cst_p): ... this.  Check and store unsigned HOST_WIDE_INT
value rather than host size_t.
(fold_const_call): Change type of s2 from size_t to
unsigned HOST_WIDE_INT.  Use size_t_cst_p instead of
host_size_t_cst_p.  For strncmp calls, pass MIN (s2, SIZE_MAX)
instead of s2 as last argument.

Arm: Add NEON and MVE complex mul, mla and mls patterns.

This adds implementation for the optabs for complex operations.  With this the
following C code:

  void g (float complex a[restrict N], float complex b[restrict N],
  float complex c[restrict N])
  {
    for (int i=0; i < N; i++)
      c[i] =  a[i] * b[i];
  }

generates

NEON:

g:
        vmov.f32        q11, #0.0  @ v4sf
        add     r3, r2, #1600
.L2:
        vmov    q8, q11  @ v4sf
        vld1.32 {q10}, [r1]!
        vld1.32 {q9}, [r0]!
        vcmla.f32       q8, q9, q10, #0
        vcmla.f32       q8, q9, q10, #90
        vst1.32 {q8}, [r2]!
        cmp     r3, r2
        bne     .L2
        bx      lr

MVE:

g:
        push    {lr}
        mov     lr, #100
        dls     lr, lr
.L2:
        vldrw.32        q1, [r1], #16
        vldrw.32        q2, [r0], #16
        vcmul.f32       q3, q2, q1, #0
        vcmla.f32       q3, q2, q1, #90
        vstrw.32        q3, [r2], #16
        le      lr, .L2
        ldr     pc, [sp], #4

instead of

g:
        add     r3, r2, #1600
.L2:
        vld2.32 {d20-d23}, [r0]!
        vld2.32 {d16-d19}, [r1]!
        vmul.f32        q14, q11, q9
        vmul.f32        q15, q11, q8
        vneg.f32        q14, q14
        vfma.f32        q15, q10, q9
        vfma.f32        q14, q10, q8
        vmov    q13, q15  @ v4sf
        vmov    q12, q14  @ v4sf
        vst2.32 {d24-d27}, [r2]!
        cmp     r3, r2
        bne     .L2
        bx      lr

and

g:
        add     r3, r2, #1600
.L2:
        vld2.32 {d20-d23}, [r0]!
        vld2.32 {d16-d19}, [r1]!
        vmul.f32        q15, q10, q8
        vmul.f32        q14, q10, q9
        vmls.f32        q15, q11, q9
        vmla.f32        q14, q11, q8
        vmov    q12, q15  @ v4sf
        vmov    q13, q14  @ v4sf
        vst2.32 {d24-d27}, [r2]!
        cmp     r3, r2
        bne     .L2
        bx      lr

respectively.

gcc/ChangeLog:

* config/arm/iterators.md (rotsplit1, rotsplit2, conj_op, fcmac1,
VCMLA_OP, VCMUL_OP): New.
* config/arm/mve.md (mve_vcmlaq<mve_rot><mode>): Support vec_dup 0.
* config/arm/neon.md (cmul<conj_op><mode>3): New.
* config/arm/unspecs.md (UNSPEC_VCMLA_CONJ, UNSPEC_VCMLA180_CONJ,
UNSPEC_VCMUL_CONJ): New.
* config/arm/vec-common.md (cmul<conj_op><mode>3, arm_vcmla<rot><mode>,
cml<fcmac1><conj_op><mode>4): New.

Daily bump.

libphobos: Fix executables segfault on mipsel architecture

The dynamic section on MIPS is read-only, but this was not properly
handled in the runtime library. The segfault only occurred for programs
that linked to the shared libphobos library.

libphobos/ChangeLog:

PR d/98806
* libdruntime/gcc/sections/elf_shared.d (MIPS_Any): Declare version
for MIPS32 and MIPS64.
(getDependencies): Adjust dlpi_addr on MIPS_Any.