Instead of MUXCY/XORCY use CARRY4 (with timing)

Pad all boxes so that all input/output connections specified

Modify LUT area cost to be same as old abc

Merge remote-tracking branch 'origin/master' into xc7mux

Merge pull request #1017 from Kmanfi/bigger_verilog_files

Read bigger Verilog files.

Read bigger Verilog files.

Hit parser limit with 3M gate design. This commit fix it.

Merge pull request #1013 from antmicro/parameter_attributes

Support for attributes on parameters and localparams for Verilog frontend

Added tests for Verilog frontent for attributes on parameters and localparams

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored.

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Merge pull request #1012 from YosysHQ/clifford/sigspecrw

Another rounds of opt_clean improvements

Improvements in opt_clean

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add rewrite_sigspecs2, Improve remove() wires

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Do not leak file descriptors in cover.cc

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #1011 from hzeller/fix-constructing-string-from-int

Fix two instances of integer-assignment to string.

Merge pull request #1010 from hzeller/yacc-self-contained

Make the generated *.tab.hh include all the headers needed

Merge pull request #1008 from thasti/fix_libyosys_build

Create $(LIBDIR) to fix broken build in isolated environments

Merge pull request #1005 from smunaut/ice40_hfosc_trim

ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC

Fix two instances of integer-assignment to string.

o In cover.cc, the int-result of mkstemps() was assigned to a string
  and silently interpreted as a single-character filename with a funny
  value. Fix with the intent: assign the filename.
o in libparse.cc, an int was assigned to a string, but depending on
  visible constructors, this is ambiguous. Explicitly cast this to
  a char.

Make the generated *.tab.hh include all the headers needed to define the union.

extract python prefix to allow overriding

remove ldconfig call

add mkdir for libyosys target, explicitly copy to target folder

bugpoint: check for -script option.

Fixes #925.

ice40/cells_sim.v: Add support for TRIM input to SB_HFOSC

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

Merge pull request #1004 from YosysHQ/clifford/fix1002

Fix handling of glob_abort_cnt in opt_muxtree

Fix handling of glob_abort_cnt in opt_muxtree, fixes #1002

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #1003 from makaimann/zinit-all

Zinit option '-singleton' -> '-all'

Add "fmcombine -initeq -anyeq"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "stat -tech xilinx"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Zinit option '-singleton' -> '-all'

Merge pull request #1000 from bwidawsk/synth-format

Add clang format, and use on intel_synth (v2)

Fix formatting for synth_intel.cc

This is realized through the recently added .clang-format file.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Add a .clang-format

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Add $stop to documentation

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Remove added newline (by re-running minisat 00_UPDATE.sh)

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #991 from kristofferkoch/gcc9-warnings

Fix all warnings that occurred when compiling with gcc9

Fix all warnings that occurred when compiling with gcc9

Merge pull request #998 from mdaiter/get_bool_attribute_opts

Minor optimization to get_attribute_bool

Minor optimization to get_attribute_bool

Add test case from #997

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix handling of partial init attributes in write_verilog, fixes #997

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #996 from mdaiter/ceil_log2_opts

Optimize ceil_log2 function

Optimize ceil_log2 function

Add "synth_xilinx -arch"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

More opt_clean cleanups

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #946 from YosysHQ/clifford/specify

Add specify parser

Merge pull request #975 from YosysHQ/clifford/fix968

Re-enable "final loop assignment" feature and fix opt_clean warnings

Merge pull request #871 from YosysHQ/verific_import

Improve verific -chparam and add hierarchy -chparam

Add tests/various/chparam.sh

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968

Fix the other bison warning in ilang_parser.y

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Bugfix in peepopt_shiftmul.pmg

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #992 from bwidawsk/bison-fix

verilog_parser: Fix Bison warning

Merge pull request #989 from YosysHQ/dave/abc_name_improve

ABC name recovery fixes

Fix bug in "expose -input"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Cleanups in opt_clean

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve tests/various/specify.ys

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "real" keyword to ilang format

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify

verilog_parser: Fix Bison warning

As of Bison 2.6, name-prefix is deprecated. This fixes
frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated]
 %name-prefix "frontend_verilog_yy"

For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html

Compile tested only.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>

Merge pull request #988 from YosysHQ/clifford/fix987

Add approximate support for SV "var" keyword

abc: Fix handling of postfixed names (e.g. for retiming)

Signed-off-by: David Shah <dave@ds0.me>

abc: Improve name recovery

Signed-off-by: David Shah <dave@ds0.me>

Improve opt_clean handling of unused wires

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add support for SVA "final" keyword

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve write_verilog specify support

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update README

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add approximate support for SV "var" keyword, fixes #987

Signed-off-by: Clifford Wolf <clifford@clifford.at>

More testing

Fix spacing

Add quick-and-dirty specify tests

Merge remote-tracking branch 'origin/master' into clifford/specify

Rename cells_map.v to prevent clash with ff_map.v

iverilog with simcells.v as well

Add "hierarchy -chparam" support for non-verific top modules

Signed-off-by: Clifford Wolf <clifford@clifford.at>

log_warning_noprefix -> log_warning as per review

For hier_tree::Elaborate() also include SV root modules (bind)

Fix verific_parameters construction, use attribute to mark top netlists

WIP -chparam support for hierarchy when verific

verific_import() changes to avoid ElaborateAll()

Merge pull request #969 from YosysHQ/clifford/pmgenstuff

Improve pmgen, Add "peepopt" pass with shift-mul pattern

Merge pull request #984 from YosysHQ/eddie/fix_982

dffinit to do nothing when (* init *) value is 1'bx

Revert "synth_xilinx to call dffinit with -noreinit"

This reverts commit 1f62dc9081feb4852b1848d01951f631853edb38.

If init is 1'bx, do not add to dict as per @cliffordwolf

Revert "dffinit -noreinit to silently continue when init value is 1'bx"

This reverts commit aa081f83c791b1d666214776aaf744a80ce6a690.

Merge pull request #976 from YosysHQ/clifford/fix974

Fix width detection of memory access with bit slice

Merge pull request #985 from YosysHQ/clifford/fix981

Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires

Fix typo in tests/svinterfaces/runone.sh

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #979 from jakobwenzel/svinterfacesTestcase

fail svinterfaces testcases on yosys error exit

Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires, fixes #981

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Further improve unused-detection for opt_clean driver-driver conflict warning

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve unused-detection for opt_clean driver-driver conflict warning

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update pmgen documentation

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix typo

Signed-off-by: Clifford Wolf <clifford@clifford.at>

synth_xilinx to call dffinit with -noreinit

dffinit -noreinit to silently continue when init value is 1'bx

Trim off leading 1'bx in A

Add don't care optimisation

Use new peepopt from #969

Merge remote-tracking branch 'origin/clifford/pmgenstuff' into xc7mux