Brandon Potter [Fri, 24 Jul 2015 19:25:22 +0000 (12:25 -0700)]
syscall_emul: file descriptor interface changes
This patch gets rid of unused Process::dup_fd method and does minor
refactoring in the process class files. The file descriptor max has been
changed to be the number of file descriptors since this clarifies the loop
boundary condition and cleans up the code a bit. The fd_map field has been
altered to be dynamically allocated as opposed to being an array; the
intention here is to build on this is subsequent patches to allow processes
to share their file descriptors with the clone system call.
Brandon Potter [Fri, 24 Jul 2015 19:25:22 +0000 (12:25 -0700)]
ruby: dma sequencer: removes redundant code
Nilay Vaish [Wed, 22 Jul 2015 16:20:07 +0000 (11:20 -0500)]
ruby: network: NetworkLink inherits from Consumer now.
Nilay Vaish [Tue, 21 Jul 2015 15:08:25 +0000 (10:08 -0500)]
configs: network test: remove redundant physical memory
Nilay Vaish [Sat, 18 Jul 2015 20:07:35 +0000 (15:07 -0500)]
stats: x86: updates due to patch on vex
Nilay Vaish [Fri, 17 Jul 2015 16:31:22 +0000 (11:31 -0500)]
x86: decode instructions with vex prefix
This patch updates the x86 decoder so that it can decode instructions with vex
prefix. It also updates the isa with opcodes from vex opcode maps 1, 2 and 3.
Note that none of the instructions have been implemented yet. The
implementations would be provided in due course of time.
Gabor Dozsa [Thu, 16 Jul 2015 00:53:50 +0000 (19:53 -0500)]
dev: add support for multi gem5 runs
Multi gem5 is an extension to gem5 to enable parallel simulation of a
distributed system (e.g. simulation of a pool of machines
connected by Ethernet links). A multi gem5 run consists of seperate gem5
processes running in parallel (potentially on different hosts/slots on
a cluster). Each gem5 process executes the simulation of a component of the
simulated distributed system (e.g. a multi-core board with an Ethernet NIC).
The patch implements the "distributed" Ethernet link device
(dev/src/multi_etherlink.[hh.cc]). This device will send/receive
(simulated) Ethernet packets to/from peer gem5 processes. The interface
to talk to the peer gem5 processes is defined in dev/src/multi_iface.hh and
in tcp_iface.hh.
There is also a central message server process (util/multi/tcp_server.[hh,cc])
which acts like an Ethernet switch and transfers messages among the gem5 peers.
A multi gem5 simulations can be kicked off by the util/multi/gem5-multi.sh
wrapper script.
Checkpoints are supported by multi-gem5. The checkpoint must be
initiated by a single gem5 process. E.g., the gem5 process with rank 0
can take a checkpoint from the bootscript just before it invokes
'mpirun' to launch an MPI test. The message server process will notify
all the other peer gem5 processes and make them take a checkpoint, too
(after completing a global synchronisation to ensure that there are no
inflight messages among gem5).
Andreas Hansson [Mon, 13 Jul 2015 12:46:28 +0000 (08:46 -0400)]
mem: Fix (ab)use of emplace to avoid temporary object creation
Andreas Hansson [Mon, 13 Jul 2015 12:46:16 +0000 (08:46 -0400)]
mem: Updated DRAMSim2 wrapper to new drain API
Somehow this one slipped through without being updated.
Brandon Potter [Fri, 10 Jul 2015 21:05:24 +0000 (16:05 -0500)]
ruby: replace global g_abs_controls with per-RubySystem var
This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.
The list of abstract controllers is per-RubySystem and should be
represented that way, rather than as a global.
Since this is the last remaining Ruby global variable, the
src/mem/ruby/Common/Global.* files are also removed.
Brandon Potter [Fri, 10 Jul 2015 21:05:23 +0000 (16:05 -0500)]
ruby: replace global g_system_ptr with per-object pointers
This is another step in the process of removing global variables
from Ruby to enable multiple RubySystem instances in a single simulation.
With possibly multiple RubySystem objects, we can no longer use a global
variable to find "the" RubySystem object. Instead, each Ruby component
has to carry a pointer to the RubySystem object to which it belongs.
Brandon Potter [Fri, 10 Jul 2015 21:05:23 +0000 (16:05 -0500)]
ruby: replace g_ruby_start with per-RubySystem m_start_cycle
This patch begins the process of removing global variables from the Ruby
source with the goal of eventually allowing users to create multiple Ruby
instances in a single simulation. Currently, users cannot do so because
several global variables and static members are referenced by the RubySystem
object in a way that assumes that there will only ever be a single RubySystem.
These need to be replaced with per-RubySystem equivalents.
This specific patch replaces the global var g_ruby_start, which is used
to calculate throughput statistics for Throttles in simple networks and
links in Garnet networks, with a RubySystem instance var m_start_cycle.
Brandon Potter [Fri, 10 Jul 2015 21:05:23 +0000 (16:05 -0500)]
ruby: remove extra whitespace and correct misspelled words
Andreas Sandberg [Tue, 7 Jul 2015 09:03:14 +0000 (10:03 +0100)]
dev, arm: Add a device model that uses the NoMali model
Add a simple device shim that interfaces with the NoMali model
library. The gem5 side of the interface supports Mali T60x/T62x/T760
GPUs. This device model pretends to be a Mali GPU, but doesn't render
anything and executes in zero time.
Andreas Sandberg [Tue, 7 Jul 2015 09:03:13 +0000 (10:03 +0100)]
ext: Add the NoMali GPU no-simulation library
Add revision
9adf9d6e2d889a483a92136c96eb8a434d360561 of NoMali-model
from https://github.com/ARM-software/nomali-model. This library
implements the register interface of the Mali T6xx/T7xx series GPUs,
but doesn't do any rendering. It can be used to hide the effects of
software rendering.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:05 +0000 (09:51 +0100)]
stats: Update pc-switcheroo stats
The pc-switcheroo test cases has slightly different timing after
decoupling draining from the SimObject hierarchy. This is expected
since objects aren't drained in the exact same order as before.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:05 +0000 (09:51 +0100)]
sim: Refactor and simplify the drain API
The drain() call currently passes around a DrainManager pointer, which
is now completely pointless since there is only ever one global
DrainManager in the system. It also contains vestiges from the time
when SimObjects had to keep track of their child objects that needed
draining.
This changeset moves all of the DrainState handling to the Drainable
base class and changes the drain() and drainResume() calls to reflect
this. Particularly, the drain() call has been updated to take no
parameters (the DrainManager argument isn't needed) and return a
DrainState instead of an unsigned integer (there is no point returning
anything other than 0 or 1 any more). Drainable objects should return
either DrainState::Draining (equivalent to returning 1 in the old
system) if they need more time to drain or DrainState::Drained
(equivalent to returning 0 in the old system) if they are already in a
consistent state. Returning DrainState::Running is considered an
error.
Drain done signalling is now done through the signalDrainDone() method
in the Drainable class instead of using the DrainManager directly. The
new call checks if the state of the object is DrainState::Draining
before notifying the drain manager. This means that it is safe to call
signalDrainDone() without first checking if the simulator has
requested draining. The intention here is to reduce the code needed to
implement draining in simple objects.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:05 +0000 (09:51 +0100)]
sim: Decouple draining from the SimObject hierarchy
Draining is currently done by traversing the SimObject graph and
calling drain()/drainResume() on the SimObjects. This is not ideal
when non-SimObjects (e.g., ports) need draining since this means that
SimObjects owning those objects need to be aware of this.
This changeset moves the responsibility for finding objects that need
draining from SimObjects and the Python-side of the simulator to the
DrainManager. The DrainManager now maintains a set of all objects that
need draining. To reduce the overhead in classes owning non-SimObjects
that need draining, objects inheriting from Drainable now
automatically register with the DrainManager. If such an object is
destroyed, it is automatically unregistered. This means that drain()
and drainResume() should never be called directly on a Drainable
object.
While implementing the new functionality, the DrainManager has now
been made thread safe. In practice, this means that it takes a lock
whenever it manipulates the set of Drainable objects since SimObjects
in different threads may create Drainable objects
dynamically. Similarly, the drain counter is now an atomic_uint, which
ensures that it is manipulated correctly when objects signal that they
are done draining.
A nice side effect of these changes is that it makes the drain state
changes stricter, which the simulation scripts can exploit to avoid
redundant drains.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:04 +0000 (09:51 +0100)]
sim: Move mem(Writeback|Invalidate) to SimObject
The memWriteback() and memInvalidate() calls used to live in the
Serializable interface. In this series of patches, the Serializable
interface will be redesigned to make serialization independent of the
object graph and always work on the entire simulator. This means that
the Serialization interface won't be useful to perform maintenance of
the caches in a sub-graph of the entire SimObject graph. This
changeset moves these memory maintenance methods to the SimObject
interface instead.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:04 +0000 (09:51 +0100)]
sim: Make the drain state a global typed enum
The drain state enum is currently a part of the Drainable
interface. The same state machine will be used by the DrainManager to
identify the global state of the simulator. Make the drain state a
global typed enum to better cater for this usage scenario.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:04 +0000 (09:51 +0100)]
python: Remove redundant drain when changing memory modes
When the Python helper code switches CPU models, it sometimes also
needs to change the memory mode of the simulator. When this happens,
it accidentally tried to drain the simulator despite having done so
already. This changeset removes the redundant drain.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:04 +0000 (09:51 +0100)]
sim: Add macros to serialize objects into a section
Add the SERIALIZE_OBJ / UNSERIALIZE_OBJ macros that serialize an
object into a subsection of the current checkpoint section.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:04 +0000 (09:51 +0100)]
base: Add serialization support to Pixels and FrameBuffer
Serialize pixels as unsigned 32 bit integers by adding the required
to_number() and stream operators. This is used by the FrameBuffer,
which now implements the Serializable interface. Users of frame
buffers are expected to serialize it into its own section by calling
serializeSection().
Andreas Sandberg [Tue, 7 Jul 2015 08:51:04 +0000 (09:51 +0100)]
sim: Fix broken event unserialization
Events expected to be unserialized using an event-specific
unserializeEvent call. This call was never actually used, which meant
the events relying on it never got unserialized (or scheduled after
unserialization).
Instead of relying on a custom call, we now use the normal
serialization code again. In order to schedule the event correctly,
the parrent object is expected to use the
EventQueue::checkpointReschedule() call. This happens automatically
for events that are serialized using the AutoSerialize mechanism.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:03 +0000 (09:51 +0100)]
sim: Refactor the serialization base class
Objects that are can be serialized are supposed to inherit from the
Serializable class. This class is meant to provide a unified API for
such objects. However, so far it has mainly been used by SimObjects
due to some fundamental design limitations. This changeset redesigns
to the serialization interface to make it more generic and hide the
underlying checkpoint storage. Specifically:
* Add a set of APIs to serialize into a subsection of the current
object. Previously, objects that needed this functionality would
use ad-hoc solutions using nameOut() and section name
generation. In the new world, an object that implements the
interface has the methods serializeSection() and
unserializeSection() that serialize into a named /subsection/ of
the current object. Calling serialize() serializes an object into
the current section.
* Move the name() method from Serializable to SimObject as it is no
longer needed for serialization. The fully qualified section name
is generated by the main serialization code on the fly as objects
serialize sub-objects.
* Add a scoped ScopedCheckpointSection helper class. Some objects
need to serialize data structures, that are not deriving from
Serializable, into subsections. Previously, this was done using
nameOut() and manual section name generation. To simplify this,
this changeset introduces a ScopedCheckpointSection() helper
class. When this class is instantiated, it adds a new /subsection/
and subsequent serialization calls during the lifetime of this
helper class happen inside this section (or a subsection in case
of nested sections).
* The serialize() call is now const which prevents accidental state
manipulation during serialization. Objects that rely on modifying
state can use the serializeOld() call instead. The default
implementation simply calls serialize(). Note: The old-style calls
need to be explicitly called using the
serializeOld()/serializeSectionOld() style APIs. These are used by
default when serializing SimObjects.
* Both the input and output checkpoints now use their own named
types. This hides underlying checkpoint implementation from
objects that need checkpointing and makes it easier to change the
underlying checkpoint storage code.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:03 +0000 (09:51 +0100)]
tests: Skip SPARC tests if the required binaries are missing
The full-system SPARC tests depend on several binaries that aren't
generally available to the wider community. Flag the tests as skipped
instead of failed if these binaries can't be found.
Andreas Sandberg [Tue, 7 Jul 2015 08:51:03 +0000 (09:51 +0100)]
sim: Add serialization macros for std containers
Andreas Sandberg [Mon, 6 Jul 2015 16:08:53 +0000 (17:08 +0100)]
mem: Cleanup CommMonitor in preparation for probe support
Make configuration parameters constant and get rid of an unnecessary
dependency on the Time class.
Nilay Vaish [Mon, 6 Jul 2015 01:26:18 +0000 (20:26 -0500)]
stats: x86: update stats missed out on in preivous changeset
Nilay Vaish [Sat, 4 Jul 2015 15:43:47 +0000 (10:43 -0500)]
stats: update stale config.ini files, eio and few other stats.
Nikos Nikoleris [Sat, 4 Jul 2015 15:43:47 +0000 (10:43 -0500)]
x86: Adjust the size of the values written to the x87 misc registers
All x87 misc registers are implemented in an array of 64 bit values
but in real hardware the size of some of these registers is smaller.
Previsouly all 64 bits where incorrectly set and then later read. To
ensure correctness we mask the value in setMiscRegNoEffect to write
only the valid bits.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
David Hashe [Sat, 4 Jul 2015 15:43:47 +0000 (10:43 -0500)]
config: Update location of ruby topologies in help
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Sat, 4 Jul 2015 15:43:46 +0000 (10:43 -0500)]
o3: correct the number of cc registers in rename map
Nilay Vaish [Sat, 4 Jul 2015 15:43:46 +0000 (10:43 -0500)]
mem: packet: Add const to constructor argument
Nilay Vaish [Sat, 4 Jul 2015 15:43:46 +0000 (10:43 -0500)]
ruby: drop NetworkMessage class
This patch drops the NetworkMessage class. The relevant data members and functions
have been moved to the Message class, which was the parent of NetworkMessage.
Nilay Vaish [Sat, 4 Jul 2015 15:43:46 +0000 (10:43 -0500)]
ruby: mesi three level: name change to avoid clash
The accessor function getDestination() for Destination variable in the
coherence message clashes with the getDestination() that is part of the Message
class. Hence the name change.
Nilay Vaish [Sat, 4 Jul 2015 15:43:46 +0000 (10:43 -0500)]
ruby: remove message buffer node
This structure's only purpose was to provide a comparison function for
ordering messages in the MessageBuffer. The comparison function is now
being moved to the Message class itself. So we no longer require this
structure.
Andreas Hansson [Fri, 3 Jul 2015 14:15:03 +0000 (10:15 -0400)]
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Andreas Hansson [Fri, 3 Jul 2015 14:14:48 +0000 (10:14 -0400)]
mem: Increase the default buffer sizes for the DDR4 controller
This patch increases the default read/write buffer sizes for the DDR4
controller config to values that are more suitable for the high
bandwidth and high bank count.
Wendy Elsasser [Fri, 3 Jul 2015 14:14:46 +0000 (10:14 -0400)]
mem: Update DRAM command scheduler for bank groups
This patch updates the command arbitration so that bank group timing
as well as rank-to-rank delays will be taken into account. The
resulting arbitration no longer selects commands (prepped or not) that
cannot issue seamlessly if there are commands that can issue
back-to-back, minimizing the effect of rank-to-rank (tCS) & same bank
group (tCCD_L) delays.
The arbitration selects a new command based on the following priority.
Within each priority band, the arbitration will use FCFS to select the
appropriate command:
1) Bank is prepped and burst can issue seamlessly, without a bubble
2) Bank is not prepped, but can prep and issue seamlessly, without a
bubble
3) Bank is prepped but burst cannot issue seamlessly. In this case, a
bubble will occur on the bus
Thus, to enable more parallelism in subsequent selections, an
unprepped packet is given higher priority if the bank prep can be
hidden. If the bank prep cannot be hidden, the selection logic will
choose a prepped packet that cannot issue seamlessly if one exist.
Otherwise, the default selection will choose the packet with the
minimum bank prep delay.
Andreas Hansson [Fri, 3 Jul 2015 14:14:45 +0000 (10:14 -0400)]
mem: Avoid DRAM write queue iteration for merging and read lookup
This patch adds a simple lookup structure to avoid iterating over the
write queue to find read matches, and for the merging of write
bursts. Instead of relying on iteration we simply store a set of
currently-buffered write-burst addresses and compare against
these. For the reads we still perform the iteration if we have a
match. For the writes, we rely entirely on the set. Note that there
are corner-cases where sub-bursts would actually not be mergeable
without a read-modify-write. We ignore these cases and opt for speed.
Andreas Hansson [Fri, 3 Jul 2015 14:14:44 +0000 (10:14 -0400)]
mem: Delay responses in the crossbar before forwarding
This patch changes how the crossbar classes deal with
responses. Instead of forwarding responses directly and burdening the
neighbouring modules in paying for the latency (through the
pkt->headerDelay), we now queue them before sending them.
The coherency protocol is not affected as requests and any snoop
requests/responses are still passed on in zero time. Thus, the
responses end up paying for any header delay accumulated when passing
through the crossbar. Any latency incurred on the request path will be
paid for on the response side, if no other module has dealt with it.
As a result of this patch, responses are returned at a later
point. This affects the number of outstanding transactions, and quite
a few regressions see an impact in blocking due to no MSHRs, increased
cache-miss latencies, etc.
Going forward we should be able to use the same concept also for snoop
responses, and any request that is not an express snoop.
Andreas Hansson [Fri, 3 Jul 2015 14:14:43 +0000 (10:14 -0400)]
mem: Remove redundant is_top_level cache parameter
This patch takes the final step in removing the is_top_level parameter
from the cache. With the recent changes to read requests and write
invalidations, the parameter is no longer needed, and consequently
removed.
This also means that asymmetric cache hierarchies are now fully
supported (and we are actually using them already with L1 caches, but
no table-walker caches, connected to a shared L2).
Andreas Hansson [Fri, 3 Jul 2015 14:14:41 +0000 (10:14 -0400)]
mem: Split WriteInvalidateReq into write and invalidate
WriteInvalidateReq ensures that a whole-line write does not incur the
cost of first doing a read exclusive, only to later overwrite the
data. This patch splits the existing WriteInvalidateReq into a
WriteLineReq, which is done locally, and an InvalidateReq that is sent
out throughout the memory system. The WriteLineReq re-uses the normal
WriteResp.
The change allows us to better express the difference between the
cache that is performing the write, and the ones that are merely
invalidating. As a consequence, we no longer have to rely on the
isTopLevel flag. Moreover, the actual memory in the system does not
see the intitial write, only the writeback. We were marking the
written line as dirty already, so there is really no need to also push
the write all the way to the memory.
The overall flow of the write-invalidate operation remains the same,
i.e. the operation is only carried out once the response for the
invalidate comes back. This patch adds the InvalidateResp for this
very reason.
Andreas Hansson [Fri, 3 Jul 2015 14:14:40 +0000 (10:14 -0400)]
mem: Add ReadCleanReq and ReadSharedReq packets
This patch adds two new read requests packets:
ReadCleanReq - For a cache to explicitly request clean data. The
response is thus exclusive or shared, but not owned or modified. The
read-only caches (see previous patch) use this request type to ensure
they do not get dirty data.
ReadSharedReq - We add this to distinguish cache read requests from
those issued by other masters, such as devices and CPUs. Thus, devices
use ReadReq, and caches use ReadCleanReq, ReadExReq, or
ReadSharedReq. For the latter, the response can be any state, shared,
exclusive, owned or even modified.
Both ReadCleanReq and ReadSharedReq re-use the normal ReadResp. The
two transactions are aligned with the emerging cache-coherent TLM
standard and the AMBA nomenclature.
With this change, the normal ReadReq should never be used by a cache,
and is reserved for the actual (non-caching) masters in the system. We
thus have a way of identifying if a request came from a cache or
not. The introduction of ReadSharedReq thus removes the need for the
current isTopLevel hack, and also allows us to stop relying on
checking the packet size to determine if the source is a cache or
not. This is fixed in follow-on patches.
Andreas Hansson [Fri, 3 Jul 2015 14:14:39 +0000 (10:14 -0400)]
mem: Allow read-only caches and check compliance
This patch adds a parameter to the BaseCache to enable a read-only
cache, for example for the instruction cache, or table-walker cache
(not for x86). A number of checks are put in place in the code to
ensure a read-only cache does not end up with dirty data.
A follow-on patch adds suitable read requests to allow a read-only
cache to explicitly ask for clean data.
Ali Jafri [Fri, 3 Jul 2015 14:14:37 +0000 (10:14 -0400)]
mem: Add clean evicts to improve snoop filter tracking
This patch adds eviction notices to the caches, to provide accurate
tracking of cache blocks in snoop filters. We add the CleanEvict
message to the memory heirarchy and use both CleanEvicts and
Writebacks with BLOCK_CACHED flags to propagate notice of clean and
dirty evictions respectively, down the memory hierarchy. Note that the
BLOCK_CACHED flag indicates whether there exist any copies of the
evicted block in the caches above the evicting cache.
The purpose of the CleanEvict message is to notify snoop filters of
silent evictions in the relevant caches. The CleanEvict message
behaves much like a Writeback. CleanEvict is a write and a request but
unlike a Writeback, CleanEvict does not have data and does not need
exclusive access to the block. The cache generates the CleanEvict
message on a fill resulting in eviction of a clean block. Before
travelling downwards CleanEvict requests generate zero-time snoop
requests to check if the same block is cached in upper levels of the
memory heirarchy. If the block exists, the cache discards the
CleanEvict message. The snoops check the tags, writeback queue and the
MSHRs of upper level caches in a manner similar to snoops generated
from HardPFReqs. Currently CleanEvicts keep travelling towards main
memory unless they encounter the block corresponding to their address
or reach main memory (since we have no well defined point of
serialisation). Main memory simply discards CleanEvict messages.
We have modified the behavior of Writebacks, such that they generate
snoops to check for the presence of blocks in upper level caches. It
is possible in our current implmentation for a lower level cache to be
writing back a block while a shared copy of the same block exists in
the upper level cache. If the snoops find the same block in upper
level caches, we set the BLOCK_CACHED flag in the Writeback message.
We have also added logic to account for interaction of other message
types with CleanEvicts waiting in the writeback queue. A simple
example is of a response arriving at a cache removing any CleanEvicts
to the same address from the cache's writeback queue.
Andreas Hansson [Fri, 3 Jul 2015 14:14:36 +0000 (10:14 -0400)]
mem: Convert Request static const flags to enums
This patch fixes an issue which is very wide spread in the codebase,
causing sporadic linking failures. The issue is that we declare static
const class variables in the header, without any definition (as part
of a source file). In most cases the compiler propagates the value and
we have no issues. However, especially for less optimising builds such
as debug, we get sporadic linking failures due to undefined
references.
This patch fixes the Request class, by turning the static const flags
and master IDs into C++11 typed enums.
Curtis Dunham [Fri, 3 Jul 2015 14:14:35 +0000 (10:14 -0400)]
scons: remove dead leading underscore check
e56c3d8 (2008) added it but
8e37348 (2010) removed its only use.
Curtis Dunham [Fri, 3 Jul 2015 14:14:34 +0000 (10:14 -0400)]
base: remove fd from object loaders
All the object loaders directly examine the (already completely loaded
by object_file.cc) memory image. There is no current motivation to
keep the fd around.
Andreas Hansson [Fri, 3 Jul 2015 14:14:24 +0000 (10:14 -0400)]
util: Remove DRAMPower trace script
This script is deprecated and DRAMPower is now properly integrated
with the controller model.
Andreas Hansson [Fri, 3 Jul 2015 14:14:15 +0000 (10:14 -0400)]
scons: Bump compiler requirement to gcc >= 4.7 and clang >= 3.1
This patch updates the compiler minimum requirement to gcc 4.7 and
clang 3.1, thus allowing:
1. Explicit virtual overrides (no need for M5_ATTR_OVERRIDE)
2. Non-static data member initializers
3. Template aliases
4. Delegating constructors
This patch also enables a transition from --std=c++0x to --std=c++11.
Nilay Vaish [Thu, 25 Jun 2015 16:58:30 +0000 (11:58 -0500)]
ruby: slicc: remove README
No longer maintained. Updates are only made to the wiki page. So being
dropped.
Nilay Vaish [Thu, 25 Jun 2015 16:58:29 +0000 (11:58 -0500)]
ruby: message: remove a data member added by mistake
I (Nilay) had mistakenly added a data member to the Message class in revision
c1694b4032a6.
The data member is being removed.
Jason Power [Thu, 25 Jun 2015 16:58:28 +0000 (11:58 -0500)]
Ruby: Remove assert in RubyPort retry list logic
Remove the assert when adding a port to the RubyPort retry list.
Instead of asserting, just ignore the added port, since it's
already on the list.
Without this patch, Ruby+detailed fails for even the simplest tests
Andreas Sandberg [Sun, 21 Jun 2015 19:52:13 +0000 (20:52 +0100)]
base: Add a warn_if macro
Add a warn if macro that is analogous to the panic_if and fatal_if.
Andreas Sandberg [Sun, 21 Jun 2015 19:48:33 +0000 (20:48 +0100)]
arm: Cleanup arch headers to remove dma_device.hh dependency
Break the dependency on dma_device.hh by forward-declaring DmaPort in
the relevant header.
Ali Jafri [Tue, 9 Jun 2015 13:21:18 +0000 (09:21 -0400)]
mem: Add check for express snoop in packet destructor
Snoop packets share the request pointer with the originating
packets. We need to ensure that the snoop packet destruction does not
delete the request. Snoops are used for reads, invalidations,
HardPFReqs, Writebacks and CleansEvicts. Reads, invalidations, and
HardPFReqs need a response so their snoops do not delete the
request. For Writebacks and CleanEvicts we need to check explicitly
for whethere the current packet is an express snoop, in whcih case do
not delete the request.
Andreas Hansson [Tue, 9 Jun 2015 13:21:17 +0000 (09:21 -0400)]
mem: Fix snoop packet data allocation bug
This patch fixes an issue where the snoop packet did not properly
forward the data pointer in case of static data.
Rune Holm [Tue, 9 Jun 2015 13:21:16 +0000 (09:21 -0400)]
arm: Delete debug print in initialization of hardware thread
There seems to have been a debug print left in when the original ARMv8
support was merged in. This printout is performed every time you
initialize a hardware thread, and it prints raw pointers, so it always
causes diffs in the regression. This patch removes the debug print.
Rune Holm [Tue, 9 Jun 2015 13:21:15 +0000 (09:21 -0400)]
arm: Fix typo in ldrsh instruction name
ldrsh was typoed as hdrsh, which is a bit annoying when printing
instructions. This patch fixes it.
Andreas Sandberg [Tue, 9 Jun 2015 13:21:14 +0000 (09:21 -0400)]
base: Reset CircleBuf size on flush()
The flush() method in CircleBuf resets the state of the circular
buffer, but fails to set size to zero. This obviously confuses code
that tries to determine the amount of data in the buffer. Set the size
to zero on flush.
Andreas Sandberg [Tue, 9 Jun 2015 13:21:12 +0000 (09:21 -0400)]
dev, arm: Include PIO size in AmbaDmaDevice constructor
Make it possible to specify the size of the PIO space for an AMBA DMA
device. Maintain backwards compatibility and default to zero.
Andreas Hansson [Tue, 9 Jun 2015 13:21:11 +0000 (09:21 -0400)]
scons: Allow GNU assembler version strings with hyphen
Make scons a bit more forgiving when determining the GNU assembler version.
Marco Elver [Sun, 7 Jun 2015 19:02:40 +0000 (14:02 -0500)]
ruby: Fix MESI consistency bug
Fixes missed forward eviction to CPU. With the O3CPU this can lead to load-load
reordering, as the LQ is never notified of the invalidate.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Matthias Jung [Sun, 7 Jun 2015 19:02:40 +0000 (14:02 -0500)]
mem: Add HMC Timing Parameters
A single HMC-2500 x32 model based on:
[1] DRAMSpec: a high-level DRAM bank modelling tool developed at the University
of Kaiserslautern. This high level tool uses RC (resistance-capacitance) and CV
(capacitance-voltage) models to estimate the DRAM bank latency and power
numbers.
[2] A Logic-base Interconnect for Supporting Near Memory Computation in the
Hybrid Memory Cube (E. Azarkhish et. al) Assumed for the HMC model is a 30 nm
technology node. The modelled HMC consists of a 4 Gbit part with 4 layers
connected with TSVs. Each layer has 16 vaults and each vault consists of 2
banks per layer. In order to be able to use the same controller used for 2D
DRAM generations for HMC, the following analogy is done: Channel (DDR) => Vault
(HMC) device_size (DDR) => size of a single layer in a vault ranks per channel
(DDR) => number of layers banks per rank (DDR) => banks per layer devices per
rank (DDR) => devices per layer ( 1 for HMC). The parameters for which no
input is available are inherited from the DDR3 configuration.
Ruslan Bukin ext:(%2C%20Zhang%20Guoye) [Sun, 7 Jun 2015 19:02:40 +0000 (14:02 -0500)]
arch: fix build under MacOSX
put O_DIRECT under ifdefs -- this fixes build for MacOSX.
Also use correct class for arm64 openFlagTable.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Christoph Pfister [Sat, 30 May 2015 11:45:17 +0000 (13:45 +0200)]
mem: addr_mapper: restore old address if request not sent
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Curtis Dunham [Mon, 1 Jun 2015 23:05:11 +0000 (18:05 -0500)]
sim, arm: add checkpoint upgrader for
d02b45a5
The insertion of CONTEXTIDR_EL2 in the ARM miscellaneous registers
obsoletes old checkpoints.
Andreas Sandberg [Mon, 1 Jun 2015 18:44:19 +0000 (19:44 +0100)]
kvm, arm: Add support for aarch64
This changeset adds support for aarch64 in kvm. The CPU module
supports both checkpointing and online CPU model switching as long as
no devices are simulated by the host kernel. It currently has the
following limitations:
* The system register based generic timer can only be simulated by
the host kernel. Workaround: Use a memory mapped timer instead to
simulate the timer in gem5.
* Simulating devices (e.g., the generic timer) in the host kernel
requires that the host kernel also simulates the GIC.
* ID registers in the host and in gem5 must match for switching
between simulated CPUs and KVM. This is particularly important
for ID registers describing memory system capabilities (e.g.,
ASID size, physical address size).
* Switching between a virtualized CPU and a simulated CPU is
currently not supported if in-kernel device emulation is
used. This could be worked around by adding support for switching
to the gem5 (e.g., the KvmGic) side of the device models. A
simpler workaround is to avoid in-kernel device models
altogether.
Andreas Sandberg [Mon, 1 Jun 2015 18:44:17 +0000 (19:44 +0100)]
kvm, arm, dev: Add an in-kernel GIC implementation
This changeset adds a GIC implementation that uses the kernel's
built-in support for simulating the interrupt controller. Since there
is currently no support for state transfer between gem5 and the
kernel, the device model does not support serialization and CPU
switching (which would require switching to a gem5-simulated GIC).
Andreas Sandberg [Mon, 1 Jun 2015 18:43:41 +0000 (19:43 +0100)]
kvm: Handle inst events at the current instruction count
There are cases (particularly when attaching GDB) when instruction
events are scheduled at the current instruction tick. This used to
trigger an assertion error in kvm. This changeset adds a check for
this condition and forces KVM to do a quick entry that completes any
pending IO operations, but does not execute any new instructions,
before servicing the event. We could check if we need to enter KVM at
all, but forcing a quick entry is makes the code slightly cleaner and
does not hurt correctness (performance is hardly an issue in these
cases).
Andreas Sandberg [Mon, 1 Jun 2015 18:43:40 +0000 (19:43 +0100)]
kvm, arm: Move ARM-specific files to arch/arm/kvm/
This changeset moves the ARM-specific KVM CPU implementation to
arch/arm/kvm/. This change is expected to keep the source tree
somewhat cleaner as we start adding support for ARMv8 and KVM
in-kernel interrupt controller simulation.
--HG--
rename : src/cpu/kvm/ArmKvmCPU.py => src/arch/arm/kvm/ArmKvmCPU.py
rename : src/cpu/kvm/arm_cpu.cc => src/arch/arm/kvm/arm_cpu.cc
rename : src/cpu/kvm/arm_cpu.hh => src/arch/arm/kvm/arm_cpu.hh
Curtis Dunham [Tue, 26 May 2015 07:21:45 +0000 (03:21 -0400)]
arm: implement the CONTEXTIDR_EL2 system reg.
Andreas Hansson [Tue, 26 May 2015 07:21:44 +0000 (03:21 -0400)]
arm, stats: Update stats to reflect reduction in misc reg reads
Nathanael Premillieu [Tue, 26 May 2015 07:21:42 +0000 (03:21 -0400)]
arm: Make address translation faster with better caching
This patch adds better caching of the sys regs for AArch64, thus
avoiding unnecessary calls to tc->readMiscReg(MISCREG_CPSR) in the
non-faulting case.
Andreas Hansson [Tue, 26 May 2015 07:21:40 +0000 (03:21 -0400)]
base: Allow multiple interleaved ranges
This patch changes how the address range calculates intersection such
that a system can have a number of non-overlapping interleaved ranges
without complaining. Without this patch we end up with a panic.
Andreas Hansson [Tue, 26 May 2015 07:21:39 +0000 (03:21 -0400)]
stats: Update MinorCPU regressions after accounting fix
Andrew Bardsley [Tue, 26 May 2015 07:21:37 +0000 (03:21 -0400)]
cpu: Fix a bug in counting issued instructions in MinorCPU
The MinorCPU would count bubbles in Execute::issue as part of
the num_insts_issued and so sometimes reach the instruction
issue limit incorrectly.
Fixed by checking for a bubble in one new place.
Giacomo Gabrielli [Tue, 26 May 2015 07:21:35 +0000 (03:21 -0400)]
arm: Implement some missing syscalls (SE mode)
Adding a few syscalls that were previously considered unimplemented.
Andreas Hansson [Tue, 26 May 2015 07:21:34 +0000 (03:21 -0400)]
ruby: Deprecation warning for RubyMemoryControl
A step towards removing RubyMemoryControl and shift users to
DRAMCtrl. The latter is faster, more representative, very versatile,
and is integrated with power models.
Andreas Sandberg [Sat, 23 May 2015 12:50:57 +0000 (13:50 +0100)]
arm, stats: Update stats to reflect changes to generic timer
The addition of a virtual timer affects stats in minor and o3.
Andreas Sandberg [Sat, 23 May 2015 12:46:56 +0000 (13:46 +0100)]
arm, dev: Add support for a memory mapped generic timer
There are cases when we don't want to use a system register mapped
generic timer, but can't use the SP804. For example, when using KVM on
aarch64, we want to intercept accesses to the generic timer, but can't
do so if it is using the system register interface. In such cases,
we need to use a memory-mapped generic timer.
This changeset adds a device model that implements the memory mapped
generic timer interface. The current implementation only supports a
single frame (i.e., one virtual timer and one physical timer).
Andreas Sandberg [Sat, 23 May 2015 12:46:54 +0000 (13:46 +0100)]
arm: Get rid of pointless have_generic_timer param
The ArmSystem class has a parameter to indicate whether it is
configured to use the generic timer extension or not. This parameter
doesn't affect any feature flags in the current implementation and is
therefore completely unnecessary. In fact, we usually don't set it
even if a system has a generic timer. If we ever need to check if
there is a generic timer present, we should just request a pointer and
check if it is non-null instead.
Andreas Sandberg [Sat, 23 May 2015 12:46:53 +0000 (13:46 +0100)]
dev, arm: Add virtual timers to the generic timer model
The generic timer model currently does not support virtual
counters. Virtual and physical counters both tick with the same
frequency. However, virtual timers allow a hypervisor to set an offset
that is subtracted from the counter when it is read. This enables the
hypervisor to present a time base that ticks with virtual time in the
VM (i.e., doesn't tick when the VM isn't running). Modern Linux
kernels generally assume that virtual counters exist and try to use
them by default.
Andreas Sandberg [Sat, 23 May 2015 12:46:52 +0000 (13:46 +0100)]
dev, arm: Refactor and clean up the generic timer model
This changeset cleans up the generic timer a bit and moves most of the
register juggling from the ISA code into a separate class in the same
source file as the rest of the generic timer. It also removes the
assumption that there is always 8 or fewer CPUs in the system. Instead
of having a fixed limit, we now instantiate per-core timers as they
are requested. This is all in preparation for other patches that add
support for virtual timers and a memory mapped interface.
Andreas Sandberg [Sat, 23 May 2015 12:37:22 +0000 (13:37 +0100)]
kvm: Fix dumping code for large registers
The register dumping code in kvm tries to print the bytes in large
registers (128 bits and larger) instead of printing them as hex. This
changeset fixes that.
Andreas Sandberg [Sat, 23 May 2015 12:37:20 +0000 (13:37 +0100)]
kvm, x86: Guard x86-specific APIs in KvmVM
Protect x86-specific APIs in KvmVM with compile-time guards to avoid
breaking ARM builds.
Andreas Sandberg [Sat, 23 May 2015 12:37:18 +0000 (13:37 +0100)]
build: Don't test for KVM xsave support on ARM
The current build tests for KVM unconditionally check for xsave
support. This obviously never works on ARM since xsave is
x86-specific. This changeset refactors the build tests probing for KVM
support and moves the xsave test to an x86-specific section of
is_isa_kvm_compatible().
Andreas Sandberg [Sat, 23 May 2015 12:37:04 +0000 (13:37 +0100)]
arm: Workaround incorrect HDLCD register order in kernel
Some versions of the kernel incorrectly swap the red and blue color
select registers. This changeset adds a workaround for that by
swapping them when instantiating a PixelConverter.
Andreas Sandberg [Sat, 23 May 2015 12:37:03 +0000 (13:37 +0100)]
base: Redesign internal frame buffer handling
Currently, frame buffer handling in gem5 is quite ad hoc. In practice,
we pass around naked pointers to raw pixel data and expect consumers
to convert frame buffers using the (broken) VideoConverter.
This changeset completely redesigns the way we handle frame buffers
internally. In summary, it fixes several color conversion bugs, adds
support for more color formats (e.g., big endian), and makes the code
base easier to follow.
In the new world, gem5 always represents pixel data using the Pixel
struct when pixels need to be passed between different classes (e.g.,
a display controller and the VNC server). Producers of entire frames
(e.g., display controllers) should use the FrameBuffer class to
represent a frame.
Frame producers are expected to create one instance of the FrameBuffer
class in their constructors and register it with its consumers
once. Consumers are expected to check the dimensions of the frame
buffer when they consume it.
Conversion between the external representation and the internal
representation is supported for all common "true color" RGB formats of
up to 32-bit color depth. The external pixel representation is
expected to be between 1 and 4 bytes in either big endian or little
endian. Color channels are assumed to be contiguous ranges of bits
within each pixel word. The external pixel value is scaled to an 8-bit
internal representation using a floating multiplication to map it to
the entire 8-bit range.
Andreas Sandberg [Sat, 23 May 2015 12:37:01 +0000 (13:37 +0100)]
base: Clean up bitmap generation code
The bitmap generation code is hard to follow and incorrectly uses the
size of an enum member to calculate the size of a pixel. This
changeset cleans up the code and adds some documentation.
Joel Hestness [Tue, 19 May 2015 15:56:51 +0000 (10:56 -0500)]
ruby: Fix RubySystem warm-up and cool-down scope
The processes of warming up and cooling down Ruby caches are simulation-wide
processes, not just RubySystem instance-specific processes. Thus, the warm-up
and cool-down variables should be globally visible to any Ruby components
participating in either process. Make these variables static members and track
the warm-up and cool-down processes as appropriate.
This patch also has two side benefits:
1) It removes references to the RubySystem g_system_ptr, which are problematic
for allowing multiple RubySystem instances in a single simulation. Warmup and
cooldown variables being static (global) reduces the need for instance-specific
dereferences through the RubySystem.
2) From the AbstractController, it removes local RubySystem pointers, which are
used inconsistently with other uses of the RubySystem: 11 other uses reference
the RubySystem with the g_system_ptr. Only sequencers have local pointers.
Andreas Hansson [Fri, 15 May 2015 17:40:01 +0000 (13:40 -0400)]
arm: Identify table-walker requests
This patch ensures all page-table walks are flagged as such.
Andreas Hansson [Fri, 15 May 2015 17:39:53 +0000 (13:39 -0400)]
misc: Appease gcc 5.1
Three minor issues are resolved:
1. Apparently gcc 5.1 does not like negation of booleans followed by
bitwise AND.
2. Somehow the compiler also gets confused and warns about
NoopMachInst being unused (removing it causes compilation errors
though). Most likely a compiler bug.
3. There seems to be a number of instances where loop unrolling causes
false positives for the array-bounds check. For now, switch to
std::array. Potentially we could disable the warning for newer gcc
versions, but switching to std::array is probably a good move in
any case.
Andreas Sandberg [Fri, 15 May 2015 17:39:44 +0000 (13:39 -0400)]
sim: Don't clear the active CPU vector in System::initState
The system class currently clears the vector of active CPUs in
initState(). CPUs are added to the list by registerThreadContext()
which is called from BaseCPU::init(). This obviously breaks when the
System object is initialized after the CPUs. This changeset removes
the offending clear() call since the list will be empty after it has
been instantiated anyway.
Andreas Hansson [Fri, 15 May 2015 17:38:46 +0000 (13:38 -0400)]
config: Use null memory for DRAM sweep script
Do not waste time when we do not care about the data.
Wendy Elsasser [Fri, 15 May 2015 17:38:45 +0000 (13:38 -0400)]
config: Add new MemConfig options to DRAM sweep script
Update script to match current MemConfig options with
external_memory_system option set to 0.
Steve Reinhardt [Tue, 5 May 2015 16:25:59 +0000 (09:25 -0700)]
syscall_emul: fix warn_once behavior
The current ignoreWarnOnceFunc doesn't really work as expected,
since it will only generate one warning total, for whichever
"warn-once" syscall is invoked first. This patch fixes that
behavior by keeping a "warned" flag in the SyscallDesc object,
allowing suitably flagged syscalls to warn exactly once per
syscall.
Andreas Hansson [Tue, 5 May 2015 07:22:48 +0000 (03:22 -0400)]
stats, arm: Update stats for missing FPEXC.EN check
Only one regression is affected.