Luke Kenneth Casson Leighton [Fri, 28 Jun 2019 10:05:28 +0000 (11:05 +0100)]
fix fprintfs
Luke Kenneth Casson Leighton [Fri, 28 Jun 2019 10:05:19 +0000 (11:05 +0100)]
remove src suboffset
Luke Kenneth Casson Leighton [Fri, 28 Jun 2019 09:58:41 +0000 (10:58 +0100)]
remove set CSR_SV_STATE for now
Luke Kenneth Casson Leighton [Fri, 28 Jun 2019 09:58:30 +0000 (10:58 +0100)]
mess with CSR_SV_STATE set
Luke Kenneth Casson Leighton [Fri, 28 Jun 2019 09:48:13 +0000 (10:48 +0100)]
printf wrong args
Luke Kenneth Casson Leighton [Fri, 28 Jun 2019 09:47:48 +0000 (10:47 +0100)]
printf wrong args
Luke Kenneth Casson Leighton [Fri, 28 Jun 2019 09:40:59 +0000 (10:40 +0100)]
vl, mvl, subvl should all be 1 when returned from CSR_SV_STATE
Luke Kenneth Casson Leighton [Fri, 28 Jun 2019 09:23:05 +0000 (10:23 +0100)]
sub-loop independent (only one offset)
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 20:57:47 +0000 (21:57 +0100)]
restore svstate on exit from trap (mret, sret)
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 14:46:56 +0000 (15:46 +0100)]
add sesvstate / mesvstate, set on entry to trap
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 14:26:23 +0000 (15:26 +0100)]
rename SV CSRs, to use CSR_UESVSTATE etc.
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 12:53:05 +0000 (13:53 +0100)]
make vlen loop run times subvl, set subvl default to 1 not 0
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 12:52:30 +0000 (13:52 +0100)]
disable subvl-mult on predication remap
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 10:58:04 +0000 (11:58 +0100)]
start using subvl to calculate offset. predication and stack pointer needed
sub-offsets, one fake (predication does not use subvl), one real
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 09:23:00 +0000 (10:23 +0100)]
pass sub-offset down through remap in sv_insn_t into reg_spec_t
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 09:01:02 +0000 (10:01 +0100)]
add the subvl offset to sv_insn_t
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 08:46:53 +0000 (09:46 +0100)]
rename sub offsets
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 08:33:46 +0000 (09:33 +0100)]
add comments
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 08:31:07 +0000 (09:31 +0100)]
add in use of inc_offs and sub-src/dest offsets
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 07:48:57 +0000 (08:48 +0100)]
initialise SUBVL to 1
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 07:42:44 +0000 (08:42 +0100)]
add inc_offs function to be used for vl/subvl loops
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 07:10:49 +0000 (08:10 +0100)]
add comment on SUBVL in setpc
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 06:36:56 +0000 (07:36 +0100)]
add get on subvl
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 06:36:00 +0000 (07:36 +0100)]
alter STATE CSR to support subvl
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 06:34:11 +0000 (07:34 +0100)]
add SUBVL CSR set
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 06:30:49 +0000 (07:30 +0100)]
add SUBVL CSR set
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 06:24:15 +0000 (07:24 +0100)]
add subvl to headers, comment out state-cfg
Luke Kenneth Casson Leighton [Thu, 27 Jun 2019 06:13:06 +0000 (07:13 +0100)]
rename packed field to fail-on-first
Luke Kenneth Casson Leighton [Thu, 29 Nov 2018 09:25:08 +0000 (09:25 +0000)]
start to update predicated Branch to latest spec
Luke Kenneth Casson Leighton [Thu, 29 Nov 2018 07:10:10 +0000 (07:10 +0000)]
on branch, obtain the predicate inversion flag
Luke Kenneth Casson Leighton [Thu, 29 Nov 2018 07:08:57 +0000 (07:08 +0000)]
get the predicate inv argument as well
Luke Kenneth Casson Leighton [Sat, 17 Nov 2018 06:58:14 +0000 (06:58 +0000)]
c_lwsp fix-up to use src_pred, and pass width not xlen into READ_REG bitwidth
Luke Kenneth Casson Leighton [Sat, 17 Nov 2018 05:35:37 +0000 (05:35 +0000)]
add element-offset mode on LD/ST when isvec=false on address
Luke Kenneth Casson Leighton [Sat, 17 Nov 2018 04:40:13 +0000 (04:40 +0000)]
predication remapping added
Luke Kenneth Casson Leighton [Thu, 15 Nov 2018 23:45:31 +0000 (23:45 +0000)]
add in predication remapping into src, dest and branch target
Luke Kenneth Casson Leighton [Thu, 15 Nov 2018 23:23:13 +0000 (23:23 +0000)]
add predication remap option
Luke Kenneth Casson Leighton [Wed, 14 Nov 2018 21:55:40 +0000 (21:55 +0000)]
comment out debug code not needed
Luke Kenneth Casson Leighton [Tue, 13 Nov 2018 23:17:24 +0000 (23:17 +0000)]
change SV_REGCSR csrrwi to different meaning: 5-bit is num CSR entries to pop
however, it has to be limited to what will fit into the return result.
so stops at 4 non-zero entries on RV64 and 2 on RV32.
perhaps use notification of use of x0 to remove all items requested?
can do a complate stack-wipe with one csrrwi instruction, then
Luke Kenneth Casson Leighton [Tue, 13 Nov 2018 16:02:05 +0000 (16:02 +0000)]
pass in arg to set_csr from csrrwi to indicate "immediate enabled"
Luke Kenneth Casson Leighton [Tue, 13 Nov 2018 15:57:59 +0000 (15:57 +0000)]
modify csrrwi and csrrw back to original, change old val inside set_csr
Luke Kenneth Casson Leighton [Tue, 13 Nov 2018 15:53:27 +0000 (15:53 +0000)]
csrrwi cut out extraneous get_csr
Luke Kenneth Casson Leighton [Tue, 13 Nov 2018 15:52:26 +0000 (15:52 +0000)]
whoops missing brackets
Luke Kenneth Casson Leighton [Tue, 13 Nov 2018 13:52:48 +0000 (13:52 +0000)]
alter set_csr to call get_csr, will make csrrw* easier
Luke Kenneth Casson Leighton [Tue, 13 Nov 2018 13:38:33 +0000 (13:38 +0000)]
redo SV CSRs to use a stack-based mechanism
Luke Kenneth Casson Leighton [Sun, 11 Nov 2018 20:20:11 +0000 (20:20 +0000)]
c_lwsp and c_swsp were not working correctly
needed to be in ADDRmode (dropping down to mmu_t::load_xxx not sv_mmu_t)
and also needed to stop using reg_spec.offset. added an extra
argument to rvc_sp() which is "use_offset=true/false".
switching to use_offset=false for c_lwsp and c_swsp, and getting them
to both NOT be in the normal ADDRmode for LD/ST, we get an
increment on the registers from SP.
really should redirect the CSRs to not use SP, x28-x30 instead or
something, in the unit tests...
Luke Kenneth Casson Leighton [Sat, 10 Nov 2018 20:32:15 +0000 (20:32 +0000)]
macro-ify rv_sr and rv_sl
Luke Kenneth Casson Leighton [Sat, 10 Nov 2018 20:24:59 +0000 (20:24 +0000)]
remove extra rv_sl and rv_sr overload fns
Luke Kenneth Casson Leighton [Sat, 10 Nov 2018 20:21:36 +0000 (20:21 +0000)]
whitespace
Luke Kenneth Casson Leighton [Sat, 10 Nov 2018 20:08:29 +0000 (20:08 +0000)]
macro-ify 64-bit mulh fns
Luke Kenneth Casson Leighton [Sat, 10 Nov 2018 06:59:17 +0000 (06:59 +0000)]
slightly different 64-bit rv_mulhu elwidth rules
Luke Kenneth Casson Leighton [Sat, 10 Nov 2018 06:27:52 +0000 (06:27 +0000)]
realised that the bitwidth sign-extension needs to be FROM the
source bitwidth not TO the TARGET bitwidth
Luke Kenneth Casson Leighton [Fri, 9 Nov 2018 12:09:56 +0000 (12:09 +0000)]
macro-ify 32-bit mulh group
Luke Kenneth Casson Leighton [Fri, 9 Nov 2018 12:03:42 +0000 (12:03 +0000)]
mulh 32-bit elwidth
Luke Kenneth Casson Leighton [Fri, 9 Nov 2018 10:25:27 +0000 (10:25 +0000)]
macroify rv_and, rv_or, rv_xor
Luke Kenneth Casson Leighton [Fri, 9 Nov 2018 10:21:43 +0000 (10:21 +0000)]
got fed up with repeated code on s/u-ops, use macros
Luke Kenneth Casson Leighton [Fri, 9 Nov 2018 10:11:34 +0000 (10:11 +0000)]
macro-ify gt, ge, eq and ne
Luke Kenneth Casson Leighton [Fri, 9 Nov 2018 10:10:24 +0000 (10:10 +0000)]
bge and blt are signed ops
Luke Kenneth Casson Leighton [Fri, 9 Nov 2018 10:06:15 +0000 (10:06 +0000)]
got fed up with repeated code, using macros
Luke Kenneth Casson Leighton [Fri, 9 Nov 2018 09:54:23 +0000 (09:54 +0000)]
elwidth version of lt
Luke Kenneth Casson Leighton [Fri, 9 Nov 2018 09:53:43 +0000 (09:53 +0000)]
elwidth version of lt
Luke Kenneth Casson Leighton [Fri, 9 Nov 2018 04:35:19 +0000 (04:35 +0000)]
add mulhsu elwidth variant
Luke Kenneth Casson Leighton [Thu, 8 Nov 2018 18:12:08 +0000 (18:12 +0000)]
very bad hack on xlen=32 to sign-extend out into top bits of 64-bit register
Luke Kenneth Casson Leighton [Thu, 8 Nov 2018 18:11:43 +0000 (18:11 +0000)]
zero-extend mulhu result
Luke Kenneth Casson Leighton [Thu, 8 Nov 2018 12:10:45 +0000 (12:10 +0000)]
add comment
Luke Kenneth Casson Leighton [Thu, 8 Nov 2018 11:08:18 +0000 (11:08 +0000)]
annoyingly, have to modify rv_mulhu to take source reg width as basis
Luke Kenneth Casson Leighton [Wed, 7 Nov 2018 17:29:43 +0000 (17:29 +0000)]
whoops, must use dest bitwidth on mulhsu
Luke Kenneth Casson Leighton [Wed, 7 Nov 2018 16:55:41 +0000 (16:55 +0000)]
elwidth variant of rv_mulhu
Luke Kenneth Casson Leighton [Wed, 7 Nov 2018 11:49:00 +0000 (11:49 +0000)]
mulh* redirect through rv_mul, to save on code
Luke Kenneth Casson Leighton [Wed, 7 Nov 2018 11:42:56 +0000 (11:42 +0000)]
add mul elwidth redirection
Luke Kenneth Casson Leighton [Wed, 7 Nov 2018 11:42:10 +0000 (11:42 +0000)]
add mul elwidth redirection
Luke Kenneth Casson Leighton [Wed, 7 Nov 2018 10:37:20 +0000 (10:37 +0000)]
fix bitwidth issues for rv32 in mulh* and sra
Luke Kenneth Casson Leighton [Wed, 7 Nov 2018 09:24:12 +0000 (09:24 +0000)]
fix fsgn elwidth
Luke Kenneth Casson Leighton [Wed, 7 Nov 2018 09:20:42 +0000 (09:20 +0000)]
attempting to get rv32 mv working
Luke Kenneth Casson Leighton [Wed, 7 Nov 2018 09:14:09 +0000 (09:14 +0000)]
fix length=0 in fsw and fsd
Luke Kenneth Casson Leighton [Wed, 7 Nov 2018 07:46:44 +0000 (07:46 +0000)]
macro-ify rv op elwidth setup/teardown
Luke Kenneth Casson Leighton [Tue, 6 Nov 2018 17:51:11 +0000 (17:51 +0000)]
elwidth rv_rem
Luke Kenneth Casson Leighton [Tue, 6 Nov 2018 17:49:45 +0000 (17:49 +0000)]
unsigned version of div
Luke Kenneth Casson Leighton [Tue, 6 Nov 2018 17:45:15 +0000 (17:45 +0000)]
add unsigned versions of rv_int_op_prepare and finish
Luke Kenneth Casson Leighton [Tue, 6 Nov 2018 16:11:12 +0000 (16:11 +0000)]
add debug info on rv_sr
Luke Kenneth Casson Leighton [Tue, 6 Nov 2018 11:40:22 +0000 (11:40 +0000)]
convert rv_sl to same extra bitwidth arg
Luke Kenneth Casson Leighton [Tue, 6 Nov 2018 11:36:43 +0000 (11:36 +0000)]
convert rv_sl to same extra bitwidth arg
Luke Kenneth Casson Leighton [Tue, 6 Nov 2018 11:35:42 +0000 (11:35 +0000)]
convert rv_sl to same extra bitwidth arg
Luke Kenneth Casson Leighton [Tue, 6 Nov 2018 11:33:26 +0000 (11:33 +0000)]
pass in extra arg (bitwidth) into rv_sr
Luke Kenneth Casson Leighton [Tue, 6 Nov 2018 11:28:14 +0000 (11:28 +0000)]
alter rv_sr to take bitwidth arg
Luke Kenneth Casson Leighton [Tue, 6 Nov 2018 11:20:34 +0000 (11:20 +0000)]
elwidth-ify rv_sl and rv_sr
Luke Kenneth Casson Leighton [Tue, 6 Nov 2018 11:18:43 +0000 (11:18 +0000)]
break int op down into prepare, do, and finish
Luke Kenneth Casson Leighton [Mon, 5 Nov 2018 08:55:04 +0000 (08:55 +0000)]
add CSR_USVCFG set/get
Luke Kenneth Casson Leighton [Mon, 5 Nov 2018 08:51:49 +0000 (08:51 +0000)]
correct bank and size, use in setting up CSR tables
Luke Kenneth Casson Leighton [Mon, 5 Nov 2018 08:07:57 +0000 (08:07 +0000)]
move csr reg and predicate table unpack to separate function
Luke Kenneth Casson Leighton [Mon, 5 Nov 2018 08:01:46 +0000 (08:01 +0000)]
add state and bank sv csr bitfields
Luke Kenneth Casson Leighton [Sun, 4 Nov 2018 16:18:06 +0000 (16:18 +0000)]
debug shape remap
Luke Kenneth Casson Leighton [Sun, 4 Nov 2018 02:27:48 +0000 (02:27 +0000)]
set isvec when predication enabled
Luke Kenneth Casson Leighton [Sat, 3 Nov 2018 15:24:14 +0000 (15:24 +0000)]
raise exception if permutation set to reserved value
Luke Kenneth Casson Leighton [Sat, 3 Nov 2018 15:22:32 +0000 (15:22 +0000)]
add comment on where reshape map is set up
Luke Kenneth Casson Leighton [Sat, 3 Nov 2018 14:00:57 +0000 (14:00 +0000)]
add reshaping algorithm for elements
Luke Kenneth Casson Leighton [Sat, 3 Nov 2018 10:57:49 +0000 (10:57 +0000)]
add stub "remap" of register offsets
Luke Kenneth Casson Leighton [Sat, 3 Nov 2018 10:32:14 +0000 (10:32 +0000)]
add sv shape CSRs
Luke Kenneth Casson Leighton [Sat, 3 Nov 2018 10:26:17 +0000 (10:26 +0000)]
add placeholder CSR uremap get
Luke Kenneth Casson Leighton [Sat, 3 Nov 2018 10:25:42 +0000 (10:25 +0000)]
add remap CSR set
Luke Kenneth Casson Leighton [Sat, 3 Nov 2018 10:17:39 +0000 (10:17 +0000)]
add reshape data structures and get_shape function