anv: Clean up some unused variables

Following on from the spirit of commit 011e5570f.

Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

swr: [rasterizer common/core/jitter] fetch support for GL_FIXED

v2: use fmul(1/65536) instead of fdiv(65535)

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

configure: cleanup GLX_USE_TLS handling

Mesa requires ax_pthread_ok = yes, thus we can fold/rewrite the
conditional to follow the more common "if test" pattern.

No functional change intended.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

configure: enable glx-tls by default

In the (not too) distant future we'd want to remove this option and
effectively drop the other codepath(s) we have in our dispatch.

Linux distributions have been using --enable-glx-tls for a number of
years. Some/most BSD platforms still don't support this, yet this should
serve as an encouragement to move things forwards.

Note: we had many bug reports were opened due to the wrong default
option. See the list below for details.

v2:
 - Correct default option in help string (Andreas)
 - Add bugzilla references.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70623
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72902
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=73778
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89043

Cc: Jean-Sébastien Pédron <dumbbell@FreeBSD.org>
Cc: Jonathan Gray <jsg@jsg.id.au>
Cc: mesa-maintainers@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Andreas Boll <andreas.boll.dev@gmail.com>

docs: document how to (self-) reject stable patches

Document what has been the unofficial way to self-reject stable patches.

Namely: drop the mesa-stable tag and push the commit.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

egl: add and enable EGL_KHR_config_attribs

Extension is already implemented in the main code.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

egl/surfaceless: remove duplicate KHR_image_base enablement

Already set by the core code - dri2_create_screen/dri2_setup_screen

Cc: Chad Versace <chadversary@chromium.org>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>

egl: unexport _eglConvertIntsToAttribs

Nobody else makes use of this function.
We can always re-export it if someone ever needs it.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: rename static functions to match convention

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

compiler/glsl: fix precision problem of tanh

Clamp input scalar value to range [-10, +10] to avoid precision problems
when the absolute value of input is too large.

Fixes dEQP-GLES3.functional.shaders.builtin_functions.precision.tanh.* test
failures.

v2: added more explanation in the comment.
v3: fixed a typo in the comment.

Signed-off-by: Haixia Shi <hshi@chromium.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0" <mesa-dev@lists.freedesktop.org>

swr: [rasterizer core/memory] Finish R24_UNORM_X8_TYPELESS for AVX512

This one-off specialization was missed.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

radv: Use enum for memory types.

Inspired by patches from Eric Engestrom.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Cc: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Use enum for memory heaps.

Inspired by patches from Eric Engestrom.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Cc: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Clean up some unused variables.

Leftovers from anv?

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Dave Airlie <airlied@redhat.com>

i965: delay adding built-in uniforms to Parameters list

This is a step towards using NIR optimisations over GLSL IR
optimisations. Delaying adding built-in uniforms until after
we convert to NIR gives it a chance to optimise them away.

V2: move the new code back to brw_link_shader()

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

swr: [rasterizer core] supply proper clip distances to point sprites

Large points become pairs of triangles when rasterized, so we must feed
it three clip distances, one for each vertex.

The clip distance is not subject to sprite coord replacement, so there's
no interpolation of it. We just take its value and put it in the "z"
component of the barycentric-ready plane equation.

(We could also just cull it at an earlier point in time, but that would
require larger changes.)

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

swr: [rasterizer core] perform perspective division on clip distances

Clip distances need to be perspective-divided. This fixes all the
interpolation-*-{distance,vertex} piglits.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>

radv/ac: no need to pass nir to the post outputs handling

We don't use the nir shader in here at all.

Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: fix warnings in ubo load code.

Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/ac: pass a mask of array params not a number.

This makes it easier to add new params before the array ones.

Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: split out a chunk of variant filling code.

This code will have use for copy shaders etc.

Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/meta: don't pass rect into blit2d src function.

Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/meta: cleanup image info setup.

This just passes the subresource info in and uses it.

Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/meta: split copyimage api into api and meta function

This make it easier to add multiple queues later.

Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/meta: clean up buffer->image code.

Removes some unnecessary functions and pull
some stuff out of the loop.

Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/ac: don't pass nir to create_function

This isn't needed for later things like geom shader copy shaders,
we won't have NIR.

Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: add missing license file to radv_meta_bufimage.

Just noticed this file was missing license and any
explaination of what is in it.

(stable just for license header reasons)
Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/ac: use build_gep0 instead of opencoding it.

Reviewed by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radeonsi: disable the constant engine (CE) on Carrizo and Stoney

It must be disabled until the kernel bug is fixed, and then we'll enable CE
based on the DRM version.

Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: Fix typo: "llvm.fs.interp" => "llvm.SI.fs.interp"

Fixes lots of pixel shaders failing to compile with LLVM 3.9 or older.

Trivial.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99013#c4

radv: make push constants optional

We don't set the push constants slot up unless
something will cause us to need it.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: only emit descriptor sgprs when needed

This only emits enough descriptor sgprs for the number
of sets in the layout, and only emits the descriptors
necessary for the current stage.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: move userdata sgpr ownership to compiler side.

This isn't fully what we want yet, but is a good step on the way.

This allows the compiler to create the information structures
for the state setting side, however the state setting still expects
things to be pretty much in 2 sgpr wide register sets, and can't
handle the indirect setting yet.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: refactor out the constant setting user sgpr code.

This just refactors out some common code to make future changes
easier to understand.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: refactor out the descriptor user sgpr setting.

This just splits some common code into a utility function.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: only bind descriptor sets to stages that need them

This copies the push constant code and only binds descriptor
sets to the stages that need them. It also now has to dirty
descriptors on pipeline binds.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: move descriptor set userdata emission to draw flush time.

This is another step towards having the compiler decide the
user sgpr layout.

This still emits the descriptors sets for all shader types, but
we will fix this later.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: refactor descriptor set userdata emission out.

This just moves this into a separate function.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: pass pipeline to constant flush function

I'll need this later rather than just the layout.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: consolidate compute pipeline flushing (v1.1)

This just moves some common code into a utility function
to avoid having to change multiple places later.

v1.1: rename function to better reflect what it does. (Bas)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radeonsi: wait for outstanding LDS instructions in memory barriers if needed

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

tgsi: fix the src type of TGSI_OPCODE_MEMBAR

It's a literal integer. The next commit will need this.

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: wait for outstanding memory instructions in TCS barriers

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: allow specifying simm16 of emit_waitcnt at call sites

The next commit will use this.

Cc: 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: write shader descriptors into hang reports

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: check for sampler state CSO corruption

It really happens.

v2: declare "magic" in debug builds only

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)

radeonsi: properly declare context sampler states

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: fix incorrect FMASK checking in bind_sampler_states

Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: always restore sampler states when unbinding sampler views

Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: take LDS into account for compute shader occupancy stats

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/mesa: round lod_bias to a multiple of 1/256

This reduces the number of sampler states 3.6x in Batman Arkham: Origins.
(from ~7200 to ~2000)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium: decrease the size of pipe_sampler_state fields

We've had unused bits.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

cso: don't release sampler states that are bound

This fixes random radeonsi GPU hangs in Batman Arkham: Origins (Wine) and
probably many other games too.

cso_cache deletes sampler states when the cache size is too big and doesn't
check which sampler states are bound, causing use-after-free in drivers.
Because of that, radeonsi uploaded garbage sampler states and the hardware
went bananas. Other drivers may have experienced similar issues.

Cc: 12.0 13.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

i965: Increase max texture to 16k for gen7+

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98297
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/blorp_blit: Add split_blorp_blit_debug switch

Enabling this debug switch causes surface shrinking to happen by
default, and lowers the surface size limit which causes blorp blits to
be split.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/blorp_blit: Enable splitting large blorp blits

Detect when the surface sizes are too large for a blorp blit. When it
is too large, the blorp blit will be split into a smaller operation
and attempted again.

For gen7, this fixes the cts test:

ES3-CTS.gtf.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_multisampled_to_singlesampled_blit

It will also enable us to increase our renderable size from 8k x 8k to
16k x 16k.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/blorp_blit: Move RGB=>R conversion to follow blit splitting

In blorp_copy, when RGB surfaces are copied, we convert the
destination surface to a Red only surface, but 3 times as wide. This
introduces an implicit restriction of "mod 3" for the destination
width.

It is easier to handle the blorp split buffer offsetting with the
original RGB surface, and do the RGB=>R after this.

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/blorp_blit: Adjust blorp surface parameters for split blits

If try_blorp_blit() previously returned that a blit was too large,
shrink_surface_params() will be used to update the surface parameters
for the smaller blit so the blit operation can proceed.

v2:
 * Use double instead of float. (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/blorp_blit: Split blorp blits if they are too large

We rename do_blorp_blit() to try_blorp_blit(), and add a return error
if the surface size for the blit is too large. Now, do_blorp_blit() is
rewritten to try to split the blit into smaller operations if
try_blorp_blit() fails.

Note: In this commit, try_blorp_blit() will always attempt to blit and
never return an error, which matches the previous behavior. We will
enable the size checking and splitting in a future commit.

The motivation for this splitting is that in some cases when we
flatten an image, it's dimensions grow, and this can then exceed the
programmable hardware limits. An example is w-tiled+MSAA blits.

v2:
 * Use double instead of float. (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/blorp_blit: Create structure for src & dst coordinates

This will be useful for splitting blits into smaller sizes.

We also make the coordinates of type double rather than float. Since
we will be splitting and scaling the coordinates, we might require
extra precision in the calculations.

v2:
 * Use double instead of float. (Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

vulkan: use STATIC_ASSERT instead of static_assert

Following the spirit of commit 23d1799f, fixes compilation
warnings on Android build due to lack of C11 features.

Signed-off-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: enable INTEL_conservative_rasterization on Gen9+

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>

mesa: add support for GL_INTEL_conservative_rasterization

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>

i965: Add i965 plumbing for ARB_post_depth_coverage for i965 (gen9+).

This extension allows the fragment shader to control whether values in
gl_SampleMaskIn[] reflect the coverage after application of the early
depth and stencil tests.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

mesa: Add GL and GLSL plumbing for ARB_post_depth_coverage for i965 (gen9+).

This extension allows the fragment shader to control whether values in
gl_SampleMaskIn[] reflect the coverage after application of the early
depth and stencil tests.

Signed-off-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Chris Forbes <chrisforbes@google.com>

radeonsi: fix isolines tess factor writes to control ring

Fixes piglit arb_tessellation_shader/execution/isoline{_no_tcs}.shader_test.

Cc: mesa-stable@lists.freedesktop.org

i965: Drop redundant key->outputs_written initialization.

This was already set to the same value earlier.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Initialize "separate" flag in VUE maps.

This was uninitialized, which resulted in weird looking printouts where
it appeared that the TCS output and TES input patch URB entries differed
in SSO/non-SSO layout.  There is no "separable" layout for both, as
they're tied together.

It should have no other actual effect.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

nir: In split_var_copies_block, uint, int, and bool types cannot be matrices

Noticed while adding support for 64-bit integer types.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radeonsi: Use amdgcn intrinsics for fs interpolation

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

freedreno/a5xx: fix draw packet size with index buffer

gpuaddr of idx buffer is now two dwords (64b).

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: gmem bypass mode

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: fix emit_string_marker()

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: pitch alignment should match gmem alignment

Deal w/ differing gmem tile size alignment between generations, and make
sure texture pitch matches.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: more formats

Bunch of stuff we can at least turn on for vbo formats.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: fix fragface

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: fix fragcoord

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno: update generated headers

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: fix alpha test

GRAS_SU_DEPTH_PLANE_CNTL doesn't in fact seem to be anything to do with
alpha test.  This fixes xonotic and (other than some iommu faults) gets
gnome-shell working.

Signed-off-by: Rob Clark <robdclark@gmail.com>

freedreno/a5xx: fix VPC_VAR[n].DISABLE bits

We don't need varying interpolators enabled for pos/psize out of the VS
(despite the fact that they show up in VS_OUT map), so emit these before
we append pos/psize to the linkage.

Signed-off-by: Rob Clark <robdclark@gmail.com>

anv/TODO: Document sampling from HiZ

Acked-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Don't force SSO layout for VS->TCS.

This was a hack which worked around the VS and TCS disagreeing on their
shared interface due to the lack of varying packing.  In particular, it
was needed by Piglit's tcs-input-read-array-interface test.

However, that was just one case where things could go awry, so the
previous commit forcibly made interfaces match.  This hack is no longer
necessary.

It also seems to be broken, though I'm not sure why.  It fixes Piglit
regressions in spec/arb_shader_image_load_store/semantics from commit
ec1f159ac81ed964415d102eed4a0a29be8e7937.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98893
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

i965: Unify shader interfaces explicitly.

A while ago, I made i965 start compiling shaders independently.  The VUE
map layouts were based entirely on each shader's input/output bitfields.
Assuming the interfaces match, this works out well - both sides will
compute the same layout, and outputs are correctly routed to inputs.

At the time, I had assumed that the linker would guarantee that the
interfaces match.  While it usually succeeds, it unfortunately seems
to fail in some cases.

For example, Piglit's tcs-input-read-array-interface test has a VS
output array with two elements, but the TCS only reads one.  The linker
isn't able to eliminate the unused element from the VS, which makes the
interfaces not match.

Another case is where a shader other than the last writes clip/cull
distances.  These should be demoted to ordinary varyings, but they
currently aren't - so we think they still have some special meaning,
and prevent them from being eliminated.

Fixing the linker to guarantee this in all cases is complicated.  It
needs to be able to optimize out dead code.  It's tied into varying
packing and other messiness.  While we can certainly improve it---and
should---I'd rather not rely on it being correct in all cases.

This patch ORs adjacent stages' input/output bitfields together,
ensuring that their interface (and hence VUE map layout) will be
compatible.  This should safeguard us against linker insufficiencies.

Fixes line rendering in Dolphin, and the Piglit test based on it:
spec/glsl-1.50/execution/geometry/clip-distance-vs-gs-out.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97232
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>

genxml/gen9: Change the default of MI_SEMAPHORE_WAIT::RegisterPoleMode

We would really like it to be false as that's what you get on hardware that
doesn't have RegisterPoleMode (Sky Lake for example).  While we're at it,
we change it to a boolean.  This fixes dEQP-VK.synchronization.smoke.events
on Broxton.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>

gallivm: optimize 16bit->32bit gather path a bit

LLVM can't really optimize anything which crosses scalar/vector boundaries,
so help a bit with some particular gather operations when the width is
expanded (only do it for 16->32bit expansion for now), by doing expansion
after fetch. That is probably a better solution anyway even if llvm would
recognize it, makes for cleaner IR...

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

gallivm: handle 16bit float fetches in lp_build_fetch_rgba_soa

Note that we really want to _never_ reach the bottom of the function, which
resorts to AoS fetch.
Half floats can be handled just like other formats which fit into 32bit
vectors (so, only 1x16 and 2x16 formats, albeit with more channels things
are not THAT bad), with minimal plumbing. I've seen code size go down nearly
by a factor of 3 for a complete texture sampling function (including bilinear
filtering) using R16F.
(What we should do for everything not special cased is to do AoS gather,
shuffle/shift things into SoA vectors, and then do the conversion there.
Otherwise it's particularly bad with 1 or 2 channel formats - that r16f
format with either 4 or 8-wide vectors was still doing one element at a
time, essentially doing exactly the same work as for rgba16f. Also replacing
the channels with SWIZZLE0/1 (particularly the latter) adds even more
work, as it has to be done per aos vector, and not just straightforward
at the end with the SoA vector.)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

util: (trivial) ETC1 meets the criteria for fitting into unorm8

Just like other similar compressed formats.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

i965: Emit proper NOPs.

The PRMs for HSW and newer say that other than the opcode and DebugCtrl
bits of the instruction word, the rest must be zero.

By zeroing the instruction word manually, we avoid using any of the
state inherited through brw_codegen.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96959
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

glsl: (trivial) fix type typo

Accidentally changed the type of a constant in
df33f11b39abf313a0db7b9fefaf739b88133161 causing assertion failures.

i965: Allocate at least some URB space even when max_vertices = 0.

Allocating zero URB space is a really bad idea.  The hardware has to
give threads a handle to their URB space, and threads have to use that
to terminate the thread.  Having it be an empty region just breaks a
lot of assumptions.  Hence, why we asserted that it isn't possible.

Unfortunately, it /is/ possible prior to Gen8, if max_vertices = 0.
In theory a geometry shader could do SSBO/image access and maybe
still accomplish something.  In reality, this is tripped up by
conformance tests.

Gen8+ already avoids this problem by placing the vertex count DWord
in the URB entry header.  This fixes things on earlier generations.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Tested-by: Ian Romanick <ian.d.romanick@intel.com>

main: allow NEAREST_MIPMAP_NEAREST for stencil texturing

As per GL 4.5 rules, which fixed a spec mistake in GL_ARB_stencil_texturing.
The extension spec wasn't updated, but just allow it with older GL versions
as well, hoping there aren't any crazy tests which want to see an error
there... (Compile tested only.)

Reported by Józef Kucia <joseph.kucia@gmail.com>

Acked-by: Józef Kucia <joseph.kucia@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl: fix ldexp lowering if bitfield insert lowering is also requested

Trivial, this just resurrects the code which was there once upon a time
(the code can't lower instructions generated in the lowering pass there,
and even if it could it would probably be suboptimal).
This fixes piglit mesa_shader_integer_functions fs-ldexp.shader_test and
vs-ldexp.shader_test with llvmpipe.

Reviewed-by: Matt Turner <mattst88@gmail.com>

radv: fix resource leak in radv_amdgpu_ctx_create

CovID: 1396387

V2. Fixup bad whitespace.

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folkore1984.net>

st/omx/enc Raise default encode level

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=91281
Signed-off-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vce Handle H.264 level 5.2

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=91281
v2: explicitly add case 52

Signed-off-by: Andy Furniss <adf.lists@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

nir: Remove some unused fields from nir_variable

All of these are happily set from glsl_to_nir or spirv_to_nir but their
values are never used for anything.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir: Delete most of the constant_initializer support

Constant initializers have been a constant (ha!) pain for quite some time.
While they're useful from a language perspective, people writing passes or
backends really don't want deal with them most of the time.  This commit
removes most of the constant initializer support from NIR.  It is expected
that you call nir_lower_constant_initializers VERY EARLY to ensure that
they're gone before you do anything interesting.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir: Simplify nir_lower_gs_intrinsics

It's only ever called on single-function shaders.  At this point, there are
a lot of helpers that can make it all much simpler.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir/lower_returns: Stop using constant initializers

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

glsl/nir: Call nir_lower_constant_initializers

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>