swr/rast: enable SIMD16 8x2 tile backend

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: add SwrInit() to init backend/memory tables

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: increment depth/stencil tile pointer in SIMD16 BE

Misplaced #endif preventing depth and stencil hot tile pointers
from incrementing in SIMD16 8x2 configuration of BackendPixelRate.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: add SwrGetInterface() function to return api

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: enable per-warp scratch space for CS

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: reduce simd{16}vertex stack for VS output

Frontend - reduce simdvertex/simd16vertex stack usage for VS output in
ProcessDraw, fixes stack overflow in some of the deeper call stacks under
SIMD16.

1. Move the vertex store out of PA_FACTORY, and off the stack
2. Allocate the vertex store out of the aligned heap (pointer is
   temporarily stored in TLS, but will be migrated to thread pool
   along with other frontend temporary buffers).
3. Grow the vertex store as necessary for the number of verts per
   primitive, in chunks of 8/4 simdvertex/simd16vertex

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: remove default argument from SwrSync()

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: remove unused variables in the SIMD16 FE

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: move construction of const above goto

Fixes gcc error for SIMD16 FE.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: name threads to aid debugging

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: disable buffer overrun warning for Assemble()

Disabling buffer overrun warning for Assemble(uint32_t slot,
simdvector *verts) due to what looks like a MSVC compiler bug
when compiling the SIMD16 FE.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: clean up clipper comments

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: add SIMDAPI decorators in binner/clipper

Fixes MSVC errors with SIMD16 FE.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: add additional jit utility functions

Not used yet.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: more flexible max attribute slots

Ability to allocate space for an arbitrary number (at compile time)
of positions in the vertex layout.

Removes KNOB_NUM_ATTRIBUTES from knobs.h, replaces the VTX slot
number #defines with the SWR_VTX_SLOTS enum (which contains
replacement for NUM_ATTRIBUTES: SWR_VTX_NUM_SLOTS)

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

i965: Drop BRW_NEW_CONTEXT from 3DSTATE_DS/GS on Gen7-7.5.

We already have BRW_NEW_BATCH, which completely covers all the cases
that BRW_NEW_CONTEXT would handle.  Drop it.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Drop _NEW_TRANSFORM from 3DSTATE_DS/GS on Gen7-7.5.

There's no reason for this as far as I can tell.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Set point rasterization rule to UPPER_RIGHT on Gen6-7.5.

Gen4-5 and Gen8+ already set this, but Gen6-7.5 did not.  We ought to
be consistent - the answer depends on the API, not the hardware generation.

The Sandybridge PRM says about RASTRULE_UPPER_RIGHT:

   "To match OpenGL point rasterization rules (round to +infinity, where
    this is the upper right direction wrt OpenGL screen origin of lower
    left).

So this is likely the one we should use.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>

i965: Always set AALINEDISTANCE_TRUE on Sandybridge.

We set this unconditionally on every other platform.  Zero (Manhattan)
isn't even listed as an option in the Sandybridge docs - only "true".

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

i965: Use true AA line distance on G45/Ironlake.

The original Broadwater and Crestline platforms computed antialiased
line distances using "manhattan" distance, aka a + b = c.  Eaglelake
and Cantiga added "true" distance, which apparently does something
like max(a, b) + min(a, b) / 4.  Not exactly "true", but at least
more accurate.

The G45 documentation indicates that the old manhattan distance setting
is "only for debug purposes" and should never be used.  The Ironlake
documentation no longer mentions AALINEDISTANCE_MANHATTAN, though it
does still contain the narrative about the feature.

At any rate, we should use the more accurate mode.

Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>

docs: add news item and link release notes for 17.0.5

Signed-off-by: Andres Gomez <agomez@igalia.com>

docs: add sha256 checksums for 17.0.5

Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 6cb65ce2d3689ae7f692f8cf08559109037dd74e)

docs: add release notes for 17.0.5

Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 61b134a862ecc1877bbe2f2c14e493b5fb607e04)

radeonsi: don't load unused compute shader input SGPRs and VGPRs

Basically, don't load GRID_SIZE or BLOCK_SIZE if they are unused, determine
whether to load BLOCK_ID for each component separately, and set the number
of THREAD_ID VGPRs to load. Now we should get the maximum CS launch wave
rate in most cases.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

tgsi/scan: record compute shader system value usage

v2: just do indexing with swizzle[i]

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add a HUD query for draw calls with primitive restart

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radeonsi: tell LLVM not to remove s_barrier instructions

LLVM 5.0 removes s_barrier instructions if the max-work-group-size
attribute is not set. What a surprise.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: fix tess offchip offset for per-patch attributes

We need 4 more bits there. I don't know what is fixed by this.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: pass tessellation ring addresses via user SGPRs

This removes s_load_dword latency for tess rings.

We need just 1 SGPR for the address if we use 64K alignment. The final asm
for recreating the descriptor is:

    // s2 is (address >> 16)
    s_mov_b32 s3, 0
    s_lshl_b64 s[4:5], s[2:3], 16
    s_mov_b32 s6, -1
    s_mov_b32 s7, 0x27fac

v2: bitcast the descriptor type from v2i64 to v4i32

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: use si_insert_input_ret in si_llvm_emit_tcs_epilogue

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove VS epilog code, compile VS with PrimID export on demand

The use of PrimID in the pixel shader is too rare to deserve such
a sizable support code.

The initial idea of the VS epilog was to move the clipping code there and
remove it based on states, but optimized variants are now used to do that
and are easier to support, so the VS epilog has turned out to be not so
useful.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: get InstanceID from VGPR1 (or VGPR2 for tess) instead of VGPR3

VGPR1 = InstanceID / StepRate0; // StepRate0 can be set to 1

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't load PrimID in TES if it's not used

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: explain (non-)monolithic shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: enable OpenGL 4.5

Tentatively enable it, expecting the scratch buffer support to be done before
the next Mesa release.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: 2nd shader of merged shaders should hold a reference of the 1st

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add reference counting for shader selectors

The 2nd shader of merged shaders should take a reference of the 1st shader.
The next commit will do that.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set VGT_VERTEX_REUSE for ES in ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set TES registers for merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: disallow scratch buffer for LS-HS and ES-GS

not implemented yet

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: always compile monolithic ES-GS (asynchronously)

In addition to the non-monolithic variant.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add support for monolithic ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: make sure the 1st shader's main part exists for merged shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: select shader parts for non-monolithic ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add GS prolog support for merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add VS prolog support for merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: pass GS input SGPRs and VGPRs from the ES part to GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: store ES outputs to LDS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: load GS inputs from LDS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: get GS wave ID from the correct input

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add the function signature of merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set registers and shader key for merged ES-GS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add GS user SGPRs

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: rename declare_tess_lds -> declare_lds_as_pointer

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: simplify some shader type conditions

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: rename the swizzle parameter of lds_store

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add si_shader::prolog2

For a GS prolog in merged ES-GS.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: move RW_BUFFERS to s[0:1] for merged shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add support for monolithic merged LS-HS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set EXEC for non-mono merged shaders, add a barrier between them

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't store the HS control word

GFX9 doesn't have it.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: pass inputs from LS to TCS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add TCS epilog support for merged LS-HS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add VS prolog support for merged LS-HS

HS input VGPRs must be reserved.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: merged shaders have scratch offset at the beginning

also, screen wasn't initialized for compute shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: define LS-HS main shader function prototype

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: assign VS/TCS/TES/GS shader input parameter locations dynamically

They will vary with merged stages.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: define and set LS-HS user SGPRs

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: set up shader registers for merged LS-HS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add initial code generation for non-monolithic merged LS-HS

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: separate out code for selecting the VS prolog

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: add si_shader::previous_stage for merged shaders

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: enlarge num_input_sgprs in shader keys due to higher hw limit

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: update the summary of shader stage configs

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: adjust the signature of si_get_vs_prolog_key

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: separate out VS prolog key generation

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: separate out VS prolog key printing

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: code shuffling in si_emit_derived_tess_state

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: separate out TGSI initialization of si_shader_context

so that we can put multiple different TGSI shaders into one module.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/mesa: use min_index and max_index directly from vbo

also remove the incorrect comment about primitive restart.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

vbo: set min_index = 0 so gallium can use the value directly

We could also remove index_bounds_valid and use max_index != ~0 instead.
Opinions on that are welcome.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

Revert "glsl: reject image qualifiers with non-image types inside uniform blocks"

This reverts commit 24011ead71ea9980e6b34e40d9dbd64e6560f5a4.

This causes lots of ES 3.1 CTS tests to fail to compile a bit of code
like:

   layout(binding = 0) buffer InOut
   {
        highp uint inputValues[384];
        highp uint outputValues[384];
        coherent highp uint groupValues[64];      <-----
   } sb_inout;

   error: memory qualifiers may only be applied to images

st/mesa: add more fallback gallium formats for GL integer formats

The VMware driver has a limited set of integer texture formats.  We
often have to fall back to 4-component formats when 1- or 2-component
formats are missing.

This fixes about 8 integer texture Piglit tests with the VMware driver
on Linux.  We've had this code in-house for a long time but I guess it
was never up-streamed to Mesa master.

This shouldn't regress any other drivers since we're either choosing
an earlier format in the list, or failing anyway.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa: optimize color_buffer_writes_enabled()

Return as soon as we find an existing color channel that's enabled for
writing.  Typically, this allows us to return true on the first loop
iteration intead of doing four iterations.

No piglit regressions.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: whitespace clean-ups in st_manager.c

Trivial.

Revert "glsl: set vector_elements to 1 for samplers"

This reverts commit 75a31a20af269c047661af33e28f793269537b79.

This breaks thousands of tests on i965 with malloc corruption.

anv: Drop 'x11' prefix from non-X11 WSI funcs

Drop it from x11_anv_wsi_image_create and x11_anv_wsi_image_free. The
functions are used by Wayland WSI too.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

anv: Alphabetize KHR extensions

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

ac: automake: sort sources list alphabetically

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

ac: include all sources in the tarball

Fixes: e2659176cef ("radeonsi/ac: move vertex export remove to common code.")
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>

st/mesa: remove redundant stfb->iface checks

stfb->iface is always non-NULL for an st_framebuffer. These checks
were incorrect, relying on out-of-bounds memory access in the
surface-less case of EGL_KHR_surfaceless_context.

v2: remove redundant stread check (Marek)

Reviewed-by: Marek Olšák <marek@olsak@amd.com> (v2)

st/mesa: don't cast the incomplete framebufer to st_framebuffer

The incomplete framebuffer is set for a surfaceless context. This leads to
the following error in piglit spec@egl_khr_surfaceless_context@viewport:

==26703==ERROR: AddressSanitizer: global-buffer-overflow on address 0x7f6886e43240 at pc 0x7f68854db0fd bp 0x7ffca404b3b0 sp 0x7ffca404b3a0
READ of size 8 at 0x7f6886e43240 thread T0
    #0 0x7f68854db0fc in st_viewport ../../../mesa-src/src/mesa/state_tracker/st_cb_viewport.c:57
    #1 0x556840176cdb in main tests/egl/spec/egl_khr_surfaceless_context/viewport.c:101
    #2 0x7f688edcf3f0 in __libc_start_main (/lib/x86_64-linux-gnu/libc.so.6+0x203f0)
    #3 0x556840176e19 in _start (/home/nha/amd/piglit/bin/egl-surfaceless-context-viewport+0xe19)

0x7f6886e43240 is located 32 bytes to the left of global variable 'DummyRenderbuffer' defined in '../../../mesa-src/src/mesa/main/fbobject.c:69:31' (0x7f6886e43260) of size 112
0x7f6886e43240 is located 8 bytes to the right of global variable 'IncompleteFramebuffer' defined in '../../../mesa-src/src/mesa/main/fbobject.c:73:30' (0x7f6886e42de0) of size 1112
SUMMARY: AddressSanitizer: global-buffer-overflow ../../../mesa-src/src/mesa/state_tracker/st_cb_viewport.c:57 in st_viewport

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek@olsak@amd.com>

st/glsl_to_tgsi: make undef_src and undef_dst const

st/glsl_to_tgsi: cleanup using visit_generic_intrinsic

It turns out that explicitly setting the writemask isn't actually
needed; emit_asm does the right thing based on looking at the types.

glsl: remove the shader_group_vote and shader_ballot expression ops

They are now no longer used.

glsl: implement arb_shader_ballot builtins using intrinsics

glsl: implement arb_shader_group_vote builtins via intrinsics

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/glsl_to_tgsi: implement shader_group_vote and shader_ballot intrinsics

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: add intrinsics for ARB_shader_group_vote and ARB_shader_ballot

These operations are currently implemented as IR expressions. However,
they cannot be transformed and moved in the way that other IR
expressions can because they have non-trivial interactions with
control-flow.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: reject image qualifiers with non-image types inside uniform blocks

Fixes the following ARB_shader_image_load_store tests:

format-layout-with-non-image-type.frag
memory-qualifier-with-non-image-type.frag

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>