Samuel Pitoiset [Wed, 11 Mar 2020 15:07:18 +0000 (16:07 +0100)]
radv: fix 32-bits build (again)
Fixes: dcfc08f5b8a ("radv/sqtt: describe begin/end command buffers with user markers")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4044>
Marek Olšák [Wed, 12 Feb 2020 22:49:45 +0000 (17:49 -0500)]
mesa: don't unroll glMultiDrawElements with user indices for gallium
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3591>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3591>
Marek Olšák [Fri, 14 Feb 2020 21:01:50 +0000 (16:01 -0500)]
gallium: add PIPE_CAP_DRAW_INFO_START_WITH_USER_INDICES
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3591>
Marek Olšák [Sun, 8 Mar 2020 21:58:49 +0000 (17:58 -0400)]
vbo: fix vbo_copy_vertices for GL_PATCHES and adjacency primitive types
Fixes: 4c6323c49f1 - vbo: handle GS and tess primitive types when splitting Begin/End
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3591>
Marek Olšák [Thu, 27 Feb 2020 21:04:00 +0000 (16:04 -0500)]
vbo: fix transitions from glVertexN to glVertexM where M < N
Fixes: 1f6e53e2 "vbo: don't store glVertex values temporarily into exec"
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3591>
Marek Olšák [Thu, 27 Feb 2020 20:46:11 +0000 (15:46 -0500)]
vbo: use vbo_exec_wrap_upgrade_vertex for glVertex in ATTR_UNION
We can't decrease the size for glVertex before a flush,
so use vbo_exec_wrap_upgrade_vertex directly.
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3591>
Marek Olšák [Sat, 2 Nov 2019 03:55:58 +0000 (23:55 -0400)]
st/mesa: keep serialized NIR instead of nir_shader in st_program
This decreases memory usage, because serialized NIR is more compact.
The first variant is created from nir_shader for uncached shaders.
All other variants are created from serialized NIR.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2909>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2909>
Michel Dänzer [Tue, 10 Mar 2020 09:16:47 +0000 (10:16 +0100)]
gitlab-ci: Don't restrict ppc64el/s390x build jobs to gstreamer runners
The packet runners have beefier CPUs now and don't seem to run into
test timeouts anymore.
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4128>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4128>
Andres Gomez [Sat, 7 Mar 2020 23:32:17 +0000 (01:32 +0200)]
gitlab-ci: Sort packages to install alphabetically
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Andres Gomez [Sat, 7 Mar 2020 23:30:45 +0000 (01:30 +0200)]
gitlab-ci: Remove unneeded python3-pilkit dependency
It was added with tracie, but it doesn't depend on it.
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Andres Gomez [Sat, 7 Mar 2020 23:29:02 +0000 (01:29 +0200)]
gitlab-ci: Fix indentation and dangerous "\" in the last multiline line
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Chris Lord [Thu, 5 Mar 2020 16:37:53 +0000 (16:37 +0000)]
vc4: Fix query_dmabuf_modifiers mis-reporting external_only property
vc4_screen_query_dmabuf_modifiers doesn't consider that the given format
may only be supported by lowering, which only happens for external
textures.
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4063>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4063>
Timur Kristóf [Mon, 9 Mar 2020 15:27:54 +0000 (16:27 +0100)]
aco: Don't store TCS outputs to LDS when we're sure that none are read.
This allows us not to write an output to LDS, even if it has
an indirect offset.
No pipeline DB changes.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Sat, 7 Mar 2020 00:51:39 +0000 (01:51 +0100)]
aco: Only write TCS outputs to LDS when they are read by the TCS.
Note that tess factors are always read at the end of the shader,
so those are still always saved to LDS.
Totals from affected shaders:
VGPRS: 25244 -> 25164 (-0.32 %)
Code Size:
1768268 ->
1690804 (-4.38 %) bytes
Max Waves: 4947 -> 4953 (0.12 %)
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Fri, 6 Mar 2020 19:24:55 +0000 (21:24 +0200)]
aco: Store tess factors in VMEM only at the end of the shader.
This optimizes out several superfluous stores of the tess factors,
especially if the shader wrote those outputs multiple times.
Pipeline DB changes on GFX10:
Totals from affected shaders:
SGPRS: 30384 -> 29536 (-2.79 %)
Code Size:
2260720 ->
2214484 (-2.05 %) bytes
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Mon, 24 Feb 2020 14:27:43 +0000 (15:27 +0100)]
aco: Don't generate an if when the first part of a merged HS or GS is empty.
In some cases (eg. in a few tessellation CTS tests) the VS part of
a merged HS is completely empty. Let's not generate a divergent if
in these cases. (LLVM also doesn't do it.)
No pipeline DB changes, only affects the CTS.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Sat, 29 Feb 2020 10:59:58 +0000 (11:59 +0100)]
radv: Enable ACO on all stages.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Sat, 29 Feb 2020 10:57:58 +0000 (11:57 +0100)]
aco: Enable running TES as ES, including merged TES+GS.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Thu, 27 Feb 2020 19:05:16 +0000 (20:05 +0100)]
radv: Enable ACO for TES when there is no GS.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Fri, 28 Feb 2020 14:27:41 +0000 (15:27 +0100)]
aco: Implement loading TES inputs.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Fri, 6 Mar 2020 11:52:35 +0000 (13:52 +0200)]
aco: Enable streamout when TES runs on the HW VS stage.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Fri, 6 Mar 2020 11:51:17 +0000 (13:51 +0200)]
aco: Store TES outputs when TES runs on the HW VS stage.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Thu, 27 Feb 2020 18:59:37 +0000 (19:59 +0100)]
aco: Use TES output info when TES runs on the VS stage.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Thu, 27 Feb 2020 18:56:35 +0000 (19:56 +0100)]
aco: Setup tessellation evaluation shader variables.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Wed, 26 Feb 2020 17:31:34 +0000 (18:31 +0100)]
radv: Enable ACO for tessellation control shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Mon, 9 Mar 2020 11:44:03 +0000 (12:44 +0100)]
aco: Fix LS VGPR init bug on affected hardware.
Vega 10 and Raven have a HW bug: when the HS thread count is zero,
the LS input arguments are loaded in the wrong registers. This commit
works around this by using the registers where the data actually is,
for the affected arguments.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Tue, 18 Feb 2020 16:51:05 +0000 (17:51 +0100)]
aco: Store VS outputs correctly when tessellation is used.
When tessellation is used, the VS runs on the HW LS stage (merged
into HS on GFX9-10). This commit enables such VS to store its
outputs properly in LDS so that the TCS can load them as its
per-vertex inputs.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Fri, 21 Feb 2020 16:46:15 +0000 (17:46 +0100)]
aco: Implement tessellation control shader input/output.
Tessellation control shaders can have per-vertex inputs,
and both per-vertex and per-patch outputs. TCS can not only store,
but also load their outputs.
The TCS outputs are stored in RING_HS_TESS_OFFCHIP in VMEM, which
is where the TES reads them from. Additionally, the are also stored
in LDS to make sure they can be loaded fast when read by the TCS.
Tessellation factors are always just stored in LDS.
At the end of the shader, the first shader invocation reads these
from LDS and writes them to RING_HS_TESS_FACTOR in VMEM, and
additionally to RING_HS_TESS_OFFCHIP when they are read by
the Tessellation Evaluation Shader.
This implementation matches the memory layouts used by radv_nir_to_llvm.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Mon, 9 Mar 2020 16:07:41 +0000 (17:07 +0100)]
aco: Fix combining DS additions in the optimizer.
Previously, it was calculated incorrectly for 64-bit writes and reads.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Wed, 26 Feb 2020 17:24:42 +0000 (18:24 +0100)]
aco: Slight fix to lds_store and lds_load.
This commit fixes lds_store and lds_load so that they can
properly support 32 and 64-bit loads and stores; and makes
them a little more reusable so they can be used by
tessellation control shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Fri, 28 Feb 2020 15:20:01 +0000 (16:20 +0100)]
aco: Refactor VS output stores in preparation for tessellation.
This commit takes the new helpers into use by the VS output
store function. This function is also where the VS outputs will
be handled when the VS runs on the HW LS stage.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Fri, 28 Feb 2020 15:06:19 +0000 (16:06 +0100)]
aco: Refactor load_per_vertex_input in preparation for tessellation.
This commit carves out the GS per-vertex input load, and takes the
new helper functions into use.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Fri, 28 Feb 2020 14:50:54 +0000 (15:50 +0100)]
aco: Introduce new helpers for calculating address offsets.
These helpers are going to make it unnecessary to reimplement the
(almost) same address offset calculation in mulitple places.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Fri, 28 Feb 2020 14:48:01 +0000 (15:48 +0100)]
aco: Introduce new VMEM load/store helpers.
These are going to be used for loading and storing inputs
and outputs in various stages, such as GS, TCS and TES.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Tue, 18 Feb 2020 19:21:20 +0000 (20:21 +0100)]
aco: Remove esgs_itemsize from LDS alignment calculation.
It was problematic to have it, because some shader stages might
not even know about the esgs_itemsize, for example TCS and
the merged VS+TCS stages.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Tue, 18 Feb 2020 15:54:44 +0000 (16:54 +0100)]
aco: Extract LDS alignment calculation to a separate function.
This function is going to be reused in multiple functions when
storing or loading something in the LDS.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Wed, 12 Feb 2020 13:27:05 +0000 (14:27 +0100)]
aco: Remove vertex_geometry_gs assertion from merged shaders.
We are going to support more kinds of merged shaders, such
as vertex_tess_control_hs and tess_eval_geometry_gs.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Tue, 18 Feb 2020 14:55:54 +0000 (15:55 +0100)]
aco: Use mesa shader stage when loading inputs.
This makes it more clear which stages should load these inputs.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Wed, 12 Feb 2020 14:33:02 +0000 (15:33 +0100)]
aco: Setup correct HW stages when tessellation is used.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Sat, 7 Mar 2020 17:26:52 +0000 (18:26 +0100)]
aco: Implement load_view_index for TCS and TES.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Fri, 6 Mar 2020 12:02:03 +0000 (14:02 +0200)]
aco: Implement memory_barrier_tcs_patch.
TCS outputs are going to be written to LDS, so it
has to use memory_barrier_shared in order to ensure
that it waits for LDS writes.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Wed, 26 Feb 2020 16:41:04 +0000 (17:41 +0100)]
aco: Implement control_barrier for tessellation control shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Wed, 12 Feb 2020 13:28:29 +0000 (14:28 +0100)]
aco: Implement load_invocation_id for tessellation control shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Tue, 25 Feb 2020 12:20:36 +0000 (13:20 +0100)]
aco: Implement load_patch_vertices_in.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Mon, 24 Feb 2020 16:10:13 +0000 (17:10 +0100)]
aco: Implement load_primitive_id for tessellation shaders.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Mon, 17 Feb 2020 15:56:39 +0000 (16:56 +0100)]
aco: Implement load_tess_coord.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Wed, 12 Feb 2020 14:22:17 +0000 (15:22 +0100)]
aco: Setup tessellation control shader variables.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Wed, 12 Feb 2020 13:23:17 +0000 (14:23 +0100)]
aco: Extract setup_gs_variables into a separate function.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Timur Kristóf [Mon, 24 Feb 2020 14:44:48 +0000 (15:44 +0100)]
radv: Move some helper functions to the radv_shader.h header file.
Move calculate_tess_lds_size and get_tcs_num_patches to radv_shader.h
ACO will need to call these functions too.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3964>
Pierre-Eric Pelloux-Prayer [Sun, 8 Mar 2020 08:01:42 +0000 (09:01 +0100)]
vdpau: remove bogus assert
The assert introduced by
24f2b0a8560 triggers when an application
requests a chroma_type that's different to the one from the
PIPE_VIDEO_CAP_PREFERED_FORMAT (before this change the chroma_type
was set but ignored).
So restore this behavior and ignore the chroma_type.
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Fixes: 24f2b0a8560 ("gallium/video: remove pipe_video_buffer.chroma_format")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4104>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4104>
Samuel Pitoiset [Tue, 10 Mar 2020 17:35:15 +0000 (18:35 +0100)]
radv: do not recursively begin/end render pass for meta operations
To avoid breaking SQTT user markers that are emitted to report
barriers and layout transitions to RGP.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4136>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4136>
Vasily Khoruzhick [Tue, 10 Mar 2020 08:11:11 +0000 (01:11 -0700)]
lima/gpir: print acc ops even if we have only one source
floor and sign have only one source, so we need to print acc ops
even if src1 is unused.
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4110>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4110>
Vasily Khoruzhick [Sun, 8 Mar 2020 23:38:21 +0000 (16:38 -0700)]
lima/gpir: improve disassembler output
Print each op at new line and add unit name suffix for each op.
It improves readability a bit and gives us a hint what unit
was used for particular op.
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4110>
Vasily Khoruzhick [Sun, 8 Mar 2020 18:05:12 +0000 (11:05 -0700)]
lima: print gp uniforms if gp debug is enabled
Since we keep other constants there as well it's useful for reading disassembly.
Reviewed-by: Andreas Baierl <ichgeh@imkreisrum.de>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4110>
Samuel Pitoiset [Mon, 9 Mar 2020 16:53:51 +0000 (17:53 +0100)]
gitlab-ci: add rules:changes for RADV
Including mesa_core_file_list is probably not the best but it's
better than nothing.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4117>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4117>
John Stultz [Tue, 10 Mar 2020 03:27:35 +0000 (03:27 +0000)]
gallium: hud_context: Fix scalar initializer warning.
When trying to build mesa/master under AOSP, I've run into the
following error:
external/mesa3d/src/gallium/auxiliary/hud/hud_context.c:1821:31: error: braces around scalar initializer [-Werror,-Wbraced-scalar-init]
struct sigaction action = {{0}};
^~~
1 error generated.
This patch addresses this by switching to using memset instead of
using an initializer.
Signed-off-by: John Stultz <john.stultz@linaro.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4141>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4141>
John Stultz [Tue, 10 Mar 2020 03:37:44 +0000 (03:37 +0000)]
panfrost: Move pan_afbc.c file to the the right Makefile.source file
It seems pan_afbc.c was added to the wrong Makefile.sources file.
So fix this, so we don't run into build issues with mesa/master
trying to build under AOSP.
Signed-off-by: John Stultz <john.stultz@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4141>
John Stultz [Tue, 10 Mar 2020 03:14:34 +0000 (03:14 +0000)]
freedreno: Add ir3_cf.c and ir3_delay.c to Makefile.sources
This patch adds missing ir3_cf.c and ir3_delay.c files to
the Makefile.sources file to address build issues seen
when trying to build mesa/master on AOSP
Signed-off-by: John Stultz <john.stultz@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4141>
Marek Olšák [Thu, 5 Mar 2020 20:09:28 +0000 (15:09 -0500)]
gallium/cso_context: remove cso_delete_xxx_shader helpers to fix the live cache
With the live shader cache, equivalent shaders can be backed by the same
CSO. This breaks the logic that identifies whether the shader being deleted
is bound.
For example, having shaders A and B, you can bind shader A and delete
shader B. Deleting shader B will unbind shader A if they are equivalent.
Pierre-Eric figured out the root cause for this issue.
Fixes: 0db74f479b9 - radeonsi: use the live shader cache
Closes: #2596
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4078>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4078>
Eric Engestrom [Tue, 10 Mar 2020 17:54:41 +0000 (18:54 +0100)]
vulkan/wsi: fix cleanup when dup() fails
Fixes: f5433e4d6ce247b86dae ("vulkan/wsi: Add modifiers support to wsi_create_native_image")
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4137>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4137>
Karol Herbst [Tue, 10 Mar 2020 22:41:26 +0000 (22:41 +0000)]
Revert "gallium: make handles of set_global_binding 64 bit"
This reverts commit
e1ffb72a05f9b50ee47767aaadbab3e47896ee14
Karol Herbst [Fri, 28 Feb 2020 14:54:08 +0000 (15:54 +0100)]
gallium: make handles of set_global_binding 64 bit
needed by CL
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4072>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4072>
Alyssa Rosenzweig [Tue, 10 Mar 2020 12:21:35 +0000 (08:21 -0400)]
pan/bi: Implement comparison opcodes via BI_CMP
Pretty straightforward for the moment. Ideally these would be fused into
csel/branches but that will come a bit later.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 12:47:39 +0000 (08:47 -0400)]
pan/bi: Print source types unconditionally
We track them all now, let's use them.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 12:47:20 +0000 (08:47 -0400)]
pan/bi: Specify comparison op for BI_CMP
...and adjust printing so we can use it as an op name.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 12:33:11 +0000 (08:33 -0400)]
pan/bi: Lower b2f to bcsel
Since we can get a zero for free and a one inlined into the constant,
the obvious turns out to be efficient (while allowing flexibility for
boolean size).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 12:32:56 +0000 (08:32 -0400)]
pan/bi: Implement nir_op_bcsel
No condition fusing yet.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 12:20:59 +0000 (08:20 -0400)]
pan/bi: Import algebraic pass from midgard
We'll need some of these at least.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 12:03:20 +0000 (08:03 -0400)]
pan/bi: Add isub op
Can't be a regular ADD since there's no negate modifier for integers
(it's a different opcode entirely).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 11:56:14 +0000 (07:56 -0400)]
pan/bi: Disable lower_sub
For float, fixing up the modifier ourselves is easy. For int, we have a
dedicated isub instruction anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 11:52:24 +0000 (07:52 -0400)]
pan/bi: Implement fabs, fneg as fmov with mods
Fusing will come later with the appropriate NIR support.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 01:20:20 +0000 (21:20 -0400)]
pan/bi: Handle special ops in NIR->BIR
Only on supported GPUs at the moment; for older Bifrost that don't
support these, I'm not sure yet where the right place to do the lowering
is. NIR algebraic rules would be "nice" but probably impractical -- but
it wouldn't be hard to do it directly in BIR (as a lowering pass or
alternative implementation).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 01:20:03 +0000 (21:20 -0400)]
pan/bi: Add BI_SPECIAL_* enum
To disambiguate the different special ops from each other.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 01:10:41 +0000 (21:10 -0400)]
pan/bi: Add a bunch of ALU ops
These are all regular ALU ops found in GLES2 which makes them
particularly nice targets at the moment. Just translate straight to our
IR.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 01:02:51 +0000 (21:02 -0400)]
pan/bi: Implement fsat as mov.sat
Soon we'll have a NIR support to handle this the Right Way along with
pos and sat_signed support, but we'll always need the fallback anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 00:32:00 +0000 (20:32 -0400)]
pan/bi: Allow inlining constants
This will allow us to optimize out the constant moves (although that
will require a DCE pass which has yet to be written).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 00:19:51 +0000 (20:19 -0400)]
pan/bi: Add initial handling of ALU ops
We do the bare minimum translation, just enough for fmov/fadd/fmul right
now with no modifiers / inlined constants / etc. The rest is to come!
But hopefully I got bitsize handling right this time around.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Mon, 9 Mar 2020 23:56:35 +0000 (19:56 -0400)]
pan/bi: Lower vec* to writemasks in NIR
I was hoping not to tread down this path but it seems inevitable now.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Mon, 9 Mar 2020 23:52:56 +0000 (19:52 -0400)]
pan/bi: Remove bi_load
This is now made redundant with writemasks, so let's regularize the IR.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Mon, 9 Mar 2020 18:25:00 +0000 (14:25 -0400)]
pan/bi: Introduce writemasks
I feel so dirty. But this will let the IR be a lot more flexible seeing
as we really are vector in a certain sense (I/O, small types)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Mon, 9 Mar 2020 18:09:04 +0000 (14:09 -0400)]
pan/bi: Generalize swizzles to avoid extracts
We'd really rather not emit extracts. We are approaching on a vector IR
anyway which is annoying but really necessary to handle I/O and fp16
correctly. So let's just go all the way and deal with swizzles and masks
within reason; it'll still be somewhat saner in the long-term.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Alyssa Rosenzweig [Tue, 10 Mar 2020 00:19:29 +0000 (20:19 -0400)]
panfrost: Move mir_to_bytemask to common code
...also so we can start sharing code properly between the panfrost
compilers.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
Rob Clark [Tue, 10 Mar 2020 15:10:22 +0000 (08:10 -0700)]
freedreno/fdperf: set locale
Set local to get numbers printed w/ commas.. much easier to read that
way.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4119>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4119>
Rob Clark [Sun, 8 Mar 2020 23:42:23 +0000 (16:42 -0700)]
freedreno/computerator: add performance counter support
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4119>
Jason Ekstrand [Mon, 2 Mar 2020 23:26:43 +0000 (17:26 -0600)]
vulkan/wsi: Return an error if dup() fails
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4135>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4135>
Jason Ekstrand [Mon, 2 Mar 2020 23:05:59 +0000 (17:05 -0600)]
vulkan/wsi: Don't leak the FD when GetImageDrmFormatModifierProperties fails
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4135>
Rob Clark [Wed, 4 Mar 2020 17:06:51 +0000 (09:06 -0800)]
freedreno/ir3: try to avoid syncs
Update postsched to be better aware of where costly (ss) syncs would
result. Sometimes it is better to allow a nop or two, to avoid a
sync quickly after an SFU.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Rob Clark [Fri, 28 Feb 2020 20:48:16 +0000 (12:48 -0800)]
freedreno/ir3: round-robin RA
In the second (scalar pass) use the information about # of registers
used in the first pass as the target max, and round-robin within that
range. This generally gives the post-RA sched pass more opportunities
to re-order instructions to remove nop's.
Also, we can be a bit clever when assigning dest registers for SFU
instructions, by picking the register used for it's src (if available
and already assigned). This avoids some (ss) syncs caused by write
after read hazards. (Ie. the SFU instruction will read it's own src
before writing dest.)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Rob Clark [Fri, 28 Feb 2020 19:02:26 +0000 (11:02 -0800)]
freedreno/ir3: track register usage in first RA pass
We'll use the feedback from the first pass to select a target register
usage in the second pass.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Rob Clark [Fri, 28 Feb 2020 23:45:53 +0000 (15:45 -0800)]
freedreno/ir3: fix has_latency_to_hide
Also count tex-prefetch instructions. And only let the no-latency rule
kick in for frag shaders.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Rob Clark [Fri, 28 Feb 2020 20:47:29 +0000 (12:47 -0800)]
freedreno/ir3: split out has_latency_to_hide()
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Rob Clark [Mon, 9 Mar 2020 21:20:50 +0000 (14:20 -0700)]
util/ra: move NO_REG to header
In the select_reg callback, I want to be able to determine if a given
node is already assigned, and if so what physical register has been
assigned.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Rob Clark [Fri, 28 Feb 2020 18:06:54 +0000 (10:06 -0800)]
util/ra: spiff out select_reg_callback
Add a parameter so the callback can know which node it is selecting a
register for. And remove the graph parameter, as it is unused by
existing users, and somewhat unnecessary (ie. the callback data could
be used instead).
And add a comment so $future_me remembers how this works.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Rob Clark [Sun, 1 Mar 2020 22:16:59 +0000 (14:16 -0800)]
freedreno: fix FD_MESA_DEBUG=inorder
Fixes: 2c07e03b792 ("freedreno: allow ctx->batch to be NULL")
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Rob Clark [Wed, 4 Mar 2020 18:51:10 +0000 (10:51 -0800)]
freedreno/ir3: add simplified stall estimation
Doesn't take into account stalls that result from a register written in
a different block, etc. But this should be more useful than just using
number of (ss)'s by trying to estimate how costly a given sync is.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Rob Clark [Tue, 25 Feb 2020 18:42:57 +0000 (10:42 -0800)]
freedreno/ir3: remove extra nops inserted in scheduler
They were inserting a nop between back to back SFU instrucions. But
that doesn't actually appear to be required. And they get stripped out
later anyways before legalize.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Rob Clark [Sun, 1 Mar 2020 22:20:56 +0000 (14:20 -0800)]
freedreno/computerator: add hrsq/hlog2/hexp2
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Rob Clark [Wed, 4 Mar 2020 20:06:30 +0000 (12:06 -0800)]
freedreno/ir3: also lower lowp frag outputs
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Rob Clark [Wed, 4 Mar 2020 19:54:26 +0000 (11:54 -0800)]
nir/print: show variable precision
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
Danylo Piliaiev [Tue, 10 Mar 2020 14:24:59 +0000 (16:24 +0200)]
intel/tools: Fix compilation with UBSan
Compilation failed with several similar errors:
../src/intel/tools/aub_read.c:322:4: error: case label does not reduce to an integer constant
322 | case MAKE_HEADER(TYPE_AUB, OPCODE_AUB, SUBOPCODE_HEADER):
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4132>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4132>
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