litex.git
11 years agobank/description: AutoReg
Sebastien Bourdeauducq [Sat, 9 Mar 2013 23:43:16 +0000 (00:43 +0100)]
bank/description: AutoReg

11 years agomigen/fhdl/autofragment: factorize
Sebastien Bourdeauducq [Sat, 9 Mar 2013 22:23:24 +0000 (23:23 +0100)]
migen/fhdl/autofragment: factorize

11 years agofhdl/autofragment: remove legacy functions
Sebastien Bourdeauducq [Sat, 9 Mar 2013 22:05:45 +0000 (23:05 +0100)]
fhdl/autofragment: remove legacy functions

11 years agofhdl/tools/flat_iteration: generalize
Sebastien Bourdeauducq [Sat, 9 Mar 2013 22:03:15 +0000 (23:03 +0100)]
fhdl/tools/flat_iteration: generalize

11 years agofhdl/autofragment: fix submodules
Sebastien Bourdeauducq [Sat, 9 Mar 2013 20:15:38 +0000 (21:15 +0100)]
fhdl/autofragment: fix submodules

11 years agofhdl/autofragment: empty build_fragment by default
Sebastien Bourdeauducq [Sat, 9 Mar 2013 18:10:47 +0000 (19:10 +0100)]
fhdl/autofragment: empty build_fragment by default

11 years agoUse common definition for FinalizeError
Sebastien Bourdeauducq [Sat, 9 Mar 2013 18:03:13 +0000 (19:03 +0100)]
Use common definition for FinalizeError

11 years agocsr/SRAM: support for writes with memory widths larger than bus words
Sebastien Bourdeauducq [Fri, 8 Mar 2013 23:50:57 +0000 (00:50 +0100)]
csr/SRAM: support for writes with memory widths larger than bus words

11 years agofhdl/verilog: tristate outputs are always wire
Sebastien Bourdeauducq [Wed, 6 Mar 2013 10:30:52 +0000 (11:30 +0100)]
fhdl/verilog: tristate outputs are always wire

11 years agobus/csr: support memories with larger word width than the bus (read only)
Sebastien Bourdeauducq [Sun, 3 Mar 2013 18:27:13 +0000 (19:27 +0100)]
bus/csr: support memories with larger word width than the bus (read only)

11 years agofhdl/autofragment: bugfixes + add auto_attr
Sebastien Bourdeauducq [Sun, 3 Mar 2013 16:53:06 +0000 (17:53 +0100)]
fhdl/autofragment: bugfixes + add auto_attr

11 years agofhdl/autofragment: FModule
Sebastien Bourdeauducq [Sat, 2 Mar 2013 22:30:54 +0000 (23:30 +0100)]
fhdl/autofragment: FModule

11 years agocsr/SRAM: prefix page register with memory name
Sebastien Bourdeauducq [Fri, 1 Mar 2013 11:06:12 +0000 (12:06 +0100)]
csr/SRAM: prefix page register with memory name

11 years agofhdl/verilog: insert reset before listing signals
Sebastien Bourdeauducq [Wed, 27 Feb 2013 17:10:04 +0000 (18:10 +0100)]
fhdl/verilog: insert reset before listing signals

11 years agobank/description: memprefix
Sebastien Bourdeauducq [Mon, 25 Feb 2013 22:14:15 +0000 (23:14 +0100)]
bank/description: memprefix

11 years agofhdl/specials: allow setting memory name
Sebastien Bourdeauducq [Mon, 25 Feb 2013 22:14:03 +0000 (23:14 +0100)]
fhdl/specials: allow setting memory name

11 years agouio/ioo: fix specials
Sebastien Bourdeauducq [Mon, 25 Feb 2013 22:13:38 +0000 (23:13 +0100)]
uio/ioo: fix specials

11 years agofhdl/specials/Instance: _printintbool -> verilog_printexpr
Sebastien Bourdeauducq [Sun, 24 Feb 2013 12:08:01 +0000 (13:08 +0100)]
fhdl/specials/Instance: _printintbool -> verilog_printexpr

11 years agoexamples/psync: cleanup
Sebastien Bourdeauducq [Sat, 23 Feb 2013 18:14:31 +0000 (19:14 +0100)]
examples/psync: cleanup

11 years agoexamples/basic/psync: demonstrate the new features
Sebastien Bourdeauducq [Sat, 23 Feb 2013 18:04:11 +0000 (19:04 +0100)]
examples/basic/psync: demonstrate the new features

11 years agogenlib: clock domain crossing elements
Sebastien Bourdeauducq [Sat, 23 Feb 2013 18:03:35 +0000 (19:03 +0100)]
genlib: clock domain crossing elements

11 years agofhdl/verilog: support special lowering and overrides
Sebastien Bourdeauducq [Sat, 23 Feb 2013 18:03:16 +0000 (19:03 +0100)]
fhdl/verilog: support special lowering and overrides

11 years agoexamples/fir: better filter
Sebastien Bourdeauducq [Fri, 22 Feb 2013 22:19:56 +0000 (23:19 +0100)]
examples/fir: better filter

11 years agocorelogic -> genlib
Sebastien Bourdeauducq [Fri, 22 Feb 2013 22:19:37 +0000 (23:19 +0100)]
corelogic -> genlib

11 years agofhdl: inline synthesis directive support
Sebastien Bourdeauducq [Fri, 22 Feb 2013 18:10:02 +0000 (19:10 +0100)]
fhdl: inline synthesis directive support

11 years agodoc: new 'specials' API
Sebastien Bourdeauducq [Fri, 22 Feb 2013 17:12:42 +0000 (18:12 +0100)]
doc: new 'specials' API

11 years agoNew 'specials' API
Sebastien Bourdeauducq [Fri, 22 Feb 2013 16:56:35 +0000 (17:56 +0100)]
New 'specials' API

11 years agodoc: tristates
Sebastien Bourdeauducq [Tue, 19 Feb 2013 16:52:57 +0000 (17:52 +0100)]
doc: tristates

11 years agofhdl: TSTriple
Sebastien Bourdeauducq [Tue, 19 Feb 2013 16:26:02 +0000 (17:26 +0100)]
fhdl: TSTriple

11 years agofhdl: tristate support
Sebastien Bourdeauducq [Thu, 14 Feb 2013 23:17:24 +0000 (00:17 +0100)]
fhdl: tristate support

11 years agofhdl/autofragment: from_attributes
Sebastien Bourdeauducq [Mon, 11 Feb 2013 17:34:01 +0000 (18:34 +0100)]
fhdl/autofragment: from_attributes

11 years agodoc: fix signal desc layout
Sebastien Bourdeauducq [Sun, 10 Feb 2013 18:39:18 +0000 (19:39 +0100)]
doc: fix signal desc layout

11 years agoMerge branch 'master' of github.com:milkymist/migen
Sebastien Bourdeauducq [Sun, 10 Feb 2013 18:03:32 +0000 (19:03 +0100)]
Merge branch 'master' of github.com:milkymist/migen

11 years agodoc/dataflow: remove ActorNode
Sebastien Bourdeauducq [Sun, 10 Feb 2013 18:03:18 +0000 (19:03 +0100)]
doc/dataflow: remove ActorNode

11 years agodoc/dataflow: remove ALA
Sebastien Bourdeauducq [Sun, 10 Feb 2013 17:57:03 +0000 (18:57 +0100)]
doc/dataflow: remove ALA

11 years agodoc: multiple clock domains
Sebastien Bourdeauducq [Sun, 10 Feb 2013 17:56:45 +0000 (18:56 +0100)]
doc: multiple clock domains

11 years agodoc: do not inline examples as this never works with most Sphinx setups ...
Sebastien Bourdeauducq [Sun, 10 Feb 2013 17:45:06 +0000 (18:45 +0100)]
doc: do not inline examples as this never works with most Sphinx setups ...

11 years agodoc: update to new Migen APIs
Sebastien Bourdeauducq [Sun, 10 Feb 2013 17:42:47 +0000 (18:42 +0100)]
doc: update to new Migen APIs

11 years agosim: default runner to Icarus Verilog
Sebastien Bourdeauducq [Sat, 9 Feb 2013 16:04:53 +0000 (17:04 +0100)]
sim: default runner to Icarus Verilog

11 years agoflow/perftools: finish removing ActorNode
Sebastien Bourdeauducq [Sat, 9 Feb 2013 16:03:48 +0000 (17:03 +0100)]
flow/perftools: finish removing ActorNode

11 years agofhdl/structure: store clock domain name
Sebastien Bourdeauducq [Thu, 24 Jan 2013 12:49:49 +0000 (13:49 +0100)]
fhdl/structure: store clock domain name

11 years agofhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()
Sebastien Bourdeauducq [Wed, 23 Jan 2013 14:13:06 +0000 (15:13 +0100)]
fhdl/verilog: fix spurious clock/reset signals on multiple calls to convert()

11 years agocorelogic: complex arithmetic support
Sebastien Bourdeauducq [Sat, 5 Jan 2013 13:18:36 +0000 (14:18 +0100)]
corelogic: complex arithmetic support

11 years agofhdl: support nested statement lists
Sebastien Bourdeauducq [Sat, 5 Jan 2013 13:18:15 +0000 (14:18 +0100)]
fhdl: support nested statement lists

11 years agopytholite: fix bug with constant assignment to register
Sebastien Bourdeauducq [Wed, 19 Dec 2012 15:21:57 +0000 (16:21 +0100)]
pytholite: fix bug with constant assignment to register

11 years agopytholite: prune unused registers
Sebastien Bourdeauducq [Wed, 19 Dec 2012 15:03:05 +0000 (16:03 +0100)]
pytholite: prune unused registers

11 years agoDo not use super()
Sebastien Bourdeauducq [Tue, 18 Dec 2012 13:54:33 +0000 (14:54 +0100)]
Do not use super()

11 years agoexamples/pytholite: fix imports
Sebastien Bourdeauducq [Sun, 16 Dec 2012 19:26:23 +0000 (20:26 +0100)]
examples/pytholite: fix imports

11 years agofhdl/tools: bitreverse
Sebastien Bourdeauducq [Fri, 14 Dec 2012 22:56:16 +0000 (23:56 +0100)]
fhdl/tools: bitreverse

11 years agoactorlib/sim/SimActor: do not drive busy low when generator yields None
Sebastien Bourdeauducq [Fri, 14 Dec 2012 22:56:03 +0000 (23:56 +0100)]
actorlib/sim/SimActor: do not drive busy low when generator yields None

11 years agoToken: support idle_wait
Sebastien Bourdeauducq [Fri, 14 Dec 2012 18:16:22 +0000 (19:16 +0100)]
Token: support idle_wait

11 years agoMove Token to migen.flow.transactions
Sebastien Bourdeauducq [Fri, 14 Dec 2012 14:55:38 +0000 (15:55 +0100)]
Move Token to migen.flow.transactions

11 years agoreplace some forgotten is_abstract()
Sebastien Bourdeauducq [Wed, 12 Dec 2012 21:36:45 +0000 (22:36 +0100)]
replace some forgotten is_abstract()

11 years agoRemove ActorNode
Sebastien Bourdeauducq [Wed, 12 Dec 2012 21:20:48 +0000 (22:20 +0100)]
Remove ActorNode

11 years agoMerge branch 'master' of github.com:milkymist/migen
Sebastien Bourdeauducq [Thu, 6 Dec 2012 19:57:30 +0000 (20:57 +0100)]
Merge branch 'master' of github.com:milkymist/migen

11 years agofhdl/structure: do not create Signal in Instance when parameter is int
Sebastien Bourdeauducq [Thu, 6 Dec 2012 19:56:46 +0000 (20:56 +0100)]
fhdl/structure: do not create Signal in Instance when parameter is int

11 years agoelsewhere: do not create interface in default param
Sebastien Bourdeauducq [Thu, 6 Dec 2012 16:34:48 +0000 (17:34 +0100)]
elsewhere: do not create interface in default param

11 years agomigen/bank: do not create interface in default param
Sebastien Bourdeauducq [Thu, 6 Dec 2012 16:28:28 +0000 (17:28 +0100)]
migen/bank: do not create interface in default param

11 years agobus/csr: add SRAM
Sebastien Bourdeauducq [Thu, 6 Dec 2012 16:16:17 +0000 (17:16 +0100)]
bus/csr: add SRAM

11 years agobank/csrgen: interface -> bus
Sebastien Bourdeauducq [Thu, 6 Dec 2012 16:15:34 +0000 (17:15 +0100)]
bank/csrgen: interface -> bus

11 years agobank/description: define reset value of read signal
Sebastien Bourdeauducq [Wed, 5 Dec 2012 15:40:44 +0000 (16:40 +0100)]
bank/description: define reset value of read signal

11 years agoactorlib/sim: drive busy high until generator is finished
Sebastien Bourdeauducq [Wed, 5 Dec 2012 15:40:12 +0000 (16:40 +0100)]
actorlib/sim: drive busy high until generator is finished

11 years agobus/wishbone/sram: accept memories < 32 bits
Sebastien Bourdeauducq [Sat, 1 Dec 2012 12:04:22 +0000 (13:04 +0100)]
bus/wishbone/sram: accept memories < 32 bits

11 years agobus/wishbone: add SRAM
Sebastien Bourdeauducq [Sat, 1 Dec 2012 11:59:09 +0000 (12:59 +0100)]
bus/wishbone: add SRAM

12 years agopytholite: fix bit width of selection signal
Sebastien Bourdeauducq [Fri, 30 Nov 2012 16:07:32 +0000 (17:07 +0100)]
pytholite: fix bit width of selection signal

12 years agopytholite: support signed registers
Sebastien Bourdeauducq [Fri, 30 Nov 2012 16:07:12 +0000 (17:07 +0100)]
pytholite: support signed registers

12 years agocorelogic/roundrobin: fix request width (again)
Sebastien Bourdeauducq [Thu, 29 Nov 2012 22:47:51 +0000 (23:47 +0100)]
corelogic/roundrobin: fix request width (again)

12 years agocorelogic/roundrobin: fix request width
Sebastien Bourdeauducq [Thu, 29 Nov 2012 22:47:08 +0000 (23:47 +0100)]
corelogic/roundrobin: fix request width

12 years agoFix various errors from new bitwidth/signedness system conversion
Sebastien Bourdeauducq [Thu, 29 Nov 2012 22:36:55 +0000 (23:36 +0100)]
Fix various errors from new bitwidth/signedness system conversion

12 years agofhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)
Sebastien Bourdeauducq [Thu, 29 Nov 2012 21:59:54 +0000 (22:59 +0100)]
fhdl/verilog: make signal behave as integers in arithmetic (MyHDL style)

See http://jandecaluwe.com/hdldesign/counting.html

12 years agofhdl/structure: add unary minus
Sebastien Bourdeauducq [Thu, 29 Nov 2012 21:52:57 +0000 (22:52 +0100)]
fhdl/structure: add unary minus

12 years agoReplace Signal(bits_for(... with Signal(max=...
Sebastien Bourdeauducq [Thu, 29 Nov 2012 20:53:36 +0000 (21:53 +0100)]
Replace Signal(bits_for(... with Signal(max=...

12 years agoNew specification for width and signedness
Sebastien Bourdeauducq [Thu, 29 Nov 2012 20:22:38 +0000 (21:22 +0100)]
New specification for width and signedness

12 years agoRefactor Case
Sebastien Bourdeauducq [Thu, 29 Nov 2012 00:11:15 +0000 (01:11 +0100)]
Refactor Case

12 years agopytholite/reg: use source id in dictionary
Sebastien Bourdeauducq [Wed, 28 Nov 2012 23:09:35 +0000 (00:09 +0100)]
pytholite/reg: use source id in dictionary

12 years agoRemove Constant
Sebastien Bourdeauducq [Wed, 28 Nov 2012 22:18:43 +0000 (23:18 +0100)]
Remove Constant

12 years agoexamples/sim/dataflow: update to new APIs
Sebastien Bourdeauducq [Wed, 28 Nov 2012 21:44:14 +0000 (22:44 +0100)]
examples/sim/dataflow: update to new APIs

12 years agoexamples/dataflow/dma: update to new APIs
Sebastien Bourdeauducq [Wed, 28 Nov 2012 21:42:01 +0000 (22:42 +0100)]
examples/dataflow/dma: update to new APIs

12 years agoexamples/basic: remove unroll example
Sebastien Bourdeauducq [Wed, 28 Nov 2012 21:16:02 +0000 (22:16 +0100)]
examples/basic: remove unroll example

12 years agofhdl/structure: improved bits_for function
Sebastien Bourdeauducq [Wed, 28 Nov 2012 17:39:44 +0000 (18:39 +0100)]
fhdl/structure: improved bits_for function

12 years agovisit/NodeTransformer: copy most nodes
Sebastien Bourdeauducq [Wed, 28 Nov 2012 16:50:55 +0000 (17:50 +0100)]
visit/NodeTransformer: copy most nodes

12 years agofhdl/tools: use NodeTransformer to lower arrays
Sebastien Bourdeauducq [Wed, 28 Nov 2012 16:46:15 +0000 (17:46 +0100)]
fhdl/tools: use NodeTransformer to lower arrays

12 years agoexamples/basic/arrays: add array assignment to fragment
Sebastien Bourdeauducq [Mon, 26 Nov 2012 21:47:35 +0000 (22:47 +0100)]
examples/basic/arrays: add array assignment to fragment

12 years agofhdl/tools: use NodeVisitor
Sebastien Bourdeauducq [Mon, 26 Nov 2012 20:40:23 +0000 (21:40 +0100)]
fhdl/tools: use NodeVisitor

12 years agoRemove unroll
Sebastien Bourdeauducq [Mon, 26 Nov 2012 19:07:48 +0000 (20:07 +0100)]
Remove unroll

12 years agofhdl/structure: remove deprecated MemoryPort
Sebastien Bourdeauducq [Mon, 26 Nov 2012 18:36:43 +0000 (19:36 +0100)]
fhdl/structure: remove deprecated MemoryPort

12 years agobus/wishbone2asmi: do not use MemoryPort
Sebastien Bourdeauducq [Mon, 26 Nov 2012 18:14:59 +0000 (19:14 +0100)]
bus/wishbone2asmi: do not use MemoryPort

12 years agoactorlib/spi: do not use MemoryPort
Sebastien Bourdeauducq [Mon, 26 Nov 2012 17:27:59 +0000 (18:27 +0100)]
actorlib/spi: do not use MemoryPort

12 years agoexamples/sim/memory: do not use MemoryPort
Sebastien Bourdeauducq [Mon, 26 Nov 2012 17:19:10 +0000 (18:19 +0100)]
examples/sim/memory: do not use MemoryPort

12 years agoactorlib/sim: Dumper
Sebastien Bourdeauducq [Fri, 23 Nov 2012 23:00:07 +0000 (00:00 +0100)]
actorlib/sim: Dumper

12 years agofhdl/structure: disable we_granularity when larger than width
Sebastien Bourdeauducq [Fri, 23 Nov 2012 22:08:12 +0000 (23:08 +0100)]
fhdl/structure: disable we_granularity when larger than width

12 years agosim/generic/multiread: do not return spurious items
Sebastien Bourdeauducq [Fri, 23 Nov 2012 22:07:25 +0000 (23:07 +0100)]
sim/generic/multiread: do not return spurious items

12 years agopytholite: fix import of _Slice
Sebastien Bourdeauducq [Fri, 23 Nov 2012 20:20:18 +0000 (21:20 +0100)]
pytholite: fix import of _Slice

12 years agopytholite/io: support memory
Sebastien Bourdeauducq [Fri, 23 Nov 2012 19:36:09 +0000 (20:36 +0100)]
pytholite/io: support memory

12 years agofhdl/structure/Memory: fix we width
Sebastien Bourdeauducq [Fri, 23 Nov 2012 18:21:52 +0000 (19:21 +0100)]
fhdl/structure/Memory: fix we width

12 years agoexamples/memory: use new get_port API
Sebastien Bourdeauducq [Fri, 23 Nov 2012 18:18:08 +0000 (19:18 +0100)]
examples/memory: use new get_port API

12 years agofhdl/structure: add Memory.get_port API
Sebastien Bourdeauducq [Fri, 23 Nov 2012 18:17:49 +0000 (19:17 +0100)]
fhdl/structure: add Memory.get_port API

12 years agofhdl: use object creation counter (HUID) as hash. This finally makes the generated...
Sebastien Bourdeauducq [Fri, 23 Nov 2012 17:38:03 +0000 (18:38 +0100)]
fhdl: use object creation counter (HUID) as hash. This finally makes the generated code textually the same across runs.

12 years agofhdl/structure: use sets for memories and instance collections
Sebastien Bourdeauducq [Fri, 23 Nov 2012 16:20:08 +0000 (17:20 +0100)]
fhdl/structure: use sets for memories and instance collections

12 years agoexamples/pytholite/uio: demonstrate memories
Sebastien Bourdeauducq [Fri, 23 Nov 2012 15:24:20 +0000 (16:24 +0100)]
examples/pytholite/uio: demonstrate memories