i965: Add missing BRW_NEW_FS_PROG_DATA to render target reads.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Move BRW_NEW_FRAGMENT_PROGRAM from 3DSTATE_PS to PS_EXTRA.

3DSTATE_PS doesn't need this.  3DSTATE_PS_EXTRA however does,
for brw_color_buffer_write_enabled().

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Add missing BRW_NEW_VS_PROG_DATA to 3DSTATE_CLIP.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Fix missing _NEW_TRANSFORM in Gen8+ 3DSTATE_DS atom.

Needed for user clip plane enables.  Broken since this code was
introduced.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965: Enable ARB_shader_atomic_counter_ops

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: Refactor emission of atomic counter operations

This will make it easier to add more operations.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

nir/intrinsics: Add more atomic_counter ops

v2: Delete some stray debug code notice by Iago.

v3: Massive rebase on new ir_function_signature::intrinsic_id mechanism.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> [v1]
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

nir/intrinsics: Include atomic_counter_ in the names used in macro invocations

Otherwise grepping for where atomic_counter_inc and friends are defined
is a very frustrating experience.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: Kill __intrinsic_atomic_sub

Just generate an __intrinsic_atomic_add with a negated parameter.

Some background on the non-obvious reasons for the the big change to
builtin_builder::call()... this is cribbed from some discussion with
Ilia on mesa-dev.

Why change builtin_builder::call() to allow taking dereferences and
create them here rather than just feeding in the ir_variables directly?
The problem is the neg_data ir_variable node would have to be in two
lists at the same time: the instruction stream and parameters.  The
ir_variable node is automatically added to the instruction stream by the
call to make_temp.  Restructuring the code so that the ir_variables
could be in parameters then move them to the instruction stream would
have been pretty terrible.

ir_call in the instruction stream has an exec_list that contains
ir_dereference_variable nodes.

The builtin_builder::call method previously took an exec_list of
ir_variables and created a list of ir_dereference_variable.  All of the
original users of that method wanted to make a function call using
exactly the set of parameters passed to the built-in function (i.e.,
call __intrinsic_atomic_add using the parameters to atomicAdd).  For
these users, the list of ir_variables already existed:  the list of
parameters in the built-in function signature.

This new caller doesn't do that.  It wants to call a function with a
parameter from the function and a value calculated in the function.  So,
I changed builtin_builder::call to take a list that could either be a
list of ir_variable or a list of ir_dereference_variable.  In the former
case it behaves just as it previously did.  In the latter case, it uses
(and removes from the input list) the ir_dereference_variable nodes
instead of creating new ones.

   text    data     bss     dec     hex filename
6036395  283160   28608 6348163  60dd83 lib64/i965_dri.so before
6036923  283160   28608 6348691  60df93 lib64/i965_dri.so after

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: Remove ir_function_signature::_is_intrinsic field

   text    data     bss     dec     hex filename
6036491  283160   28608 6348259  60dde3 lib64/i965_dri.so before
6036395  283160   28608 6348163  60dd83 lib64/i965_dri.so after

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: Add ir_function_signature::is_intrinsic() method

This necessetated renaming the is_intrinsic field to _is_intrinsic.  The
next commit will remove the field.

   text    data     bss     dec     hex filename
6036507  283160   28608 6348275  60ddf3 lib64/i965_dri.so before
6036491  283160   28608 6348259  60dde3 lib64/i965_dri.so after

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: Use the ir_intrinsic_* enums instead of the __intrinsic_* name strings

   text    data     bss     dec     hex filename
6038043  283160   28608 6349811  60e3f3 lib64/i965_dri.so before
6036507  283160   28608 6348275  60ddf3 lib64/i965_dri.so after

v2: s/ir_intrinsic_atomic_sub/ir_intrinsic_atomic_counter_sub/.  Noticed
by Ilia.

v3: Silence unhandled enum in switch warnings in st_glsl_to_tgsi.

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: Track a unique intrinsic ID with each intrinsic function

   text    data     bss     dec     hex filename
6037483  283160   28608 6349251  60e1c3 lib64/i965_dri.so before
6038043  283160   28608 6349811  60e3f3 lib64/i965_dri.so after

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: Don't emit ir_binop_carry during ir_binop_imul_high lowering

st_glsl_to_tgsi only calls lower_instructions once (instead of in a
loop), so the ir_binop_carry generated would not get lowered.  Fixes
assertion failure

state_tracker/st_glsl_to_tgsi.cpp:2265: void glsl_to_tgsi_visitor::visit_expression(ir_expression*, st_src_reg*): Assertion `!"Invalid ir opcode in glsl_to_tgsi_visitor::visit()"' failed.

on softpipe in 16 piglit tests:

    mesa_shader_integer_functions/execution/built-in-functions/fs-imulExtended-nonuniform.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/fs-imulExtended-only-msb-nonuniform.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/fs-imulExtended-only-msb.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/fs-imulExtended.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/fs-umulExtended-nonuniform.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/fs-umulExtended-only-msb-nonuniform.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/fs-umulExtended-only-msb.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/fs-umulExtended.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/vs-imulExtended-nonuniform.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/vs-imulExtended-only-msb-nonuniform.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/vs-imulExtended-only-msb.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/vs-imulExtended.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/vs-umulExtended-nonuniform.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/vs-umulExtended-only-msb-nonuniform.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/vs-umulExtended-only-msb.shader_test
    mesa_shader_integer_functions/execution/built-in-functions/vs-umulExtended.shader_test

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

i965: fix unused variable warning in brw_emit_gpgpu_walker()

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: add MAYBE_UNUSED to assert param

Fixes unused variable warning in release build.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: wrap unused function in #ifndef NDEBUG

This function is only ever used by an assert() this fixes an
unused function warning in release builds.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: fix unused variable warning in gen7_block_read_scratch()

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: add MAYBE_UNUSED to assert param

This fixes an unused variable warning on release builds.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

gallivm: Use AVX2 gather instrinsics.

v2: Use AVX2 gather for non aligned loads too.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

gallivm: Use 8 wide AoS sampling on AVX2.

v2: Make sure that with num_lods > 1 and min_filter != mag_filter we
still enter the splitting path. So this case would still use 4-wide aos
path (as a side note, the 4-wide aos sampling path could actually be
improved quite a bit if we have avx2, by just doing the filtering with
256bit vectors).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

gallivm: Basic AVX2 support.

v2: pblendb -> pblendvb

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

egl: Drop duplicate check on EGLSync type

_eglInitSync checked that the display supported the sync type (such as
EGL_SYNC_FENCE), and did it wrong. When the check failed it emitted
EGL_BAD_ATTRIBUTE, but sometimes EGL_BAD_PARAMETER is needed.

_eglCreateSync already does the error checking, and it does it right.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: Cleanup control flow in _eglParseSyncAttribList

When the function encountered an error, it effectively returned
immediately. However, it did so indirectly by breaking out of a loop.
Replace the loop breakout with a explicit 'return'.

Do the same for _eglParseSyncAttribList64 too.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: Add _eglConvertIntsToAttribs()

This function converts an attribute list from EGLint[] to EGLAttrib[].
Will be used in following patches to cleanup EGLSync attribute parsing.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: Fix an error path in eglCreateSync*

When the user called eglCreateSync64KHR on a display without
EGL_KHR_cl_event2 (the only extension that exposes it), we returned
EGL_NO_SYNC but did not update the error code.

We also did the same for eglCreateSync on a display without EGL 1.5.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: Fix truncation error in _eglParseSyncAttribList64

The function stores EGLAttrib values in EGLint variables. On 64-bit
systems, this truncated the values.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

egl: Fix missing unlock in eglGetSyncAttribKHR

On the error path, eglGetSyncAttribKHR neglected to unlock the
EGLDisplay before returning.

Fixes deadlock in dEQP-EGL.functional.fence_sync.invalid.get_invalid_value.

Cc: mesa-stable@lists.freedesktop.org
Cc: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

anv/gen7_pipeline: Fix typo in semicolon

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/gen7_pipeline: Set sample mask field in 3DSTATE_PS

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/gen7_pipeline: Move ksp{1,2} state setting next to ksp0

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/gen7: Make use of local variable prog_data

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/gen8_pipeline: Add an assert to ensure use_alt_mode is not set in prog_data

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>

anv/gen8_pipeline: Fix typo in semicolon

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Keep the value name 'Alternate' uniform across gen75.xml

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/genxml: Fix typo in gen75.xml

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

i965/gen8+: Enable GL_OES_viewport_array

This patch causes 2 regressions in khronos' gles cts tests
on various intel platforms.
Failing tests:
ES3-CTS.functional.state_query.integers.viewport_getinteger
ES3-CTS.functional.state_query.integers.viewport_getfloat

Here is an explanation of what's causing the failures:

CTS tests are not clamping the x, y location of the viewport's
bottom-left corner as recommended by ARB_viewport_array and
OES_viewport_array:
"The location of the viewport's bottom-left corner, given by (x,y), are
 clamped to be within the implementation-dependent viewport bounds range.
 The viewport bounds range [min, max] tuple may be determined by
 calling GetFloatv with the symbolic constant VIEWPORT_BOUNDS_RANGE_OES"

Khronos CTS merge request to fix the test case:
https://gitlab.khronos.org/opengl/cts/merge_requests/399

V2: Initialize the relevant variables for GL_OES_viewport_array on gen8+

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa: Add a check for OES_viewport_array

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa: Enable enums for OES_viewport_array

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

anv/gen7_pipeline: Use MSDISPMODE_PERSAMPLE for non-multisampled fbo

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv/blorp: Handle zero width/height blits in blorp_copy()

V2: Move the check from copy_buffer_to_image() to blorp_copy(). (Nanley)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/isl: Add an assert to check zero width/height surface

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

st/omx/dec/h265: add scaling list data

Specified by subclause 7.3.4

v2: get the loop optimized

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/omx/dec/h265: fix the skip for before and after list

For reference picture sets, there are cases that rps will not always
be used. Once detect the unused flag from encoded bitstream, we should
not add this rps to any list, otherwise pass the incorrect reference
and skip the correct rps.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

st/omx/dec/h265: set the default reference picture set for reference

It will fix the corruption for frame, that only has one stort term ref
picture set, we set NULL rps for this case previously, causing taking
incorrect reference. Instead we should take that only short term set
as reference

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

st/omx/dec/h265: decoder size should follow from sps

The video size from format container is not always compatible with
the size from codec bitstream, the HW decoder should take the size
information from bitstream, otherwise the corruption appears with clip
that has different size info between bitstream and format container

So we are passing width(height)_in_samples from sequence parameter
set to video decoder.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

st/omx/dec/h265: increase dpb max size to 32

For clip with frame delta poc over 16

Signed-off-by: Leo Liu <leo.liu@amd.com>

nir/spirv: Remove a duplicate spirv2nir from .gitignore

This reverts commit fc03ecfeaf5a10a8b84d366f24f02e74ab03b145.

Chad had already pushed the same change between me posting the patch and Jason
pushing it: 44bcf1ffcced04fd7f2b (".gitignore: Ignore src/compiler/spirv2nir")

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radeonsi: optionally run the LLVM IR verifier pass

This is enabled automatically if shader printing is enabled, or separately
by R600_DEBUG=checkir. Catch mal-formed IR before it crashes in a later
pass.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: fix argument type of llvm.{cttz,ctlz}.i32 intrinsics

Caught by R600_DEBUG=checkir (next commit).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: unify the creation of basic blocks

This changes the order of basic blocks to be equal to the order of code in the
original TGSI, which is nice for making sense of shader dumps.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: merge branch and loop flow control stacks

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: simplify if/else/endif blocks

In particular, we no longer emit an else block when there is no ELSE
instruction.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: label basic blocks by the corresponding TGSI pc

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium/radeon: cleanup and fix branch emits

Some of the existing code is needlessly complicated. The basic principle
should be: control-flow opcodes emit branches to properly terminate the
current block, _unless_ the current block already has a terminator (which
happens if and only if there was a BRK or CONT).

This also fixes a bug where multiple terminators were created in a block.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97887
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

winsys/radeon: add buffer_get_reloc_offset

Really fix the bug that was supposed to be fixed by commits 3e7cced4b and
a48bf02d: even when virtual addresses are used, the legacy relocation-based
method with offsets relative to the kernel's buffer object are used for
video submissions.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97969
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: don't declare LDS in PS when ds_bpermute is used

I guess this is not needed because dead code elimination removes
the declaration.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: use DDX/DDY directly in si_llvm_emit_ddxy_interp

We can finally do this, because the opcodes are scalar now.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: simplify si_llvm_emit_ddxy

si_llvm_emit_ddxy is called once per element, so we don't have to generate
code for 4 elements at once.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: don't call build_gep0 in si_llvm_emit_ddxy on VI

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: use a helper function for BuildGEP(0, x)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: remove obsolete shader definitions

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: remove unnecessary #includes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: clean up lucky #include dependencies

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: don't re-create shader PM4 states after scratch buffer update

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

gallium/radeon: move r600_common_context::texture_buffers to r600g

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: don't set sampler buffer offsets in create_sampler_view

do it at bind time, so that pipe_sampler_view is immutable with regard to
buffer reallocations and we don't have to remember all existing buffer
views.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: optimize si_invalidate_buffer based on bind_history

Just enclose each section with: if (rbuffer->bind_history & PIPE_BIND_...)

Bioshock Infinite: +1% performance

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: track buffer bind history

similar to gl_buffer_object::UsageHistory

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: drop support for NULL sampler views

not used anymore. It was used when the polygon stipple texture was constant.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: separate IA_MULTI_VGT_PARAM and VGT_PRIMITIVE_TYPE emission

We want to emit IA_MULTI_VGT_PARAM less often because it's a context reg.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: move VGT_LS_HS_CONFIG to derived tess_state

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: don't check PIPE_BARRIER_MAPPED_BUFFER

Caches are always flushed at IB boundary.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: parse SURFACE_SYNC correctly on CIK-VI

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

gallium/radeon: inline r600_context_add_resource_size

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>

radeonsi: Fix primitive restart when index changes

If primitive restart is enabled for two consecutive draws which use
different primitive restart indices, then the first draw's primitive
restart index was incorrectly used for the second draw.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98025

Cc: 11.1 11.2 12.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>

spirv: replace assert() with unreachable()

This fixes an uninitialized warning for is_vertex_input.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel: use the correct format specifier for printing uint64_t

Fixes a bunch of warnings in 32-bit builds.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

gallium/winsys: replace calls to dup(2) with fcntl(F_DUPFD_CLOEXEC)

Without this fix, duplicated file descriptors leak into child processes.
See commit aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/xa: replace call to dup(2) with fcntl(F_DUPFD_CLOEXEC)

Without this fix, duplicated file descriptors leak into child processes.
See commit aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/dri: replace calls to dup(2) with fcntl(F_DUPFD_CLOEXEC)

Without this fix, duplicated file descriptors leak into child processes.
See commit aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/auxiliary: replace call to dup(2) with fcntl(F_DUPFD_CLOEXEC)

Without this fix, duplicated file descriptors leak into child processes.
See commit aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

egl/android: replace call to dup(2) with fcntl(F_DUPFD_CLOEXEC)

Without this fix, duplicated file descriptors leak into child processes.
See commit aaac913e901229d11a1894f6aaf646de6b1a542c for one instance
where the same fix was employed.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Matt Whitlock <freedesktop@mattwhitlock.name>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

intel: fix compilation warning on gen_get_device_info

(warning: 'const' type qualifier on return type has no effect)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

i965: Only emit 1 viewport when possible.

In core profile, we support up to 16 viewports.  However, in the
majority of cases, only 1 of them is actually used - we only need
the others if the last shader stage prior to the rasterizer writes
gl_ViewportIndex.

Processing all 16 viewports adds additional CPU overhead, which hurts
CPU-intensive workloads such as Glamor.  This meant that switching to
core profile actually penalized Glamor to an extent, which is
unfortunate.

This patch tracks the number of relevant viewports, switching between
1 and ctx->Const.MaxViewports if gl_ViewportIndex is written.  A new
BRW_NEW_VIEWPORT_COUNT flag tracks this.  This could mean re-emitting
viewport state when switching, but hopefully this is offset by doing
1/16th of the work in the common case.  The new flag is also lighter
weight than BRW_NEW_VUE_MAP_GEOM_OUT, which we were using in one case.

According to Eric Anholt, x11perf -copypixwin10 performance improves by
11.5094% +/- 3.10841% (n=10) on his Skylake.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Anuj Phogat <anuj.phogat@gmail.com>

spirv: translate cull distance semantic.

This just translates to the correct cull distance slot.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

compiler: add printable values for cull distance varyings.

We need these for spir-v/nir shaders.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>

nir/spirv/cfg: Use a nop intrinsic for tagging the ends of blocks

Previously, we were saving off the last nir_block in a vtn_block before
moving on so that we could find the nir_block again when it came time to
handle phi sources.  Unfortunately, NIR's control flow modification code is
inconsistent when it comes to how it splits blocks so the block pointer we
saved off may point to a block somewhere else in the shader by the time we
get around to handling phi sources.  In order to get around this, we insert
a nop instruction and use that as the logical end of our block.  Since the
control flow manipulation code respects instructions, the nop will keeps
its place like any other instruction and we can easily find the end of our
block when we need it.

This fixes a bug triggered by a couple of vkQuake shaders.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97233
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Tested-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir: Add a nop intrinsic

This intrinsic has no destination, no sources, no variables, and can be
eliminated.  In other words, it does nothing and will always get deleted by
dead code elimination.  However, it does provide a quick-and-easy way to
temporarily tag a particular location in a NIR shader.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>

intel/isl: Allow non-2D HiZ surfaces

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/isl: Add a detailed comment about multisampling with HiZ

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/isl: Remove tiling checks from choose_msaa_layout

We already do those checks in filter_tiling.  There's no good reason to
repeat them in choose_msaa_layout.  If anything they should have been
asserts and not "return false" checks.  Also, this check was causing us to
outright reject multisampled HiZ surfaces which wasn't intended.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/isl: Handle HiZ and CCS tiling more directly

The HiZ and CCS tiling formats are always used for HiZ and CCS surfaces
respectively.  There's no reason why we should go through filter_tiling and
it's much easier to always get HiZ and CCS right if we just handle them
directly.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/isl: Allow multisampling with ISL_FORMAT_HiZ

HiZ buffers can be multisampled and, on Broadwell and earlier, simply using
interleaved multisampling with a compression block size of 8x4 samples
yields the correct HiZ surface size calculations.  Unfortunately,
choose_msaa_layout was rejecting multisampled HiZ buffers because of format
checks.  Now that we have a simple helper for determining if a format
supports multisampling, that's an easy enough issue to fix.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/isl: Allow creation of 1-D compressed textures

Compressed 1-D textures are not well-defined thing in either GL or Vulkan.
However, auxiliary surfaces are treated as compressed textures in ISL and
we can do HiZ and CCS with 1-D so we need to be able to create them.  In
order to prevent actually using them (the docs say no), we assert in the
state setup code.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/isl: Fix up asserts in calc_phys_level0_extent_sa

The assertion that a format is uncompressed in the multisample layouts
isn't quite right.  What we really want to assert is that the format
supports multisampling which is a bit more complicated query.  We also want
to assert that it has a block size of 1x1 since we do nothing with the
block size in the phys_level0_sa assignment.

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

intel/isl: Add a format_supports_multisampling helper

Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>

vl/dri3: fix warning about incompatible pointer type

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

swr: Removed stalling SwrWaitForIdle from queries.

Previous fundamental change in stats gathering added a temporary
SwrWaitForIdle to begin_query and end_query.  Code has been reworked to
remove stall.

Reviewed-by: George Kyriazis <george.kyriazis@intel.com>

swr: [rasterizer core] refactor thread creation

Create worker pool now computes number of worker threads based on
things like topologies, etc. and creates the pool but doesn't actually
launch the threads. Instead there is a separate start thread pool
function. This allows thread resources to be constructed first before
threads start.

Signed-off-by: Tim Rowley <timothy.o.rowley@intel.com>