libgo: don't copy semt into runtime.inc

    https://gcc.gnu.org/PR81449 reports a problem with the definition semt
    in runtime.inc on some systems. Since the C code in libgo/runtime
    doesn't need semt, just don't copy it into runtime.inc.

    Reviewed-on: https://go-review.googlesource.com/48593

From-SVN: r250217

cmd/go: use gccSupportsFlag for -fsplit-stack

    Don't assume that all (or only) 386/amd64 compilers support
    -fsplit-stack.

    Reviewed-on: https://go-review.googlesource.com/48592

From-SVN: r250216

rs6000-c.c (altivec_overloaded_builtins): Add array entries to represent __ieee128 versions of the scalar_test_data_class...

gcc/ChangeLog:

2017-07-14  Kelvin Nilsen  <kelvin@gcc.gnu.org>

* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
array entries to represent __ieee128 versions of the
scalar_test_data_class, scalar_test_neg, scalar_extract_exp,
scalar_extract_sig, and scalar_insert_exp built-in functions.
(altivec_resolve_overloaded_builtin): Add special case handling
for the __builtin_scalar_insert_exp function, as represented by
the P9V_BUILTIN_VEC_VSIEDP constant.
* config/rs6000/rs6000-builtin.def (VSEEQP): Add scalar extract
exponent support for __ieee128 argument.
(VSESQP): Add scalar extract signature support for __ieee128
argument.
(VSTDCNQP): Add scalar test negative support for __ieee128
argument.
(VSIEQP): Add scalar insert exponent support for __int128 argument
with __ieee128 result.
(VSIEQPF): Add scalar insert exponent support for __ieee128
argument with __ieee128 result.
(VSTDCQP): Add scalar test data class support for __ieee128
argument.
(VSTDCNQP): Add overload support for scalar test negative with
__ieee128 argument.
(VSTDCQP): Add overload support for scalar test data class
__ieee128 argument.
* config/rs6000/vsx.md (UNSPEC_VSX_SXSIG) Replace
UNSPEC_VSX_SXSIGDP.
(UNSPEC_VSX_SIEXPQP): New constant.
(xsxexpqp): New insn for VSX scalar extract exponent quad
precision.
(xsxsigqp): New insn for VSX scalar extract significand quad
precision.
(xsiexpqpf): New insn for VSX scalar insert exponent quad
precision with floating point argument.
(xststdcqp): New expand for VSX scalar test data class quad
precision.
(xststdcnegqp): New expand for VSX scalar test negative quad
precision.
(xststdcqp): New insn to match expansions for VSX scalar test data
class quad precision and VSX scalar test negative quad precision.
* config/rs6000/rs6000.c (rs6000_expand_binop_builtin): Add
special case operand checking to enforce that second operand of
VSX scalar test data class with quad precision argument is a 7-bit
unsigned literal.
* doc/extend.texi (PowerPC AltiVec Built-in Functions): Add
prototypes and descriptions of __ieee128 versions of
scalar_extract_exp, scalar_extract_sig, scalar_insert_exp,
scalar_test_data_class, and scalar_test_neg built-in functions.

gcc/testsuite/ChangeLog:

2017-07-14  Kelvin Nilsen  <kelvin@gcc.gnu.org>

* gcc.target/powerpc/bfp/scalar-cmp-exp-eq-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-eq-4.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-gt-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-gt-4.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-lt-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-lt-4.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-3.c: New test.
* gcc.target/powerpc/bfp/scalar-cmp-exp-unordered-4.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-3.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-4.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-5.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-6.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-exp-7.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-3.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-4.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-5.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-6.c: New test.
* gcc.target/powerpc/bfp/scalar-extract-sig-7.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-10.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-11.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-12.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-13.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-14.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-15.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-6.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-7.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-8.c: New test.
* gcc.target/powerpc/bfp/scalar-insert-exp-9.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-10.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-11.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-12.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-13.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-14.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-15.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-8.c: New test.
* gcc.target/powerpc/bfp/scalar-test-data-class-9.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-4.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-5.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-6.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-7.c: New test.
* gcc.target/powerpc/bfp/scalar-test-neg-8.c: New test.
* gcc.target/powerpc/bfp/vec-extract-exp-4.c: New test.
* gcc.target/powerpc/bfp/vec-extract-exp-5.c: New test.
* gcc.target/powerpc/bfp/vec-extract-sig-4.c: New test.
* gcc.target/powerpc/bfp/vec-extract-sig-5.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-10.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-11.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-8.c: New test.
* gcc.target/powerpc/bfp/vec-insert-exp-9.c: New test.
* gcc.target/powerpc/bfp/vec-test-data-class-8.c: New test.
* gcc.target/powerpc/bfp/vec-test-data-class-9.c: New test.

From-SVN: r250214

Constrain std::variant constructor for class template argument deduction

2017-07-14  Jason Merrill  <jason@redhat.com>
    Jonathan Wakely  <jwakely@redhat.com>

* include/std/variant (variant::variant(_Tp&&)): Constrain to remove
the constructor for empty variants from the candidate functions
during class template argument deduction.
* testsuite/20_util/variant/deduction.cc: New.

Co-Authored-By: Jonathan Wakely <jwakely@redhat.com>
From-SVN: r250213

re PR tree-optimization/81162 (UBSAN switch triggers incorrect optimization in SLSR)

[gcc]

2016-07-14  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

PR tree-optimization/81162
* gimple-ssa-strength-reduction.c (replace_mult_candidate): Don't
replace a negate with an add.

[gcc/testsuite]

2016-07-14  Bill Schmidt  <wschmidt@linux.vnet.ibm.com>

PR tree-optimization/81162
* gcc.dg/pr81162.c: New file.

From-SVN: r250212

ssa-dse-30.c: Correct test to look for memmove that bcopy is expected to be transformed to.

gcc/testsuite/ChangeLog:

* gcc.dg/tree-ssa/ssa-dse-30.c: Correct test to look for memmove
that bcopy is expected to be transformed to.

From-SVN: r250209

[Patch ARM] Document the +crypto extension on CPUs.

We don't document the list of CPU names which can take a +crypto extension
in the ARM port. This patch fixes that oversight.

gcc/

2017-14-07  James Greenhalgh  <james.greenhalgh@arm.com>

* doc/invoke.texi (arm/-mcpu): Document +crypto.

From-SVN: r250207

[ARM] Fix definition of __ARM_FEATURE_NUMERIC_MAXMIN

Definition of __ARM_FEATURE_NUMERIC_MAXMIN checks for
TARGET_ARM_ARCH >= 8 and TARGET_NEON being true in addition to
TARGET_VFP5. However, instructions covered by this macro are part of
FPv5 which is available in ARMv7E-M architecture. This commit fixes the
macro to only check for TARGET_VFP5.

2017-07-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm-c.c (arm_cpu_builtins): Define
    __ARM_FEATURE_NUMERIC_MAXMIN solely based on TARGET_VFP5.

From-SVN: r250206

[ARM] Add support for ARM Cortex-R52 processor

2017-07-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm-cpus.in (cortex-r52): Add new entry.
    (armv8-r): Set ARM Cortex-R52 as default CPU.
    * config/arm/arm-tables.opt: Regenerate.
    * config/arm/arm-tune.md: Regenerate.
    * config/arm/driver-arm.c (arm_cpu_table): Add entry for ARM
    Cortex-R52.
    * doc/invoke.texi: Mention -mtune=cortex-r52 and availability of fp.dp
    extension for -mcpu=cortex-r52.

From-SVN: r250205

[ARM] Rewire -mfpu=fp-armv8 as VFPv5 + D32 + DP

fp-armv8 is currently defined as a double precision FPv5 with 32 D
registers *and* a special FP_ARMv8 bit. However FP for ARMv8 should only
bring 32 D registers on top of FPv5-D16 so this FP_ARMv8 bit is
spurious. As a consequence, many instruction patterns which are guarded
by TARGET_FPU_ARMV8 are unavailable to FPv5-D16 and FPv5-SP-D16.

This commit gets rid of TARGET_FPU_ARMV8 and rewire all uses to
expressions based on TARGET_VFP5, TARGET_VFPD32 and TARGET_VFP_DOUBLE.
It also redefine ISA_FP_ARMv8 to include the D32 capability to
distinguish it from FPv5-D16. At last, it sets the +fp.sp for ARMv8-R to
enable FPv5-SP-D16 (ie FP for ARMv8 with single precision only and 16 D
registers).

2017-07-14  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * config/arm/arm-isa.h (isa_bit_FP_ARMv8): Delete enumerator.
    (ISA_FP_ARMv8): Define as ISA_FPv5 and ISA_FP_D32.
    * config/arm/arm-cpus.in (armv8-r): Define fp.sp as enabling FPv5.
    (fp-armv8): Define it as FP_ARMv8 only.
    config/arm/arm.h (TARGET_FPU_ARMV8): Delete.
    (TARGET_VFP_FP16INST): Define using TARGET_VFP5 rather than
    TARGET_FPU_ARMV8.
    config/arm/arm.c (arm_rtx_costs_internal): Replace checks against
    TARGET_FPU_ARMV8 by checks against TARGET_VFP5.
    * config/arm/arm-builtins.c (arm_builtin_vectorized_function): Define
    first ARM_CHECK_BUILTIN_MODE definition using TARGET_VFP5 rather
    than TARGET_FPU_ARMV8.
    * config/arm/arm-c.c (arm_cpu_builtins): Likewise for
    __ARM_FEATURE_NUMERIC_MAXMIN macro definition.
    * config/arm/arm.md (cmov<mode>): Condition on TARGET_VFP5 rather than
    TARGET_FPU_ARMV8.
    * config/arm/neon.md (neon_vrint): Likewise.
    (neon_vcvt): Likewise.
    (neon_<fmaxmin_op><mode>): Likewise.
    (<fmaxmin><mode>3): Likewise.
    * config/arm/vfp.md (l<vrint_pattern><su_optab><mode>si2): Likewise.
    * config/arm/predicates.md (arm_cond_move_operator): Check against
    TARGET_VFP5 rather than TARGET_FPU_ARMV8 and fix spacing.

From-SVN: r250204

c/c++: Add fix-it hints for suggested missing #includes

gcc/c-family/ChangeLog:
* c-common.c (try_to_locate_new_include_insertion_point): New
function.
(per_file_includes_t): New typedef.
(added_includes_t): New typedef.
(added_includes): New variable.
(maybe_add_include_fixit): New function.
* c-common.h (maybe_add_include_fixit): New decl.

gcc/c/ChangeLog:
* c-decl.c (implicitly_declare): When suggesting a missing
#include, provide a fix-it hint.

gcc/cp/ChangeLog:
* name-lookup.c (get_std_name_hint): Add '<' and '>' around
the header names.
(maybe_suggest_missing_header): Update for addition of '<' and '>'
to above.  Provide a fix-it hint.
* pt.c: Include "gcc-rich-location.h"
(listify): Attempt to add fix-it hint for missing
#include <initializer_list>.
* rtti.c: Include "gcc-rich-location.h".
(typeid_ok_p): Attempt to add fix-it hint for missing
#include <typeinfo>.

gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/missing-initializer_list-include.C: New test case.
* g++.dg/lookup/missing-std-include-2.C: New test case.
* g++.dg/lookup/missing-std-include-3.C: New test case.
* g++.dg/rtti/missing-typeinfo-include.C: New test case.
* gcc.dg/missing-header-fixit-1.c: New test case.
* gcc.dg/missing-header-fixit-2.c: New test case.
* gcc.dg/missing-header-fixit-2.h: New header.

From-SVN: r250203

[Patch][Aarch64] Refactor comments in aarch64_print_operand

This patch refactors comments in config/aarch64/aarch64.c aarch64_print_operand
to provide a table of aarch64 specific formating options.

---
gcc/

2017-07-14  Jackson Woodruff  <jackson.woodruff@arm.com>

* config/aarch64/aarch64.c (aarch64_print_operand): Move comments
to top of function.

From-SVN: r250202

Update comment in gimple-ssa-store-merging.c

* gimple-ssa-store-merging.c (clear_bit_region): Replace reference to
loop in comment with memset.

From-SVN: r250201

re PR sanitizer/81066 (sanitizer_stoptheworld_linux_libcdep.cc:276:22: error: aggregate ‘sigaltstack handler_stack’ has incomplete type and cannot be defined)

PR sanitizer/81066
* sanitizer_common/sanitizer_linux.h: Cherry-pick upstream r307969.
* sanitizer_common/sanitizer_linux.cc: Likewise.
* sanitizer_common/sanitizer_stoptheworld_linux_libcdep.cc: Likewise.
* tsan/tsan_platform_linux.cc: Likewise.

From-SVN: r250200

Remove Java references in source code.

2017-07-14  Martin Liska  <mliska@suse.cz>

* cfgexpand.c (expand_gimple_basic_block): Remove dead comment.
* dwarf2out.c (is_java): Remove the function.
(output_pubname): Remove usage of the function.
(lower_bound_default): Remove usage of DW_LANG_Java.
(gen_compile_unit_die): Likewise.
* gcc.c: Remove compiler defaults for .java and .zip files.
* gimple-expr.c (remove_suffix): Change as there's no longer
extension than 4-letter one.
* gimplify.c (mostly_copy_tree_r): Remove Java-special part.
(gimplify_save_expr): Likewise.
* ipa-utils.h (polymorphic_type_binfo_p): Remove the comment
as it's possible even for other languages than Java.
* langhooks.h (struct lang_hooks): Remove Java from a comment.
* lto-opts.c (lto_write_options): Remove reference to Java.
* opts.c (strip_off_ending): Update file extension handling.
* tree-cfg.c (verify_gimple_call): Remove comment with Java.
* tree-eh.c (lower_resx): Likewise.
* tree.c (free_lang_data_in_type): Remove dead code.
(find_decls_types_r): Likewise.
(build_common_builtin_nodes): Remove Java from a comment.
(verify_type): Remove dead code.
* varasm.c (assemble_external): Remove Java from a comment.

From-SVN: r250199

Add additional quotes to opts.c.

2017-07-14  Martin Liska  <mliska@suse.cz>

* opts.c (finish_options): Add quotes.
(common_handle_option): Likewise.

From-SVN: r250198

Remove Pascal language in source code.

2017-07-14  Martin Liska  <mliska@suse.cz>

* dbxout.c (get_lang_number): Do not handle GNU Pascal.
* dbxout.h (extern void dbxout_stab_value_internal_label_diff):
Remove N_SO_PASCAL.
* dwarf2out.c (lower_bound_default): Do not handle
DW_LANG_Pascal83.
(gen_compile_unit_die): Likewise.
* gcc.c: Remove default extension binding for GNU Pascal.
* stmt.c: Remove Pascal language from a comment.
* xcoffout.c: Likewise.

From-SVN: r250197

Daily bump.

From-SVN: r250195

diagnostics: fix crash when consolidating out-of-order fix-it hints (PR c/81405)

PR c/81405 identifies a crash when printing fix-it hints from
-Wmissing-braces when there are excess elements.

The fix-it hints are bogus (which I've filed separately as PR c/81432),
but they lead to a crash within the fix-it consolidation logic I added
in r247548, in line_corrections::add_hint.

The root cause is that some of the fix-it hints are out-of-order
with respect to the column numbers they affect, which can lead to negative
values when computing the gap between the fix-it hints, leading to bogus
memcpy calls that generate out-of-bounds buffer accesses.

The fix is to sort the fix-it hints after filtering them, ensuring that
the gap >= 0.  The patch also adds numerous assertions to the code, both
directly, and by moving the memcpy calls and their args behind
interfaces (themselves containing gcc_assert).

This fixes the crash; it doesn't fix the bug in -Wmissing-braces that
leads to the bogus hints.

gcc/ChangeLog:
PR c/81405
* diagnostic-show-locus.c (fixit_cmp): New function.
(layout::layout): Sort m_fixit_hints.
(column_range::column_range): Assert that the values are valid.
(struct char_span): New struct.
(correction::overwrite): New method.
(struct source_line): New struct.
(line_corrections::add_hint): Add assertions.  Reimplement memcpy
calls in terms of classes source_line and char_span, and
correction::overwrite.
(selftest::test_overlapped_fixit_printing_2): New function.
(selftest::diagnostic_show_locus_c_tests): Call it.

gcc/testsuite/ChangeLog:
PR c/81405
* gcc.dg/Wmissing-braces-fixits.c: Add coverage for PR c/81405.  */

From-SVN: r250187

rs6000.c (rs6000_gimple_fold_builtin): Return early if there is no lhs.

[gcc]

2017-07-12  Will Schmidt  <will_schmidt@vnet.ibm.com>

* config/rs6000/rs6000.c (rs6000_gimple_fold_builtin): Return
early if there is no lhs.

[testsuite]

2017-07-12  Will Schmidt  <will_schmidt@vnet.ibm.com>

* gcc.target/powerpc/fold-vec-missing-lhs: New.

From-SVN: r250185

Cleanup #2 of Pascal references.

2017-07-13  Martin Liska  <mliska@suse.cz>

* dwarf2out.c (gen_pointer_type_die): Remove dead code.
(gen_reference_type_die): Likewise.
* stor-layout.c: Remove Pascal-related comment.

From-SVN: r250184

P0512R0 - Deduction from an initializer list.

* pt.c (do_class_deduction): Do list deduction in two phases.

From-SVN: r250183

900520_03.C: Limit error to c++14_down.

* g++.old-deja/g++.bugs/900520_03.C: Limit error to c++14_down.
* g++.old-deja/g++.law/array2.C: Likewise.

From-SVN: r250182

revert previous premature commit

From-SVN: r250181

libcp1plugin.cc (plugin_build_decl): Use DECL_CXX_{CON,DE}STRUCTOR directly.

* libcp1plugin.cc (plugin_build_decl): Use
DECL_CXX_{CON,DE}STRUCTOR directly.

From-SVN: r250180

Add quotes to error messages related to Sanitizers.

2017-07-13  Martin Liska  <mliska@suse.cz>

* opts.c (finish_options): Add quotes to error messages.
(parse_sanitizer_options): Likewise.
2017-07-13  Martin Liska  <mliska@suse.cz>

* c-c++-common/ubsan/sanitize-all-1.c: Update scanned pattern.
* c-c++-common/ubsan/sanitize-recover-1.c:Likewise.
* c-c++-common/ubsan/sanitize-recover-2.c:Likewise.
* c-c++-common/ubsan/sanitize-recover-5.c:Likewise.
* c-c++-common/ubsan/sanitize-recover-7.c:Likewise.
* c-c++-common/ubsan/sanitize-recover-8.c:Likewise.
* c-c++-common/ubsan/sanitize-recover-9.c:Likewise.

From-SVN: r250179

[ARM] Mention ARMv8-R +fp.sp option

2017-07-13  Thomas Preud'homme  <thomas.preudhomme@arm.com>

    gcc/
    * doc/invoke.texi (armv8-r): Document +fp.sp ARMv8-R extension.

From-SVN: r250178

[ARM, VXworks] Fix build

My patch last week to address selection of be8 linking mode broke the
build for vxworks.  It turns out that this port is one of the few
remaining that is still not based on the EABI/AAPCS.

This patch fixes the build, but I've not really tested it beyond
building the core compiler binaries.  Building a workable compiler
entails downloading a load of vxworks stuff that I'm not sure where to
find.

* config/arm/vxworks.h (TARGET_ENDIAN_DEFAULT): Define.

From-SVN: r250177

ASAN: fix ICE in gcc.dg/asan/pr80168.c on aarch64 -mabi=ilp32

gcc/
* asan.c (asan_emit_allocas_unpoison): Use ptr_mode for arguments
during expansion.
* builtins.c (expand_asan_emit_allocas_unpoison): Likewise.

From-SVN: r250176

re PR go/81393 (Bootstrap failure on s390x-linux while building libgo against recent glibc)

PR go/81393
    syscall: don't use GETREGS/SETREGS on s390

    They were removed in recent glibc.

    Patch by Andreas Krebbel for GCC PR 81393.

    Reviewed-on: https://go-review.googlesource.com/48231

From-SVN: r250174

Daily bump.

From-SVN: r250173

re PR target/81193 (PowerPC GCC __builtin_cpu_is and __builtin_cpu_supports should warn about old libraries)

[gcc]
2017-07-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/81193
* config/rs6000/rs6000-c.c (rs6000_cpu_cpp_builtins): If GLIBC
provides the hardware capability bits, define the macro
__BUILTIN_CPU_SUPPORTS__.
* config/rs6000/rs6000.c (cpu_expand_builtin): Generate a warning
if GLIBC does not provide the hardware capability bits.  Add a
gcc_unreachable call if the built-in cpu function is neither
__builtin_cpu_is nor __builtin_cpu_supports.
(rs6000_get_function_versions_dispatcher): Change the warning
that an old GLIBC is used which does not export the capability
bits to be an error.
* doc/extend.texi (target_clones attribute): Document the
restriction that GLIBC 2.23 or newer is needed on the PowerPC.
(PowerPC built-in functions): Document that GLIBC 2.23 or newer is
needed by __builtin_cpu_is and __builtin_cpu_supports.  Document
the macros defined by GCC if the newer GLIBC is available.

[gcc/testsuite]
2017-07-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/81193
* gcc.target/powerpc/bmi-andn-1.c: Add guard against using
__builtin_cpu_supports with old GLIBC's.
* gcc.target/powerpc/bmi-andn-2.c: Likewise.
* gcc.target/powerpc/bmi-bextr-1.c: Likewise.
* gcc.target/powerpc/bmi-bextr-2.c: Likewise.
* gcc.target/powerpc/bmi-bextr-4.c: Likewise.
* gcc.target/powerpc/bmi-bextr-5.c: Likewise.
* gcc.target/powerpc/bmi-blsi-1.c: Likewise.
* gcc.target/powerpc/bmi-blsi-2.c: Likewise.
* gcc.target/powerpc/bmi-blsmsk-1.c: Likewise.
* gcc.target/powerpc/bmi-blsmsk-2.c: Likewise.
* gcc.target/powerpc/bmi-blsr-1.c: Likewise.
* gcc.target/powerpc/bmi-blsr-2.c: Likewise.
* gcc.target/powerpc/bmi-tzcnt-1.c: Likewise.
* gcc.target/powerpc/bmi-tzcnt-2.c: Likewise.
* gcc.target/powerpc/bmi2-bzhi32-1.c: Likewise.
* gcc.target/powerpc/bmi2-bzhi64-1.c: Likewise.
* gcc.target/powerpc/bmi2-mulx32-1.c: Likewise.
* gcc.target/powerpc/bmi2-mulx32-2.c: Likewise.
* gcc.target/powerpc/bmi2-mulx64-1.c: Likewise.
* gcc.target/powerpc/bmi2-mulx64-2.c: Likewise.
* gcc.target/powerpc/bmi2-pdep32-1.c: Likewise.
* gcc.target/powerpc/bmi2-pdep64-1.c: Likewise.
* gcc.target/powerpc/bmi2-pext32-1.c: Likewise.
* gcc.target/powerpc/bmi2-pext64-1.c: Likewise.
* gcc.target/powerpc/cpu-builtin-1.c: Likewise.

[libgcc]
2017-07-12  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/81193
* configure.ac (PowerPC float128 hardware support): Test whether
we can use __builtin_cpu_supports before enabling the ifunc
handler.
* configure: Regenerate.

From-SVN: r250165

riscv.c: Remove unnecessary includes.

* config/riscv/riscv.c: Remove unnecessary includes.  Reorder
remaining includes slightly.
* config/riscv/riscv-builtins.c: Include profile-count.h.

From-SVN: r250162

libcp1plugin.cc (plugin_build_decl): Use DECL_CXX_{CON,DE}STRUCTOR directly.

* libcp1plugin.cc (plugin_build_decl): Use
DECL_CXX_{CON,DE}STRUCTOR directly.

From-SVN: r250159

cp-tree.h (DECL_CONSTRUCTOR_P, [...]): Look at identifier flags.

* cp-tree.h (DECL_CONSTRUCTOR_P, DECL_MAYBE_IN_CHARGE_CONSTRUCTOR,
DECL_DESTRUCTOR_P, DECL_MAYBE_IN_CHARGE_DESTRCTOR): Look at
identifier flags.
* decl.c (grokfndecl): Set DECL_CXX_CONSTRUCTOR and
DECL_CXX_DESTRUCTOR explicitly.
* decl2.c (grokclassfn): Likewise.
* friend.c (do_friend): Likewise.
* method.c (make_thunk, make_alias_for,
implicitly_declare_fn): Likewise.

From-SVN: r250158

re PR target/79883 (avr i18n: untranslated "interrupt" or "signal")

PR target/79883
* config/avr/avr.c (avr_set_current_function): In diagnostic
messages: Quote keywords and (parts of) identifiers.
[WITH_AVRLIBC]: Warn for functions named "ISR", "SIGNAL" or
"INTERUPT".

From-SVN: r250156

rs6000-c.c: Add support for built-in functions vector bool char vec_revb (vector bool char)...

gcc/ChangeLog:

2017-07-12  Carl Love  <cel@us.ibm.com>

* config/rs6000/rs6000-c.c: Add support for built-in functions
vector bool char vec_revb (vector bool char);
vector bool short vec_revb (vector short char);
vector bool int vec_revb (vector bool int);
vector bool long long vec_revb (vector bool long long);
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.

gcc/testsuite/ChangeLog:

2017-07-12  Carl Love  <cel@us.ibm.com>

* gcc.target/powerpc/p9-xxbr-1.c (rev_bool_char, rev_bool_short,
rev_bool_int): Add test cases for builtins.
* gcc.target/powerpc/p9-xxbr-2.c (rev_long_long, rev_ulong_ulong): Add
test cases for builtins.

From-SVN: r250155

builtins-1-p9-runnable.c (dg-ddo run): Add lp64 && p9vector_hw.

gcc/testsuite/ChangeLog:

2017-07-12  Carl Love  <cel@us.ibm.com>

* gcc.target/powerpc/builtins-1-p9-runnable.c (dg-ddo run): Add
lp64 && p9vector_hw.

From-SVN: r250154

S/390: Remove loc splitter

The backend splitter splitting a 3 operand load on condition into 2 is
wrong.  The S/390 load on condition instruction might trap on the
memory operand even if the condition is false.  So if the first load
on condition overwrites a register used as part of the memory address
of the second the second might trigger a segfault even if it does not
actually perform the load.

Trying to fix this I noticed that the generated code looks anyway
better without the splitter.  So removing the splitter entirely is the
way to go here.

gcc/ChangeLog:

2017-07-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

* config/s390/s390.md: Remove movcc splitter.

From-SVN: r250153

S/390: Calculate costs for load/store on condition

This adds code to the backend rtx_costs function in order to model the
costs of a load/store on condition.

gcc/ChangeLog:

2017-07-12  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

* config/s390/s390.c (s390_rtx_costs): Return proper costs for
load/store on condition.

From-SVN: r250152

re PR target/81407 ([avr] Diagnose if a variable in progmem needs constructing.)

PR target/81407
* config/avr/avr.c (avr_encode_section_info)
[progmem && !TREE_READONLY]: Error if progmem object needs
constructing.

From-SVN: r250151

[testsuite] Fix dg-require-stack-check

2017-07-12  Christophe Lyon  <christophe.lyon@linaro.org>

* lib/target-supports.exp (check_stack_check_available): Make
testcase name depend on stack_kind.

From-SVN: r250149

aarch64-simd.md (aarch64_sub<mode>_compare0): New pattern.

2017-07-11  Michael Collison  <michael.collison@arm.com>

* config/aarch64/aarch64-simd.md(aarch64_sub<mode>_compare0):
New pattern.
* testsuite/gcc.target/aarch64/cmp-2.c: New testcase.

From-SVN: r250148

Daily bump.

From-SVN: r250147

re PR c++/51270 (missed warning about returning reference to temporary)

2017-07-11  Paolo Carlini  <paolo.carlini@oracle.com>

PR c++/51270
* g++.dg/warn/Wreturn-local-addr-3.C: New.

From-SVN: r250140

Core DR 393 - parameter pointer to array of unknown bound

* decl.c (grokparms): Downgrade error about array of unknown bound
to pedwarn and disable it for C++17.

From-SVN: r250137

rs6000-c.c: Add support for builtins vector unsigned int vec_parity_lsbb (vector signed int)...

gcc/ChangeLog:

2017-07-11  Carl Love  <cel@us.ibm.com>

* config/rs6000/rs6000-c.c: Add support for builtins
vector unsigned int vec_parity_lsbb (vector signed int);
vector unsigned int vec_parity_lsbb (vector unsigned int);
vector unsigned __int128 vec_parity_lsbb (vector signed __int128);
vector unsigned __int128 vec_parity_lsbb (vector unsigned __int128);
vector unsigned long long vec_parity_lsbb (vector signed long long);
vector unsigned long long vec_parity_lsbb (vector unsigned long long);
* config/rs6000/rs6000-builtin.def (VPARITY_LSBB): Add BU_P9V_OVERLOAD1.
* config/rs6000/altivec.h (vec_parity_lsbb): Add define.
* doc/extend.texi: Update the built-in documentation file for the
new built-in functions.

gcc/testsuite/ChangeLog:

2017-07-11  Carl Love  <cel@us.ibm.com>

* gcc.target/powerpc/builtins-2-p9-runnable.c: Add new file with
test cases for the builtins.

From-SVN: r250135

Fix ChangeLog omission in r250133

From-SVN: r250134

diagnostics: support compact printing of secondary locations

gcc/ChangeLog:
* diagnostic-show-locus.c: Include "gcc-rich-location.h".
(layout::m_primary_loc): New field.
(layout::layout): Initialize new field.  Move location filtering
logic from here to...
(layout::maybe_add_location_range): ...this new method.  Add
support for filtering to just the lines already specified by other
locations.
(layout::will_show_line_p): New method.
(selftest::test_add_location_if_nearby): New test function.
(selftest::diagnostic_show_locus_c_tests): Call it.
* gcc-rich-location.h (gcc_rich_location::add_location_if_nearby):
New method.

From-SVN: r250133

* decl2.c (reset_type_linkage_2): Dont't change ctor name.

From-SVN: r250130

Add extra initialization of broadcasted condition variables

2017-07-11  Tom de Vries  <tom@codesourcery.com>

* config/nvptx/nvptx.c (WORKAROUND_PTXJIT_BUG): New macro.
(bb_first_real_insn): New function.
(nvptx_single): Add extra initialization of broadcasted condition
variables.

From-SVN: r250129

profopt.exp: Print relative names in UNSUPPORTED AutoFDO tests.

2017-07-11  Yury Gribov  <tetra2005@gmail.com>

* lib/profopt.exp: Print relative names in UNSUPPORTED
AutoFDO tests.

From-SVN: r250128

* dwarf2out.c (gen_member_die): Remove useless check for anon ctors.

From-SVN: r250127

Improvements to the libstdc++ FAQ and manual

* doc/xml/faq.xml: Update several old entries. Improve
cross-references.
* doc/xml/manual/intro.xml: Add anchors to each DR.
* doc/html/*: Regenerate.

From-SVN: r250125

extend.texi (AVR Function Attributes): Remove weblink to Binutils doc as TEXI will mess them up.

* doc/extend.texi (AVR Function Attributes): Remove weblink to
Binutils doc as TEXI will mess them up.
* doc/invoke.texi (AVR Options): Same here.

From-SVN: r250124

sparc.opt (mfix-ut700): New option.

* config/sparc/sparc.opt (mfix-ut700): New option.
(mfix-gr712rc): Likewise.
(sparc_fix_b2bst): New variable.
* doc/invoke.texi (SPARC options): Document them.
(ARM options): Fix warnings.
* config/sparc/sparc.c (sparc_do_work_around_errata): Insert NOP
instructions to prevent sequences that can trigger the store-store
errata for certain LEON3FT processors.
(pass_work_around_errata::gate): Also test sparc_fix_b2bst.
(sparc_option_override): Set sparc_fix_b2bst appropriately.
* config/sparc/sparc.md (fix_b2bst): New attribute.
(in_branch_delay): Prevent stores in delay slot if fix_b2bst.

From-SVN: r250114

var_shift_mask_1.c: Fix for ILP32

2017-07-10  Michael Collison <michael.collison@arm.com>

* gcc.target/aarch64/var_shift_mask_1.c: Fix for ILP32

From-SVN: r250112

Daily bump.

From-SVN: r250111

re PR target/81375 (unrecognizable insn)

PR target/81375
* config/i386/i386.md (divsf3): Add TARGET_SSE to TARGET_SSE_MATH.
(rcpps): Ditto.
(*rsqrtsf2_sse): Ditto.
(rsqrtsf2): Ditto.
(div<mode>3): Macroize insn from divdf3 and divsf3
using MODEF mode iterator.

testsuite/ChangeLog:

PR target/81375
* gcc.target/i386/pr81375.c: New test.

From-SVN: r250107

PR tree-optimization/80397 - missing -Wformat-overflow with arguments of enum types

gcc/ChangeLog:

PR tree-optimization/80397
* gimple-ssa-sprintf.c (format_integer): Use INTEGRAL_TYPE_P()
instead of testing for equality to INTEGER_TYPE.

gcc/testsuite/ChangeLog:

PR tree-optimization/80397
* gcc.dg/tree-ssa/builtin-sprintf-warn-17.c: New test.

From-SVN: r250106

cp-tree.h (cp_operator_id, [...]): Document.

gcc/cp/ChangeLog:

* cp-tree.h (cp_operator_id, cp_assignment_operator_id): Document.

From-SVN: r250105

PR other/81345 -  -Wall resets -Wstringop-overflow to 1 from the default 2

gcc/c-family/ChangeLog:

PR other/81345
* c.opt (-Wstringop-overflow): Set defaults in LangEnabledBy.

gcc/testsuite/ChangeLog:

PR other/81345
* gcc.dg/pr81345.c: New test.

From-SVN: r250104

Include missing header for std::free

* testsuite/abi/pr42230.cc: Add header for std::free.

From-SVN: r250102

PR libstdc++/81381 support stateful allocators in basic_stringbuf

PR libstdc++/81381
* include/bits/sstream.tcc (basic_stringbuf::overflow)
(basic_stringbuf::basic_stringbuf(const __string_type&, ios::mode))
(basic_stringbuf::str()): Construct new strings with an allocator.
* testsuite/27_io/basic_stringbuf/cons/81381.cc: New.

From-SVN: r250101

PR libstdc++/81338 correctly manage string capacity

PR libstdc++/81338
* include/bits/basic_string.h [_GLIBCXX_USE_CXX11_ABI] (basic_string):
Declare basic_stringbuf to be a friend.
* include/bits/sstream.tcc (basic_stringbuf::overflow)
[_GLIBCXX_USE_CXX11_ABI]: Use unused capacity before reallocating.
* include/std/sstream (basic_stringbuf::__xfer_bufptrs): Update string
length to buffer length.
* testsuite/27_io/basic_stringstream/assign/81338.cc: New.

From-SVN: r250100

[ARC] Configure script to allow non uclibc based triplets

gcc/
2017-07-10  Vineet Gupta <vgupta@synopsys.com>

        * config.gcc: Remove uclibc from arc target spec.

libgcc/
2017-07-10  Vineet Gupta <vgupta@synopsys.com>

        * config.host: Remove uclibc from arc target spec.

From-SVN: r250097

[ARC] Fix tests asm constraints.

LRA doesn't like the 'X' constraint as used in our tests, remove it.

gcc/testsuite
2017-07-10  Claudiu Zissulescu  <claziss@synopsys.com>

* gcc.target/arc/mulsi3_highpart-1.c: Remove 'X' constraint.
* gcc.target/arc/mulsi3_highpart-2.c: Likewise.

From-SVN: r250096

[ARC] Define ADDITIONAL_REGISTER_NAMES.

This macro is needed to be used with -ffixed-<reg> option, and inline asm.

gcc/
2017-07-10  Claudiu Zissulescu  <claziss@synopsys.com>

* config/arc/arc.h (ADDITIONAL_REGISTER_NAMES): Define.

From-SVN: r250095

re PR bootstrap/80838 (PGO/LTO bootstrapped compiler 5% slower than pure PGO bootstrapped one)

PR lto/80838
* lto-wrapper.c (remove_option): New function.
(merge_and_complain): Merge PIC/PIE options more realistically.

From-SVN: r250094

Better ISR prologues by supporting GASes __gcc_isr pseudo insn.

gcc/
Better ISR prologues by supporting GASes __gcc_isr pseudo insn.
PR target/20296
PR target/81268
* configure.ac [target=avr]: Add GAS check for -mgcc-isr.
(HAVE_AS_AVR_MGCCISR_OPTION):  If so, AC_DEFINE it.
* config.in: Regenerate.
* configure: Regenerate.
* doc/extend.texi (AVR Function Attributes) <no_gccisr>: Document it.
* doc/invoke.texi (AVR Options) <-mgas-isr-prologues>: Document it.
* config/avr/avr.opt (-mgas-isr-prologues): New option and...
(TARGET_GASISR_PROLOGUES): ...target mask.
* common/config/avr/avr-common.c
(avr_option_optimization_table) [OPT_LEVELS_1_PLUS_NOT_DEBUG]:
Set -mgas-isr-prologues.
* config/avr/avr-passes.def (avr_pass_pre_proep): Add
INSERT_PASS_BEFORE for it.
* config/avr/avr-protos.h (make_avr_pass_pre_proep): New proto.
* config/avr/avr.c (avr_option_override)
[!HAVE_AS_AVR_MGCCISR_OPTION]: Unset TARGET_GASISR_PROLOGUES.
(avr_no_gccisr_function_p, avr_hregs_split_reg): New static functions.
(avr_attribute_table) <no_gccisr>: Add new function attribute.
(avr_set_current_function) <is_no_gccisr>: Init machine field.
(avr_pass_data_pre_proep, avr_pass_pre_proep): New pass data
and rtl_opt_pass.
(make_avr_pass_pre_proep): New function.
(emit_push_sfr) <treg>: Add argument to function and use it
instead of TMP_REG.
(avr_expand_prologue) [machine->gasisr.maybe]: Emit gasisr insn
and set machine->gasisr.yes.
(avr_expand_epilogue) [machine->gasisr.yes]: Similar.
(avr_asm_function_end_prologue) [machine->gasisr.yes]: Add
__gcc_isr.n_pushed to .L__stack_usage.
(TARGET_ASM_FINAL_POSTSCAN_INSN): Define to...
(avr_asm_final_postscan_insn): ...this new static function.
* config/avr/avr.h (machine_function)
<is_no_gccisr, use_L__stack_usage>: New fields.
<gasisr, gasisr.yes, gasisr.maybe, gasisr.regno>: New fields.
* config/avr/avr.md (UNSPECV_GASISR): Add unspecv enum.
(GASISR_Prologue, GASISR_Epilogue, GASISR_Done): New define_constants.
(gasisr, *gasisr): New expander and insn.
* config/avr/gen-avr-mmcu-specs.c (print_mcu)
[HAVE_AS_AVR_MGCCISR_OPTION]: Print asm_gccisr spec.
* config/avr/specs.h (ASM_SPEC) <asm_gccisr>: Add sub spec.

From-SVN: r250093

[arm] Fix warning in parsecpu.awk

In awk, single quotes within a quoted string do not need escaping.
The existing code causes awk to grumble in the build logs.

* config/arm/parsecpu.awk (gen_comm_data): Do not escape single quotes
in quoted strings.

(really commit it this time)...

From-SVN: r250092

Move jump-tables out of .text again.

gcc/
Move jump-tables out of .text again.
PR target/81075
* config/avr/avr.c (ASM_OUTPUT_ADDR_VEC_ELT): Remove function.
(ASM_OUTPUT_ADDR_VEC): New function.
(avr_adjust_insn_length) [JUMP_TABLE_DATA_P]: Return 0.
(avr_final_prescan_insn) [avr_log.insn_addresses]: Dump
INSN_ADDRESSes as asm comment.
* config/avr/avr.h (JUMP_TABLES_IN_TEXT_SECTION): Adjust comment.
(ASM_OUTPUT_ADDR_VEC_ELT): Remove define.
(ASM_OUTPUT_ADDR_VEC): Define to avr_output_addr_vec.
* config/avr/avr.md (*tablejump): Adjust comment.
* config/avr/elf.h (ASM_OUTPUT_BEFORE_CASE_LABEL): Remove.
* config/avr/avr-log.c (avr_log_set_avr_log) <insn_addresses>:
New detail.
* config/avr/avr-protos.h (avr_output_addr_vec_elt): Remove proto.
(avr_output_addr_vec): New proto.
(avr_log_t) <insn_addresses>: New field.

From-SVN: r250091

Daily bump.

From-SVN: r250090

re PR target/81313 (Bad stack realignment code with -mno-accumulate-outgoing-args)

PR target/81313
* gcc.dg/stack-layout-dynamic-1.c (bar): Add 4 additional
integer argumets to bypass x86_64 outgoing args optimization.

From-SVN: r250086

eoshift2.c (eoshift2): Use memcpy for innermost copy where possible.

2017-06-09  Thomas Koenig  <tkoenig@gcc.gnu.org>

* intrinsics/eoshift2.c (eoshift2):  Use memcpy
for innermost copy where possible.
* m4/eoshift1.m4 (eoshift1): Likewise.
* m4/eoshift3.m4 (eoshift3): Likewise.
* generated/eoshift1_16.c: Regenerated.
* generated/eoshift1_4.c: Regenerated.
* generated/eoshift1_8.c: Regenerated.
* generated/eoshift3_16.c: Regenerated.
* generated/eoshift3_4.c: Regenerated.
* generated/eoshift3_8.c: Regenerated.

2017-06-09  Thomas Koenig  <tkoenig@gcc.gnu.org>

* gfortran.dg/eoshift_4.f90:  New test.
* gfortran.dg/eoshift_5.f90:  New test.
* gfortran.dg/eoshift_6.f90:  New test.

From-SVN: r250085

x86: Use DRAP only if there are outgoing arguments on stack

Since DRAP is needed only if there are outgoing arguments on stack, we
should track outgoing arguments on stack and avoid setting need_drap to
true when there are no outgoing arguments on stack.

gcc/

PR target/81313
* config/i386/i386.c (ix86_function_arg_advance): Set
outgoing_args_on_stack to true if there are outgoing arguments
on stack.
(ix86_function_arg): Likewise.
(ix86_get_drap_rtx): Use DRAP only if there are outgoing
arguments on stack and ACCUMULATE_OUTGOING_ARGS is false.
* config/i386/i386.h (machine_function): Add
outgoing_args_on_stack.

gcc/testsuite/

PR target/81313
* gcc.target/i386/pr81313-1.c: New test.
* gcc.target/i386/pr81313-2.c: Likewise.
* gcc.target/i386/pr81313-3.c: Likewise.
* gcc.target/i386/pr81313-4.c: Likewise.
* gcc.target/i386/pr81313-5.c: Likewise.

From-SVN: r250084

re PR fortran/81341 (trunk/gcc/fortran/class.c:313: redundant condition ?)

2017-07-09  Dominique d'Humieres  <dominiq@lps.ens.fr>

PR fortran/81341
* class.c (class_array_ref_detected): Remove a redundant
condition.

From-SVN: r250083

config.gcc (*-*-netbsd*): Remove check for NetBSD versions not supporting pthreds.

2017-07-09  Krister Walfridsson  <krister.walfridsson@gmail.com>

* config.gcc (*-*-netbsd*): Remove check for NetBSD versions not
supporting pthreds.
* config/netbsd.h (NETBSD_LIBGCC_SPEC): Always enable pthreads.

From-SVN: r250081

config.host (*-*-netbsd*): Remove check for aout NetBSD releases.

2017-07-09  Krister Walfridsson  <krister.walfridsson@gmail.com>

* config.host (*-*-netbsd*): Remove check for aout NetBSD releases.

From-SVN: r250080

Daily bump.

From-SVN: r250079

Fix coretypes.h-related dependencies

The bug fix here is to build/min-insn-modes.o, the rest are related
clean-ups.

2017-07-08  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* Makefile.in (HOOKS_H, RTL_BASE_H, FUNCTION_H, EXPR_H, REGS_H)
(REAL_H): Remove $(MACHMODE_H).
(FIXED_VALUE_H, TREE_CORE_H, CFGLOOP_H): Remove $(MACHMODE_H) and
double-int.h.
(CORETYPES_H): Add signop.h, wide-int.h, wide-int-print.h,
$(MACHMODE_H) and double-int.h.
(build/min-insn-modes.o): Depend on $(CORETYPES_H) rather than
$(MACHMODE_H).
(gengtype-state.o, gengtype.o, build/gengtype.o): Don't depend on
double-int.h.

From-SVN: r250075

Force a dependence distance of 1 in gnat.dg/vect17.adb

2017-07-08  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/testsuite/
* gnat.dg/vect15.ads (Sarray): Increase range to 1 .. 5.
* gnat.dg/vect16.ads (Sarray): Likewise.
* gnat.dg/vect17.ads (Sarray): Likewise.
* gnat.dg/vect15.adb (Add): Create a dependence distance of 1.
* gnat.dg/vect16.adb (Add): Likewise.
* gnat.dg/vect17.adb (Add): Likewise.

From-SVN: r250074

Daily bump.

From-SVN: r250072

aarch64.c (aarch_macro_fusion_pair_p): Check prev_set and curr_set for AARCH64_FUSE_ALU_BRANCH.

2017-07-07  Andrew Pinski  <apinski@cavium.com>

        * config/aarch64/aarch64.c (aarch_macro_fusion_pair_p): Check
        prev_set and curr_set for AARCH64_FUSE_ALU_BRANCH.

From-SVN: r250068

float128-ifunc.c: Don't include auxv.h.

libgcc/
* config/rs6000/float128-ifunc.c: Don't include auxv.h.
(have_ieee_hw_p): Delete function.
(SW_OR_HW) Use __builtin_cpu_supports().

From-SVN: r250061

libcpp: preserve ranges within macro expansions (PR c++/79300)

gcc/testsuite/ChangeLog:
PR c++/79300
* g++.dg/diagnostic/pr79300.C: New test case.

libcpp/ChangeLog:
PR c++/79300
* line-map.c (linemap_macro_loc_to_def_point): Preserve range
information for macro expansions by delaying resolving ad-hoc
locations until within the loop.

From-SVN: r250058

rs6000.c (rs6000_get_function_versions_dispatcher): Add warning if GCC was not configured to link against a GLIBC that exports the...

[gcc]
2017-07-07  Michael Meissner  <meissner@linux.vnet.ibm.com>

* config/rs6000/rs6000.c (rs6000_get_function_versions_dispatcher):
Add warning if GCC was not configured to link against a GLIBC that
exports the hardware capability bits.
(make_resolver_func): Make resolver function private and not a
COMDAT function.  Create the name with clone_function_name instead
of make_unique_name.

[gcc/testsuite]
2017-07-07  Michael Meissner  <meissner@linux.vnet.ibm.com>

* gcc.target/powerpc/clone1.c: Add check to make sure the
__builtin_cpu_supports function is fully supported.
* gcc.target/powerpc/clone2.c: New runtime test for
target_clones.

From-SVN: r250055

re PR target/81348 (PowerPC64: Code built with -mcpu=power9 hits SEGV in RTL split2)

[gcc]
2017-07-07  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/81348
* config/rs6000/rs6000.md (HI sign_extend splitter): Use the
correct operand in doing the split.

[gcc/testsuite]
2017-07-07  Michael Meissner  <meissner@linux.vnet.ibm.com>

PR target/81348
* gcc.target/powerpc/pr81348.c: New test.

From-SVN: r250054

Fix pr60510.f test on arm-linux-gnueabihf

Only run the test if the target supports double precision vectorization.

gcc/testsuite/ChangeLog:

2017-07-07  Szabolcs Nagy  <szabolcs.nagy@arm.com>

* gfortran.dg/vect/pr60510.f: Require vect_double support.

From-SVN: r250053

builtins-1-p9-runnable.c: Forgot to add new file before doing commit 250051.

gcc/testsuite/ChangeLog:

2017-07-07  Carl Love  <cel@us.ibm.com>

* gcc.target/powerpc/builtins-1-p9-runnable.c: Forgot to add new
file before doing commit 250051.

From-SVN: r250052

rs6000-c: Add support for built-in function vector unsigned short vec_pack_to_short_fp32...

gcc/ChangeLog:

2017-07-07 Carl Love  <cel@us.ibm.com>

* config/rs6000/rs6000-c: Add support for built-in function
vector unsigned short vec_pack_to_short_fp32 (vector float,
      vector float).
* config/rs6000/rs6000-builtin.def (CONVERT_4F32_8I16): Add
BU_P9V_AV_2 and BU_P9V_OVERLOAD_2 definitions.
* config/rs6000/altivec.h (vec_pack_to_short_fp32): Add define.
* config/rs6000/altivec.md(UNSPEC_CONVERT_4F32_8I16): Add UNSPEC.
(convert_4f32_8i16): Add define_expand.
* doc/extend.texi: Update the built-in documentation file for the
new built-in function.

gcc/testsuite/ChangeLog:

2017-07-07  Carl Love  <cel@us.ibm.com>

* gcc.target/powerpc/builtins-1-p9-runnable.c: Add new test
file for built-ins.

From-SVN: r250051

Support for the SPARC M8 cpu.

This patch serie adds support for the SPARC M8 processor to GCC.
The SPARC M8 processor implements the Oracle SPARC Architecture 2017.

- bmask* instructions are put in their own instruction type.  It makes
  little sense to have them in the same category than array
  instructions.

- Similarly, VIS compare instructions are put in their own instruction
  type.  This is to better accommodate subtypes, which are not quite
  the same than the subtypes of `visl' instructions.

- The introduction of a new `subtype' insn attribute in sparc.md
  avoids the need for adjusting the instruction scheduler DFAs for
  previous cpu models every time a new cpu is introduced.

- The full set of SPARC instructions used in sparc.md, and their
  position in the type/subtype hierarchy, is documented in a comment.
  This eases the modification of the DFA schedulers, and the addition
  of new cpus.

- The M7 DFA scheduler is reworked:

  + To use the new type/subtype hierarchy.
  + The v3pipe insn attribute is no longer needed.
  + More accurate latencies for instructions.
  + The C4 core pipeline is documented in a comment in niagara7.md.

- Support for -mcpu=m8 (we are thus suggesting to abandon the niagaraN
  denomination for M8 and later processors.)

- Support for a new VIS level, VIS4B, covering the new VIS
  instructions introduced in OSA2017 and implemented in the M8.  Also
  built-ins.

- A M8 DFA scheduler:

  + Also based on the new type/subtype hierarchy.
  + The functional units in the C5 core are explicitly documented in a
    comment in m8.md.

gcc/ChangeLog:

* config/sparc/m8.md: New file.
* config/sparc/sparc.md: Include m8.md.

* config/sparc/sparc.opt: New option -mvis4b.
* config/sparc/sparc.c (dump_target_flag_bits): Handle MASK_VIS4B.
(sparc_option_override): Handle VIS4B.
(enum sparc_builtins): Define
SPARC_BUILTIN_DICTUNPACK{8,16,32},
SPARC_BUILTIN_FPCMP{LE,GT,EQ,NE}{8,16,32}SHL,
SPARC_BUILTIN_FPCMPU{LE,GT}{8,16,32}SHL,
SPARC_BUILTIN_FPCMPDE{8,16,32}SHL and
SPARC_BUILTIN_FPCMPUR{8,16,32}SHL.
(check_constant_argument): New function.
(sparc_vis_init_builtins): Define builtins
__builtin_vis_dictunpack{8,16,32},
__builtin_vis_fpcmp{le,gt,eq,ne}{8,16,32}shl,
__builtin_vis_fpcmpu{le,gt}{8,16,32}shl,
__builtin_vis_fpcmpde{8,16,32}shl and
__builtin_vis_fpcmpur{8,16,32}shl.
(sparc_expand_builtin): Check that the constant operands to
__builtin_vis_fpcmp*shl and _builtin_vis_dictunpack* are indeed
constant and in range.
* config/sparc/sparc-c.c (sparc_target_macros): Handle
TARGET_VIS4B.
* config/sparc/sparc.h (SPARC_IMM2_P): Define.
(SPARC_IMM5_P): Likewise.
* config/sparc/sparc.md (cpu_feature): Add new feagure "vis4b".
(enabled): Handle vis4b.
(UNSPEC_DICTUNPACK): New unspec.
(UNSPEC_FPCMPSHL): Likewise.
(UNSPEC_FPUCMPSHL): Likewise.
(UNSPEC_FPCMPDESHL): Likewise.
(UNSPEC_FPCMPURSHL): Likewise.
(cpu_feature): New CPU feature `vis4b'.
(dictunpack{8,16,32}): New insns.
(FPCSMODE): New mode iterator.
(fpcscond): New code iterator.
(fpcsucond): Likewise.
(fpcmp{le,gt,eq,ne}{8,16,32}{si,di}shl): New insns.
(fpcmpu{le,gt}{8,16,32}{si,di}shl): Likewise.
(fpcmpde{8,16,32}{si,di}shl): Likewise.
(fpcmpur{8,16,32}{si,di}shl): Likewise.
* config/sparc/constraints.md: Define constraints `q' for unsigned
2-bit integer constants and `t' for unsigned 5-bit integer
constants.
* config/sparc/predicates.md (imm5_operand_dictunpack8): New
predicate.
(imm5_operand_dictunpack16): Likewise.
(imm5_operand_dictunpack32): Likewise.
(imm2_operand): Likewise.
* doc/invoke.texi (SPARC Options): Document -mvis4b.
* doc/extend.texi (SPARC VIS Built-in Functions): Document the
ditunpack* and fpcmp*shl builtins.

* config.gcc: Handle m8 in --with-{cpu,tune} options.
* config.in: Add HAVE_AS_SPARC6 define.
* config/sparc/driver-sparc.c (cpu_names): Add entry for the SPARC
M8.
* config/sparc/sol2.h (CPP_CPU64_DEFAULT_SPEC): Define for
TARGET_CPU_m8.
(ASM_CPU32_DEFAUILT_SPEC): Likewise.
(CPP_CPU_SPEC): Handle m8.
(ASM_CPU_SPEC): Likewise.
* config/sparc/sparc-opts.h (enum processor_type): Add
PROCESSOR_M8.
* config/sparc/sparc.c (m8_costs): New struct.
(sparc_option_override): Handle TARGET_CPU_m8.
(sparc32_initialize_trampoline): Likewise.
(sparc64_initialize_trampoline): Likewise.
(sparc_issue_rate): Likewise.
(sparc_register_move_cost): Likewise.
* config/sparc/sparc.h (TARGET_CPU_m8): Define.
(CPP_CPU64_DEFAULT_SPEC): Define for M8.
(ASM_CPU64_DEFAULT_SPEC): Likewise.
(CPP_CPU_SPEC): Handle M8.
(ASM_CPU_SPEC): Likewise.
(AS_M8_FLAG): Define.
* config/sparc/sparc.md: Add m8 to the cpu attribute.
* config/sparc/sparc.opt: New option -mcpu=m8 for sparc targets.
* configure.ac (HAVE_AS_SPARC6): Check for assembler support for
M8 instructions.
* configure: Regenerate.
* doc/invoke.texi (SPARC Options): Document -mcpu=m8 and
-mtune=m8.

* config/sparc/niagara7.md: Rework the DFA scheduler to use insn
subtypes.
* config/sparc/sparc.md: Remove the `v3pipe' insn attribute.
("*movdi_insn_sp32"): Do not set v3pipe.
("*movsi_insn"): Likewise.
("*movdi_insn_sp64"): Likewise.
("*movsf_insn"): Likewise.
("*movdf_insn_sp32"): Likewise.
("*movdf_insn_sp64"): Likewise.
("*zero_extendsidi2_insn_sp64"): Likewise.
("*sign_extendsidi2_insn"): Likewise.
("*mov<VM32:mode>_insn"): Likewise.
("*mov<VM64:mode>_insn_sp64"): Likewise.
("*mov<VM64:mode>_insn_sp32"): Likewise.
("<plusminus_insn><VADDSUB:mode>3"): Likewise.
("<vlop:code><VL:mode>3"): Likewise.
("*not_<vlop:code><VL:mode>3"): Likewise.
("*nand<VL:mode>_vis"): Likewise.
("*<vlnotop:code>_not1<VL:mode>_vis"): Likewise.
("*<vlnotop:code>_not2<VL:mode>_vis"): Likewise.
("one_cmpl<VL:mode>2"): Likewise.
("faligndata<VM64:mode>_vis"): Likewise.
("alignaddrsi_vis"): Likewise.
("alignaddrdi_vis"): Likweise.
("alignaddrlsi_vis"): Likewise.
("alignaddrldi_vis"): Likewise.
("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise.
("bmaskdi_vis"): Likewise.
("bmasksi_vis"): Likewise.
("bshuffle<VM64:mode>_vis"): Likewise.
("cmask8<P:mode>_vis"): Likewise.
("cmask16<P:mode>_vis"): Likewise.
("cmask32<P:mode>_vis"): Likewise.
("pdistn<P:mode>_vis"): Likewise.
("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise.

* config/sparc/sparc.md ("subtype"): New insn attribute.
("*wrgsr_sp64"): Set insn subtype.
("*rdgsr_sp64"): Likewise.
("alignaddrsi_vis"): Likewise.
("alignaddrdi_vis"): Likewise.
("alignaddrlsi_vis"): Likewise.
("alignaddrldi_vis"): Likewise.
("<plusminus_insn><VADDSUB:mode>3"): Likewise.
("fexpand_vis"): Likewise.
("fpmerge_vis"): Likewise.
("faligndata<VM64:mode>_vis"): Likewise.
("bshuffle<VM64:mode>_vis"): Likewise.
("cmask8<P:mode>_vis"): Likewise.
("cmask16<P:mode>_vis"): Likewise.
("cmask32<P:mode>_vis"): Likewise.
("fchksm16_vis"): Likewise.
("v<vis3_shift_patname><GCM:mode>3"): Likewise.
("fmean16_vis"): Likewise.
("fp<plusminus_insn>64_vis"): Likewise.
("<plusminus_insn>v8qi3"): Likewise.
("<vis3_addsub_ss_patname><VASS:mode>3"): Likewise.
("<vis4_minmax_patname><VMMAX:mode>3"): Likewise.
("<vis4_uminmax_patname><VMMAX:mode>3"): Likewise.
("<vis3_addsub_ss_patname>v8qi3"): Likewise.
("<vis4_addsub_us_patname><VAUS:mode>3"): Likewise.
("*movqi_insn"): Likewise.
("*movhi_insn"): Likewise.
("*movsi_insn"): Likewise.
("movsi_pic_gotdata_op"): Likewise.
("*movdi_insn_sp32"): Likewise.
("*movdi_insn_sp64"): Likewise.
("movdi_pic_gotdata_op"): Likewise.
("*movsf_insn"): Likewise.
("*movdf_insn_sp32"): Likewise.
("*movdf_insn_sp64"): Likewise.
("*zero_extendhisi2_insn"): Likewise.
("*zero_extendqihi2_insn"): Likewise.
("*zero_extendqisi2_insn"): Likewise.
("*zero_extendqidi2_insn"): Likewise.
("*zero_extendhidi2_insn"): Likewise.
("*zero_extendsidi2_insn_sp64"): Likewise.
("ldfsr"): Likewise.
("prefetch_64"): Likewise.
("prefetch_32"): Likewise.
("tie_ld32"): Likewise.
("tie_ld64"): Likewise.
("*tldo_ldub_sp32"): Likewise.
("*tldo_ldub1_sp32"): Likewise.
("*tldo_ldub2_sp32"): Likewise.
("*tldo_ldub_sp64"): Likewise.
("*tldo_ldub1_sp64"): Likewise.
("*tldo_ldub2_sp64"): Likewise.
("*tldo_ldub3_sp64"): Likewise.
("*tldo_lduh_sp32"): Likewise.
("*tldo_lduh1_sp32"): Likewise.
("*tldo_lduh_sp64"): Likewise.
("*tldo_lduh1_sp64"): Likewise.
("*tldo_lduh2_sp64"): Likewise.
("*tldo_lduw_sp32"): Likewise.
("*tldo_lduw_sp64"): Likewise.
("*tldo_lduw1_sp64"): Likewise.
("*tldo_ldx_sp64"): Likewise.
("*mov<VM32:mode>_insn"): Likewise.
("*mov<VM64:mode>_insn_sp64"): Likewise.
("*mov<VM64:mode>_insn_sp32"): Likewise.

* config/sparc/sparc.md ("type"): New insn type viscmp.
("fcmp<gcond:code><GCM:gcm_name><P:mode>_vis"): Set insn type to
viscmp.
("fpcmp<gcond:code>8<P:mode>_vis"): Likewise.
("fucmp<gcond:code>8<P:mode>_vis"): Likewise.
("fpcmpu<gcond:code><GCM:gcm_name><P:mode>_vis"): Likewise.
* config/sparc/niagara7.md ("n7_vis_logical_v3pipe"): Handle
viscmp.
("n7_vis_logical_11cycle"): Likewise.
* config/sparc/niagara4.md ("n4_vis_logical"): Likewise.
* config/sparc/niagara2.md ("niag3_vis": Likewise.
* config/sparc/niagara.md ("niag_vis"): Likewise.
* config/sparc/ultra3.md ("us3_fga"): Likewise.
* config/sparc/ultra1_2.md ("us1_fga_double"): Likewise.

* config/sparc/sparc.md: New instruction type `bmask'.
(bmaskdi_vis): Use the `bmask' type.
(bmasksi_vis): Likewise.
* config/sparc/ultra3.md (us3_array): Likewise.
* config/sparc/niagara7.md (n7_array): Likewise.
* config/sparc/niagara4.md (n4_array): Likewise.
* config/sparc/niagara2.md (niag2_vis): Likewise.
(niag3_vis): Likewise.
* config/sparc/niagara.md (niag_vis): Likewise.

gcc/testsuite/ChangeLog:

* gcc.target/sparc/dictunpack.c: New file.
* gcc.target/sparc/fpcmpdeshl.c: Likewise.
* gcc.target/sparc/fpcmpshl.c: Likewise.
* gcc.target/sparc/fpcmpurshl.c: Likewise.
* gcc.target/sparc/fpcmpushl.c: Likewise.

From-SVN: r250049

ipa-comdats.c: Remove optimize check from gate.

* ipa-comdats.c: Remove optimize check from gate.
* ipa-fnsummary.c (ipa_fn_summary_generate): do not generate summary
for functions not optimized.
(ipa_fn_summary_read): Skip optimize check.
(ipa_fn_summary_write): Likewise.
* ipa-inline-analysis.c (do_estimate_growth_1): Check that caller
is optimized.
* ipa-inline.c (can_inline_edge_p): Not optimized functions are
uninlinable.
(can_inline_edge_p): Check flag_pcc_struct_return for match.
(check_callers): Give up on caller which is not optimized.
(inline_small_functions): Likewise.
(ipa_inline): Do not give up when not optimizing.
* ipa-visbility.c (function_and_variable_visibility): Do not optimize
away unoptimizes cdtors.
(whole_program_function_and_variable_visibility): Do
ipa_discover_readonly_nonaddressable_vars in LTO mode.
* ipa.c (process_references): Do not check optimize.
(symbol_table::remove_unreachable_nodes): Update optimize check.
(set_writeonly_bit): Update optimize check.
(pass_ipa_cdtor_merge::gate): Do not check optimize.
(pass_ipa_single_use::gate): Remove.

From-SVN: r250048

Daily bump.

From-SVN: r250047

rs6000.c (union_defs, [...]): Move all code related to p8 swap optimizations to file rs6000-p8swap.c.

2017-07-06  Aaron Sawdey  <acsawdey@linux.vnet.ibm.com>

* config/rs6000/rs6000.c (union_defs, union_uses, insn_is_load_p,
insn_is_store_p, insn_is_swap_p, const_load_sequence_p, v2df_reduction_p,
rtx_is_swappable_p, insn_is_swappable_p, chain_contains_only_swaps,
mark_swaps_for_removal, swap_const_vector_halves, adjust_subreg_index,
permute_load, permute_store, adjust_extract, adjust_splat,
adjust_xxpermdi, adjust_concat, adjust_vperm, handle_special_swappables,
replace_swap_with_copy, dump_swap_insn_table,
alignment_with_canonical_addr, alignment_mask, find_alignment_op,
recombine_lvx_pattern, recombine_stvx_pattern,
recombine_lvx_stvx_patterns, rs6000_analyze_swaps,
make_pass_analyze_swaps): Move all code related to p8 swap optimizations
to file rs6000-p8swap.c.
* config/rs6000/rs6000-p8swap.c: New file.
* config/rs6000/t-rs6000: Add rule to build rs6000-p8swap.o.
* config.gcc: Add rs6000-p8swap.o to extra_objs for powerpc*-*-*
and rs6000*-*-* targets.

From-SVN: r250040

re PR fortran/70071 (ICE on wrong usage of a subscript triplet)

2017-07-06  Harald Anlauf  <anlauf@gmx.de>

PR fortran/70071
* array.c (gfc_ref_dimen_size): Handle bad subscript triplets.

2017-07-06  Harald Anlauf  <anlauf@gmx.de>

PR fortran/70071
* gfortran.dg/coarray_44.f90: New testcase.

From-SVN: r250039

PR c++/81204 - parse error with dependent template-name

PR c++/81204 - parse error with dependent template-name
* parser.c (cp_parser_lookup_name): Revert previous change.

From-SVN: r250037

Remove selftest dependency on C++ frontend

gcc/ChangeLog
* Makefile.in (selftest): Remove dependency on s-selftest-c++.

From-SVN: r250036

lto-wrapper.c (merge_and_complain): Do not merge fexceptions...

* lto-wrapper.c (merge_and_complain): Do not merge
fexceptions, fnon_call_exceptions, ftrapv, ffp_contract_, fmath_errno,
fsigned_zeros, ftrapping_math, fwrapv.
(append_compiler_options): Do not track these options.
(append_linker_options): Likewie

From-SVN: r250035

cgraphunit.c (cgraph_node::finalize_function): When !flag_toplevel_reorde set no_reorder flag.

* cgraphunit.c (cgraph_node::finalize_function): When
!flag_toplevel_reorde set no_reorder flag.
(varpool_node::finalize_decl): Likewise.
(symbol_table::compile): Drop no toplevel reorder path.

* lto-partition.c (lto_balanced_map): Do not check
flag_toplevel_reorder.

From-SVN: r250034