st/mesa: add fake ARB_copy_image support in Gallium

This support should be removed in favor of something that actually works
in all the weird cases. However this is simple and is enough to allow
Bioshock Infinite to render properly on nvc0.

Since the functionality is not implemented correctly, the extension will
not appear in the extension string and mesa will still return
INVALID_OPERATION for any glCopyImageSubData calls. In order to make use
of this functionality, run with
MESA_EXTENSION_OVERRIDE=GL_ARB_copy_image

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl: enable textureSize and texelFetch on GLSL ES 3.10 with MS samplers

Patch separates array samplers from the texture_multisample check so that we
can enable only [iu]sampler2DMS, [iu]sampler2DMSArray are not supported.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>

mesa: validate size parameters for glTexStorage*Multisample

v2: code cleanup
v3: check only dimensions, samples is checked separately later

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>

mesa: expose dimension check for glTex*Storage functions

This is done so that following patch can use it to verify dimensions
for multisample variants of glTex*Storage.

v2: move function to header, use bool instead GLboolean
v3: small changes, cleanup

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>

util/ra: (trivial) fix c99 loop variable initialization

Fails with old msvc otherwise.

util: (trivial) include c99_math.h in rounding.h

Needed for rint/rintf.

i965/bdw: Fix setting the instancing state for the SGVS element

When gl_VertexID or gl_InstanceID is used a 3DSTATE_VF_SGVS
instruction is sent to create a sort of element to store the generated
values. The last instruction in this chunk of code looks like it was
trying to set the instancing state for the element using the
3DSTATE_VF_INSTANCING instruction. However it was sending
brw->vb.nr_buffers instead of the element index. This instruction is
supposed to take an element index and that is how it is used further
down in the function so the previous code looks wrong. Perhaps
previously the number of buffers coincidentally matched the number of
enabled elements so the value was generally correct anyway. In a
subsequent patch I want to change a bit how it chooses the SGVS
element index so this needs to be fixed.

v2 [by Ben]
Remove stable 10.5 stable tag (it's too late now)
Commit update as follows:
The number of vertex buffers emitted is always <= the number of vertex elements.
To maximize reuse (actually, to minimize relocations - according to the code
comments), a vertex buffer is only emitted once, even when we setup multiple
components (3DSTATE_VERTEX_ELEMENT) from that buffer. This meant that the
previous code would use the wrong indexed element for these reuse cases. This
patch by itself prevents hangs on BSW in the linked bug. It doesn't make the
test pass, the remaining patches are needed for that.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91610
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>

util/ra: Make allocating conflict lists optional

Since i965 is now using make_reg_conflicts_transitive and doesn't need
q-value computations, they are disabled on i965.  They are enabled
everywhere else so that they get the old behavior.  This reduces the time
spent in eglInitialize() on BDW by around 10-15%.

Reviewed-by: Eric Anholt <eric@anholt.net>

i965/reg_allocate: Use make_reg_conflicts_transitive

Instead of adding transitive conflicts as we go, we now add regular
conflicts and them make them all transitive at the end.  This reduces
screen creation time substantially on BDW.  The time spent in eglInitialize
is reduced from 27.78 ms/call to 9.92 ms/call in debug mode and from 13.15
ms/call to 4.54 ms/call in release mode (about 65% in either case).

Reviewed-by: Eric Anholt <eric@anholt.net>

util/ra: Add a function for making all conflicts on a register transitive

Reviewed-by: Eric Anholt <eric@anholt.net>

util/bitset: Add a BITSET_FOREACH_SET macro

Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: Move varying slots and FS output names to shader_enums.h

They're used by glsl_to_nir.cpp, and I want to use them in TGSI-to-NIR as
well (our use of the var->index slot to store slot properties no longer
works since it got truncated).

The *_MAX defines are left in mtypes.h, because they depend on config.h.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: undo split out of create shader code

This code was split out into a separate function to be used also
by GL_EXT_separate_shader_objects which has since been removed from
Mesa, so move it back.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

freedreno: use fd_pipe_wait_timeout()

To properly support the case of waiting on a fence with a 0 timeout, we
still need to call down to the kernel.  Which requires the use of the
new fd_pipe_wait_timeout() API.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: fence fix

Don't take current timestamp/fence from current ring, as we might have
already rolled over to new rb.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

Add mesa.icd to the .gitignore

Since 4d7e0fa8c731776 this file is generated by the configure script.
Reviewed-by: Tapani Palli <tapani.palli@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

drirc: Add "Unigine Oil Rush" quirk (allow_glsl_extension_directive_midshader).

Appears to fix shader compilation. Tested by starting the client and observing
that the screen was correct after the trailers ran when previously, it was
blank. Play tested on amd64.

This was suggested by "Kuuchan" on the Steam forums:

https://steamcommunity.com/app/200390/discussions/0/540731690861139279/?insideModal=1#c594820656479479870

Acked-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Richard Yao <ryao@gentoo.org>

nir: Simplify feq(fneg(a), a)) -> feq(a, 0.0)

The positive and negative value of a float can only
be equal to each other if it is -0.0f and 0.0f.
This is safe for Nan and Inf, as -Nan != Nan, and -Inf != Inf
This gives no changes in my shader-db

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

nir: Simplify fne(fneg(a), a) -> fne(a, 0.0)

-NaN != NaN, and -Inf != Inf, so this should be safe.
Found while working on my VRP pass.

Shader-db results on my IVB:
total instructions in shared programs: 1698267 -> 1698067 (-0.01%)
instructions in affected programs:     15785 -> 15585 (-1.27%)
helped:                                36
HURT:                                  0
GAINED:                                0
LOST:                                  0

Some shaders was found to have the following pattern in NIR:
vec1 ssa_26 = fneg ssa_21
vec1 ssa_27 = fne ssa_21, ssa_26

Make that:
vec1 ssa_27 = fne ssa_21, 0.0f

This is found in Dota2 and Brutal Legend.
One shader is cut by 8%, from 323 -> 296 instructons in SIMD8

Signed-off-by: Thomas Helland <thomashelland90@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965/gen7: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/gen7_sol_state.c: In function 'gen7_upload_3dstate_so_decl_list':
mesa/src/mesa/drivers/dri/i965/gen7_sol_state.c:119:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (int i = 0; i < linked_xfb_info->NumOutputs; i++) {
                      ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965/gen6: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/gen6_vs_state.c: In function 'gen6_upload_push_constants':
mesa/src/mesa/drivers/dri/i965/gen6_vs_state.c:85:21: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
       for (i = 0; i < prog_data->nr_params; i++) {
                     ^
mesa/src/mesa/drivers/dri/i965/gen6_vs_state.c:92:17: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
   for (i = 0; i < prog_data->nr_params; i++) {
                 ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/brw_vs_surface_state.c: In function 'brw_upload_pull_constants':
mesa/src/mesa/drivers/dri/i965/brw_vs_surface_state.c:84:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = 0; i < prog_data->nr_pull_params; i++) {
                  ^
mesa/src/mesa/drivers/dri/i965/brw_vs_surface_state.c:89:21: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
       for (i = 0; i < ALIGN(prog_data->nr_pull_params, 4) / 4; i++) {
                     ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/brw_wm_surface_state.c: In function 'brw_upload_abo_surfaces':
mesa/src/mesa/drivers/dri/i965/brw_wm_surface_state.c:961:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (int i = 0; i < prog->NumAtomicBuffers; i++) {
                      ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/brw_wm_surface_state.c: In function 'brw_upload_ubo_surfaces':
mesa/src/mesa/drivers/dri/i965/brw_wm_surface_state.c:901:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (int i = 0; i < shader->NumUniformBlocks; i++) {
                      ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/brw_tex_layout.c: In function 'brw_miptree_layout_texture_array':
mesa/src/mesa/drivers/dri/i965/brw_tex_layout.c:560:25: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
       for (int q = 0; q < mt->level[level].depth; q++) {
                         ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/brw_state_cache.c: In function 'brw_try_upload_using_copy':
mesa/src/mesa/drivers/dri/i965/brw_state_cache.c:216:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = 0; i < cache->size; i++) {
                  ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/brw_primitive_restart.c: In function 'can_cut_index_handle_prims':
mesa/src/mesa/drivers/dri/i965/brw_primitive_restart.c:94:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (int i = 0; i < nr_prims; i++) {
                      ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/brw_draw_upload.c: In function 'brw_prepare_vertices':
mesa/src/mesa/drivers/dri/i965/brw_draw_upload.c:434:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = j = 0; i < brw->vb.nr_enabled; i++) {
                      ^
mesa/src/mesa/drivers/dri/i965/brw_draw_upload.c:557:17: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
   for (i = 0; i < nr_uploads; i++) {
                 ^
mesa/src/mesa/drivers/dri/i965/brw_draw_upload.c:569:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = 0; i < nr_uploads; i++) {
                  ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/brw_draw.c: In function 'brw_draw_destroy':
mesa/src/mesa/drivers/dri/i965/brw_draw.c:630:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = 0; i < brw->vb.nr_buffers; i++) {
                  ^
mesa/src/mesa/drivers/dri/i965/brw_draw.c:636:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = 0; i < brw->vb.nr_enabled; i++) {
                  ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

mesa/egl: Resolve GCC sign-compare warning.

mesa/src/egl/drivers/dri2/platform_drm.c: In function 'release_buffer':
mesa/src/egl/drivers/dri2/platform_drm.c:73:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++) {
                  ^
mesa/src/egl/drivers/dri2/platform_drm.c: In function 'has_free_buffers':
mesa/src/egl/drivers/dri2/platform_drm.c:87:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++)
                  ^
mesa/src/egl/drivers/dri2/platform_drm.c: In function 'dri2_drm_destroy_surface':
mesa/src/egl/drivers/dri2/platform_drm.c:199:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++) {
                  ^
mesa/src/egl/drivers/dri2/platform_drm.c: In function 'get_back_bo':
mesa/src/egl/drivers/dri2/platform_drm.c:224:21: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
       for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++) {
                     ^
mesa/src/egl/drivers/dri2/platform_drm.c: In function 'dri2_drm_swap_buffers':
mesa/src/egl/drivers/dri2/platform_drm.c:425:24: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
          for (i = 0; i < ARRAY_SIZE(dri2_surf->color_buffers); i++)
                        ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

mesa/gbm: Resolve GCC sign-compare warning.

mesa/src/gbm/main/backend.c: In function 'find_backend':
mesa/src/gbm/main/backend.c:70:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = 0; i < ARRAY_SIZE(backends); ++i) {
                  ^
mesa/src/gbm/main/backend.c: In function '_gbm_create_device':
mesa/src/gbm/main/backend.c:95:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = 0; i < ARRAY_SIZE(backends) && dev == NULL; ++i) {
                  ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

mesa/glx: Resolve GCC sign-compare warning.

mesa/src/glx/dri_common_query_renderer.c: In function 'dri2_convert_glx_query_renderer_attribs':
mesa/src/glx/dri_common_query_renderer.c:61:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = 0; i < ARRAY_SIZE(query_renderer_map); i++)
                  ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

mesa/glx: Resolve GCC sign-compare warning.

mesa/src/glx/dri_common.c: In function 'scalarEqual':
mesa/src/glx/dri_common.c:259:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = 0; i < ARRAY_SIZE(attribMap); i++)
                  ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/intel_screen.c: In function 'intel_screen_make_configs':
mesa/src/mesa/drivers/dri/i965/intel_screen.c:1222:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (int i = 0; i < ARRAY_SIZE(formats); i++) {
                      ^
mesa/src/mesa/drivers/dri/i965/intel_screen.c:1259:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (int i = 0; i < ARRAY_SIZE(formats); i++) {
                      ^
mesa/src/mesa/drivers/dri/i965/intel_screen.c:1291:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (int i = 0; i < ARRAY_SIZE(formats); i++) {
                      ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/intel_fbo.c: In function 'intel_validate_framebuffer':
mesa/src/mesa/drivers/dri/i965/intel_fbo.c:734:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = 0; i < ARRAY_SIZE(fb->Attachment); i++) {
                  ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

mesa: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/common/utils.c: In function 'driGetConfigAttrib':
mesa/src/mesa/drivers/dri/common/utils.c:457:19: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
     for (i = 0; i < ARRAY_SIZE(attribMap); i++)
                   ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/intel_screen.c: In function 'aub_dump_bmp':
mesa/src/mesa/drivers/dri/i965/intel_screen.c:125:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (int i = 0; i < fb->_NumColorDrawBuffers; i++) {
                      ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/intel_fbo.c: In function 'intel_blit_framebuffer_with_blitter':
mesa/src/mesa/drivers/dri/i965/intel_fbo.c:836:21: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
       for (i = 0; i < drawFb->_NumColorDrawBuffers; i++) {
                     ^
V2 (Thomas Helland):
  -Use unsigned instead of GLuint (trivial)

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/brw_wm_state.c: In function 'brw_color_buffer_write_enabled':
mesa/src/mesa/drivers/dri/i965/brw_wm_state.c:53:18: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
                  ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

i965: Resolve GCC sign-compare warning.

mesa/src/mesa/drivers/dri/i965/brw_draw.c: In function 'brw_postdraw_set_buffers_need_resolve':
mesa/src/mesa/drivers/dri/i965/brw_draw.c:390:22: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
    for (int i = 0; i < fb->_NumColorDrawBuffers; i++) {
                      ^

Signed-off-by: Rhys Kidd <rhyskidd@gmail.com>
Reviewed-by: Thomas Helland <thomashelland90@gmail.com>

glx: Fix __glXWireToEvent for BufferSwapComplete

In the DRI2 path this event is magically synthesized from the
corresponding DRI2 event, but with Present, the server sends us the
event itself. The DRI2 path fills in the serial number, send_event, and
display fields of the XEvent struct that the app sees, but the Present
path did not.

This is likely related to a class of crashes seen in gtk/clutter apps:

https://bugzilla.redhat.com/attachment.cgi?id=1032631

Note that the crashing instruction is looking up the lock_fns slot in
the Display *, and %rdi (holding the Display *) is 0x1.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

radeon/uvd: remove unused variables

Recent commits introduced new unused variable warnings, fix them.

Reviewed-by: Christian König <christian.koenig@amd.com>

nouveau: recognize tess stages in nouveau_compiler

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

tgsi: fix parsing of tessellation shader inputs/outputs

Tessellation control shaders write to outputs as OUT[ADDR[0].x][0], make
sure to parse the indirect dimension on outputs.

Also tess control inputs/outputs and tess eval input declarations need
to receive the same treatment as geometry shader inputs.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

tgsi: set implicit array size for tess stages

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa: move non-generic samples validation

The previous patch replaces the other use case.

V2: remove the validation from it old location.

Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

mesa: check samples > 0 for glTex*Multisample

The GL 4.5 spec says its an GL_INVALID_VALUE error if samples equals 0 for
glTexImage*Multisample and an GL_INVALID_VALUE error if samples < 1 for
glTexStorage*Multisample.

The spec says its undefined what happens if glTexImage*Multisample is passed
a samples value < 0 but we currently already produced a GL_INVALID_VALUE error
in this case, this is also consistent with the Nvidia binary.

Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

i965/vec4/nir: Emit single MOV to generate a scalar constant.

If an immediate is written to multiple channels, we can load it in a
single writemasked MOV.

total instructions in shared programs: 6285144 -> 6261991 (-0.37%)
instructions in affected programs:     718991 -> 695838 (-3.22%)
helped:                                5762

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

freedreno/a3xx: add s3tc texture format support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a3xx: fix up logic for handling block formats

This only appears in cubemaps which have have packed layers, so are very
sensitive to any layout disagreement between sw and hw.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a3xx: double the polygon offset value

A few other drivers do this, fixes the gl-1.4-polygon-offset piglit test

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: implement the color buffer 0 is integer rule for alpha-to-one/cov

The hardware checks for multisampling being enabled, but does not have
the rule about cbuf0 being an integer format. Only enable
alpha-to-one/alpha-to-coverage if cbuf0 is not an integer format.

Fixes piglits
  ext_framebuffer_multisample-int-draw-buffers-alpha-to-one
  ext_framebuffer_multisample-int-draw-buffers-alpha-to-coverage

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa: Raise INVALID_VALUE from glCreateShaderProgramv if count < 0

According to OpenGL version 4.5 and OpenGL ES 3.1 standards, section 7.3:
GL_INVALID_VALUE should be generated, if count is less than 0.

V2: Changed title, eased Open GL ES 3.1 restriction and added comments.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>

mesa: AtomicBufferBindings should be initialized to zero.

According to OpenGL specification version 4.5 table 23.46
and OpenGL ES specification version 3.1 table 20.31:
ATOMIC_COUNTER_BUFFER_START and ATOMIC_COUNTER_BUFFER_SIZE
should have the initial value of zero.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Erik Faye-Lund <kusmabite@gmail.com>

mesa: fix target error checking in glGetTexLevelParameter

With non-dsa functions we need to do target error checking before
_mesa_get_current_tex_object which would just call _mesa_problem without
raising GL_INVALID_ENUM error. In other places of Mesa, target gets checked
before this call.

Fixes failures in:
   ES31-CTS.texture_storage_multisample.APIGLGetTexLevelParameterifv.*

v2: do the target check also for dsa functions (Timothy)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>

gk110/ir: fix sched calculator to consider all registers in the ISA

GK110/GK208 have 256 registers, not 64. Find out the number of registers
from the target to avoid unnecessary iteration for pre-GK110.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa: rename texture function now that its static

Reviewed-by: Brian Paul <brianp@vmware.com>

glsl: add missing MS sampler builtin types for GLSL ES 3.10

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

mesa: Implement glMemoryBarrierByRegion

The function glMemoryBarrierByRegion is part of OpenGL ES 3.1
and OpenGL 4.5 core and compatibility profiles.

Signed-off-by: Marta Lofstedt <marta.lofstedt@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

nvc0: program smooth line width when multisampling is enabled

There are separate line widths for smooth and aliased lines. The smooth
one is selected when multisampling is enabled even if line smoothing
isn't explicitly turned on.

Fixes the ext_framebuffer_multisample-line-smooth piglits

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: bind a fake tess control program when there isn't one available

Apparently this is necessary in order for tess factors to work in a tess
eval program without a tess control program bound. Probably because it
uses the fake program's shader header to work out the number of patch
constants.

Fixes vs-tes-tessinner-tessouter-inputs

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

gm107/ir: avoid letting the lowering pass get out of sync

There's a lot of functionality duplicated in the gm107 lowering pass
from the nvc0 pass. As that one gets updated, the gm107 one falls
behind. Avoid this by sharing the code.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50,nvc0: take level into account when doing eng2d multi-layer blits

This fixes arb_get_texture_sub_image-get, and any situation where the 2d
engine was being used for multi-layer blits to a non-0 level.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>

st/mesa: also move yoffset to zoffset for 1d array textures

Do the same as in st_TexSubImage. This fixes
arb_get_texture_sub_image-get on llvmpipe when it is set to prefer
blits, and nouveau when it uses the 3d engine for blits.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

nir: Add a glsl_uint_type() wrapper.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>

freedreno/a3xx: add per-texture seamless cubemap control

The default is to enable seamless cubemap filtering, but there's a bit
to turn it off.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: add cube map array support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

freedreno/a4xx: fix srgb render targets

Also fixes mipmap level generation for srgb textures.

Signed-off-by: Rob Clark <robclark@freedesktop.org>

freedreno: update generated headers

Signed-off-by: Rob Clark <robclark@freedesktop.org>

scons: Always define __STDC_LIMIT_MACROS.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91591
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

freedreno: expose OES exts for float linear filtering

a4xx can do both float and half-float, while a3xx can only do half-float

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: disable tessellation on maxwell

The address calculations are all different (e.g. see GP), there appear
to be sync's in programs, and probably a bunch of other differences.
Just disable it for now.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nir: Add support for CSE on textures.

NIR instruction count results on i965:
total instructions in shared programs: 1261954 -> 1261937 (-0.00%)
instructions in affected programs:     455 -> 438 (-3.74%)

One in yofrankie, two in tropics.  Apparently i965 had also optimized all
of these out anyway.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

nir: Zero out texture instructions when creating them.

There are so many flags in textures, that the CSE pass would have a hard
time referencing the correct set when figuring out if two texture ops are
the same.  By zeroing, we can avoid that fragility.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

vc4: Move all of our fixed function fragment color handling to NIR.

This massively reduces our dependency on VC4-specific optimization passes.

shader-db:
total uniforms in shared programs: 32077 -> 32067 (-0.03%)
uniforms in affected programs:     149 -> 139 (-6.71%)
total instructions in shared programs: 98208 -> 98182 (-0.03%)
instructions in affected programs:     2154 -> 2128 (-1.21%)

vc4: Add a helper for making driver-specific NIR load_uniform for GL state

In order to move more of our lowering into NIR, we need the ability to
reference various pipeline state (like texture rectangle scaling factors
or blend colors), so we just set those up as a load_uniform with a big
offset to indicate that it's not within the shader's uniform storage and
is one of our state values.

nir: Don't try to scalarize unpack ops.

Avoids regressions in vc4 when trying to do our blending in NIR.

v2: Add the other unpack ops I meant to when writing the original commit
    message.

Reviewed-by: Matt Turner <mattst88@gmail.com>

nir: Add a nir_opt_undef() to handle csels with undef.

We may find a cause to do more undef optimization in the future, but for
now this fixes up things after if flattening.  vc4 was handling this
internally most of the time, but a GLB2.7 shader that did a conditional
discard and assign gl_FragColor in the else was still emitting some extra
code.

total instructions in shared programs: 100809 -> 100795 (-0.01%)
instructions in affected programs:     37 -> 23 (-37.84%)

v2: Use nir_instr_rewrite_src() to update def/use on src[0] (by Thomas
    Helland).
v3: Make sure to flag metadata dirties, and copy the swizzle and abs/neg
    over to src[0], too (by anholt).

Reviewed-by: Thomas Helland <thomashelland90@gmail.com> (v2)
Tested-by: Thomas Helland <thomashelland90@gmail.com> (v2)

gm107/ir: indirect handle goes first on maxwell also

Fixes fs-simple-texture-size.shader_test

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.6" <mesa-stable@lists.freedesktop.org>

nv30: add depth bounds test support for hw that has it

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50: add depth bounds test support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0: add depth bounds test support

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

docs/relnotes: document amdgpu, GL 4.1 and other new features

radeonsi: add all new VI PCI IDs including Fiji

radeonsi: revert a wrong DB bug workaround for VI

The bug was misunderstood. Besides that, the bug affects a DB feature we
don't use yet.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeon/uvd: implement HEVC support

add context buffer to fix H265 uvd decode issue.
fix H265 corruption issue caused by incorrect assigned ref_pic_list.

v2: disable interlace for HEVC
    add CZ sps flag workaround
    fix coding style

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>

radeon/vce: disable VCE dual instance for harvest part

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vce: implement VCE dual instance support

VCE dual instances are encoding in parallel, it needs two frames for
encoding with their own parameters in one IB. Master instance will check
the task info to find another frame, assign it to the slave instance

Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>

radeon/video: config encode stacked frame number based on HW

since VCE 3.0 with dual instances, we need stack frames for them.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vce: make reloc offset signed

We need a negative offset for FW 50.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>

radeon/vce: add config task and put task info into encoder v2

The config task has own task ID, extract the configuration functions
into config task.

v2 (chk): calculate offset automatically

Signed-off-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>

radeon/vce: fix VCE fail after rebase

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vce: add dual pipe support for VI

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vce: add new firmware support for VI and CI

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/vce: implement VCE two pipe support

v2: rebase by Marek

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/uvd: make 30M as minimum for MPEG4 dpb buffer size

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/uvd: recalculate dbp buffer size

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

radeon/video: add 4K support for decode/encode parameters

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>

gallium/radeon: add h264 performance HW decoder support

v2: -make tonga use new h264 performance HW decoder;
    -integrate it scaling buffer to msg_fb buffer

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

gallium/radeon: use VM for VCE

v2: (leo) add checking for driver backend
v3: (leo) change variable name from use_amdgpu to use_vm
v4: rebase by Marek

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>