Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 14:47:44 +0000 (15:47 +0100)]
remove 1st col
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 14:47:03 +0000 (15:47 +0100)]
redo as tables
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 14:45:38 +0000 (15:45 +0100)]
add Form, ordered set
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 14:43:00 +0000 (15:43 +0100)]
table plugin
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 14:42:28 +0000 (15:42 +0100)]
table plugin
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 14:41:48 +0000 (15:41 +0100)]
table plugin
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 14:41:05 +0000 (15:41 +0100)]
table plugin
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 14:39:13 +0000 (15:39 +0100)]
table format of keys
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 14:35:26 +0000 (15:35 +0100)]
auto-generated opcode groups for SV
Luke Kenneth Casson Leighton [Wed, 7 Oct 2020 14:34:06 +0000 (15:34 +0100)]
sv isatable prefix analyser
lkcl [Wed, 7 Oct 2020 13:35:35 +0000 (14:35 +0100)]
lkcl [Wed, 7 Oct 2020 13:18:56 +0000 (14:18 +0100)]
Jacob Lifshay [Wed, 7 Oct 2020 03:58:20 +0000 (20:58 -0700)]
fix div spec
Cole Poirier [Wed, 7 Oct 2020 01:18:32 +0000 (18:18 -0700)]
update csv column order to have opcode at beginning instead of end
Cole Poirier [Wed, 7 Oct 2020 01:14:05 +0000 (18:14 -0700)]
new deduped csv, should compare results with lkcl's
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 23:25:15 +0000 (00:25 +0100)]
remove carry columns
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 23:24:35 +0000 (00:24 +0100)]
remove carry columns
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 23:22:59 +0000 (00:22 +0100)]
remove carry columns
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 23:21:36 +0000 (00:21 +0100)]
remove carry columns
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 23:19:39 +0000 (00:19 +0100)]
remove SPR
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 23:18:06 +0000 (00:18 +0100)]
remove SPR
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 23:17:29 +0000 (00:17 +0100)]
dedupe opcodes
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 21:47:12 +0000 (22:47 +0100)]
uniquify opcodes
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 21:41:47 +0000 (22:41 +0100)]
uniquify opcodes
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 21:38:54 +0000 (22:38 +0100)]
uniquify opcodes
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 21:23:39 +0000 (22:23 +0100)]
uniquify opcodes
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 21:13:23 +0000 (22:13 +0100)]
uniquify opcodes
Luke Kenneth Casson Leighton [Tue, 6 Oct 2020 21:10:13 +0000 (22:10 +0100)]
add dvi
Cole Poirier [Tue, 6 Oct 2020 20:29:53 +0000 (13:29 -0700)]
add csv of deduplicated opcodes/registers
Jacob Lifshay [Tue, 6 Oct 2020 02:51:40 +0000 (19:51 -0700)]
working on fixing divde
Jacob Lifshay [Tue, 6 Oct 2020 02:12:55 +0000 (19:12 -0700)]
fix moduw spec
Jacob Lifshay [Tue, 6 Oct 2020 01:54:13 +0000 (18:54 -0700)]
fix modsw spec
Jacob Lifshay [Tue, 6 Oct 2020 01:00:50 +0000 (18:00 -0700)]
fix divweu bug
lkcl [Mon, 5 Oct 2020 15:20:45 +0000 (16:20 +0100)]
lkcl [Mon, 5 Oct 2020 11:58:57 +0000 (12:58 +0100)]
lkcl [Mon, 5 Oct 2020 11:57:41 +0000 (12:57 +0100)]
Jacob Lifshay [Sat, 3 Oct 2020 01:01:56 +0000 (18:01 -0700)]
working on fixing divwe. spec bugs
lkcl [Fri, 2 Oct 2020 21:43:33 +0000 (22:43 +0100)]
Luke Kenneth Casson Leighton [Thu, 1 Oct 2020 21:49:26 +0000 (22:49 +0100)]
add openpower linkedin post
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 21:36:31 +0000 (22:36 +0100)]
add I2C and rename SDRAM pins
Luke Kenneth Casson Leighton [Wed, 30 Sep 2020 18:14:47 +0000 (19:14 +0100)]
add large (nearly completed) 180nm layout
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 14:03:09 +0000 (15:03 +0100)]
add 2nd ioring ls180 iteration
lkcl [Mon, 28 Sep 2020 11:37:27 +0000 (12:37 +0100)]
Luke Kenneth Casson Leighton [Sun, 27 Sep 2020 22:17:24 +0000 (23:17 +0100)]
add corona first version of ls180
mePy2 [Sun, 27 Sep 2020 21:41:11 +0000 (22:41 +0100)]
Added the GitHub repo link to the page.
Luke Kenneth Casson Leighton [Sun, 27 Sep 2020 15:55:09 +0000 (16:55 +0100)]
renamed to circuitverse.mdwn
mePy2 [Sun, 27 Sep 2020 15:30:09 +0000 (16:30 +0100)]
Removed the “blahblah" section created earlier.
mePy2 [Sun, 27 Sep 2020 15:23:07 +0000 (16:23 +0100)]
mePy2 [Sun, 27 Sep 2020 15:19:58 +0000 (16:19 +0100)]
mePy2 [Sun, 27 Sep 2020 15:18:25 +0000 (16:18 +0100)]
mePy2 [Sun, 27 Sep 2020 15:15:52 +0000 (16:15 +0100)]
lkcl [Sun, 27 Sep 2020 15:02:12 +0000 (16:02 +0100)]
lkcl [Sat, 26 Sep 2020 21:07:54 +0000 (22:07 +0100)]
lkcl [Sat, 26 Sep 2020 21:07:03 +0000 (22:07 +0100)]
Luke Kenneth Casson Leighton [Fri, 25 Sep 2020 12:48:37 +0000 (13:48 +0100)]
add descriptions to ls180 pinouts
Luke Kenneth Casson Leighton [Fri, 25 Sep 2020 12:25:06 +0000 (13:25 +0100)]
add ls180.mdwn auto-generated
Luke Kenneth Casson Leighton [Fri, 25 Sep 2020 12:21:48 +0000 (13:21 +0100)]
update UART page
Luke Kenneth Casson Leighton [Fri, 25 Sep 2020 10:28:01 +0000 (11:28 +0100)]
add XDC2020 and OpenPOWER NA 2020
Luke Kenneth Casson Leighton [Fri, 25 Sep 2020 10:26:59 +0000 (11:26 +0100)]
add rust users discussion
Luke Kenneth Casson Leighton [Thu, 24 Sep 2020 23:18:36 +0000 (00:18 +0100)]
add i2c litex gateware link
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 21:52:21 +0000 (22:52 +0100)]
add phoronix article
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 10:51:20 +0000 (11:51 +0100)]
whoops pseudocode for divwe / divde checking wrong half of result
must check the *upper* half which of course is inverted numbering
in PowerISA sigh
lkcl [Mon, 21 Sep 2020 13:57:30 +0000 (14:57 +0100)]
lkcl [Mon, 21 Sep 2020 13:57:09 +0000 (14:57 +0100)]
Cesar_Strauss [Mon, 21 Sep 2020 10:04:04 +0000 (11:04 +0100)]
Update my home page with the recent new tasks
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 09:43:17 +0000 (10:43 +0100)]
add flexgripplus
Luke Kenneth Casson Leighton [Fri, 18 Sep 2020 11:01:37 +0000 (12:01 +0100)]
tidyup nlnet page, add bug links
Luke Kenneth Casson Leighton [Wed, 16 Sep 2020 15:59:27 +0000 (16:59 +0100)]
add xdc2020 tex
Luke Kenneth Casson Leighton [Wed, 16 Sep 2020 14:12:56 +0000 (15:12 +0100)]
move openpowerna .tex to conferences directory
Luke Kenneth Casson Leighton [Tue, 15 Sep 2020 10:04:10 +0000 (11:04 +0100)]
add slbia tlbie opcodes and move dcbz to new MMU FU
programmerjake [Mon, 14 Sep 2020 16:33:01 +0000 (17:33 +0100)]
Luke Kenneth Casson Leighton [Sun, 13 Sep 2020 12:55:03 +0000 (13:55 +0100)]
decode dcbz correctly
programmerjake [Fri, 11 Sep 2020 01:51:20 +0000 (02:51 +0100)]
programmerjake [Fri, 11 Sep 2020 01:33:13 +0000 (02:33 +0100)]
programmerjake [Thu, 10 Sep 2020 22:27:01 +0000 (23:27 +0100)]
programmerjake [Thu, 10 Sep 2020 20:36:01 +0000 (21:36 +0100)]
programmerjake [Thu, 10 Sep 2020 19:37:25 +0000 (20:37 +0100)]
programmerjake [Thu, 10 Sep 2020 17:49:10 +0000 (18:49 +0100)]
start adding circuitjs stuff for bug 488
programmerjake [Thu, 10 Sep 2020 17:46:59 +0000 (18:46 +0100)]
Luke Kenneth Casson Leighton [Thu, 10 Sep 2020 11:57:56 +0000 (12:57 +0100)]
add NLnet PET link
Luke Kenneth Casson Leighton [Thu, 10 Sep 2020 11:32:42 +0000 (12:32 +0100)]
add more openpower2020 slides
Luke Kenneth Casson Leighton [Thu, 10 Sep 2020 11:02:53 +0000 (12:02 +0100)]
add additional vhdl-vs-nmigen screenshots to openpower2020
Luke Kenneth Casson Leighton [Wed, 9 Sep 2020 20:07:03 +0000 (21:07 +0100)]
more slides, add PowerISA decoder screenshot
Luke Kenneth Casson Leighton [Wed, 9 Sep 2020 13:38:13 +0000 (14:38 +0100)]
more slides in openpower 2020
Luke Kenneth Casson Leighton [Wed, 9 Sep 2020 11:39:30 +0000 (12:39 +0100)]
add openpower 2020 slides presentation (texstudio)
projects / libreriscv.git / log