cpu, sim-se: don't wake up threads that are awake in futex

FutexMap::wakeup is called when the futex(TGT_FUTEX_WAKE syscall is done.

FutexMap maintains a list of sleeping threads for each futex address
added on FutexMap::suspend, and entries are removed from the list
at FutexMap::wakeup.

The problem is that this system was not taking into account that threads
can be woken up by memory accesses to locked addresses via the path:

SimpleThread::activate
BaseSimpleCPU::wakeup
AbstractMemory::checkLockedAddrList
AbstractMemory::access
DRAMCtrl::recvAtomic
CoherentXBar::recvAtomicBackdoor
SimpleExecContext::writeMem

which happens on trivial pthread examples on ARM at least. The instruction
that locked memory in those test cases was LDAXR.

This could lead futex(TGT_FUTEX_WAKE to awake a thread that is already
awake but is first on the sleeping thread list, instead of a sleeping one,
which can lead all threads to incorrectly sleep and in turn to
"simulate() limit reached".

To implement this, ThreadContext::activate return now returns a boolean
that indicates if the state changed. suspend and halt are also modified
to also return a boolean in the same case for symmetry, although this is
not strictly necessary for the current patch.

Change-Id: Ia6b4d3e6148c64721d810b8f1fffaa208a394b06
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21606
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: fix futexFunc TGT_FUTEX_WAIT always selects bitset

Change-Id: I3e2bd1dd34d7cc00b2685547ab74b56bd8126128
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21605
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Add string constructors which delegate to const char * ones.

Change-Id: I22d88111409fc477c135b15c8f898adad4f6d4ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21502
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

cpu: Apply the ARM TLB rework to the O3 checker CPU.

The TLBs now create the stage 2 MMUs as children, and since those are
specialized for instruction and data, the CPU needs to use ArmITB or
ArmDTB instead of ArmTLB which is the base class without an MMU. This
was changed for the BaseCPU and SimpleCPU checker already, but the TLBs
are added in the O3 checker CPU as well.

Change-Id: I498f247f376c8721fb70ce26c0f1b0815b12fe2d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22039
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Drop sysctl support if built against glibc

Since glibc 2.30 the sysctl() function has been declared deprecated and
it will be deleted in future versions. This patch removes the support
for the sysctl system call in SE mode (which is currently serviced
calling the sysctl() function) if gem5 is built against glibc, keeping
it with other libc implementations, as a temporary measure to prevent
the generation of a compilation error. Note that this system call in
gem5 is only supported for the arm/freebsd architecture.

Change-Id: Ie5fcb983d15c0a27c7820d24250d7ae5dbe12355
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21519
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Clean setupBootLoader signature

This is because the bus parameter is not used anymore

Change-Id: I27aa8cc064904a6e3e0376f61eb7db74ea1a4d6c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22002
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

configs: Do not assume bootmem is a System child

As far as I can see bootmem is used in Arm systems only.

With

https://gem5-review.googlesource.com/c/public/gem5/+/21604

bootmem has been moved from system to system.realview.
This patch fix things by removing the assumption that the bootmem
SimObject lives under the system.
It is now trying to getattr a reference of the bootmem.
It is the ISA specific system builder's duty to bind the bootmem
reference (_bootmem) to the real bootmem object

Change-Id: I1e7405b5cb186de13c44bfd93fb4c8a1a5447f24
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22001
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm, configs: Using _on_chip_memory for on chip memory

This patch is pulling the on-chip memory outside of the on_chip_devices
list.
The external interface will be more or less the same: configuration
scripts will still use the attachOnChipIO method; a new kw argument has
been added in order to store mem_ports.

We want to provide to on-chip memory the same mechanism used when
collecting on-chip dma ports. This is needed when using Ruby, since
we need to pass a non None mem_ports to prevent the bootmem to be
wired to the bus.

Change-Id: Ifc519c3072dc5de1530772c70c80dc2094e2c54c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22000
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Apply the ARM TLB rework to the checker CPU.

The TLBs now create the stage 2 MMUs as children, and since those are
specialized for instruction and data, the CPU needs to use ArmITB or
ArmDTB instead of ArmTLB which is the base class without an MMU. This
was changed for the BaseCPU already, but the TLBs are added in the
checker CPU as well.

Change-Id: Ide8ce950622b40f69c37bbe2ea0d22295b76d7a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21979
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Add Giacomo Travaglini as an Arm maintainer

I have been delegating a lot of changes to Giacomo T for a long time,
making him a de facto Arm co-maintainer. Make this official by adding
him to the list of maintainers.

Change-Id: I69c53316e2fc6ca162d07ac2d167ac2ae2b6bbee
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21899
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs.

This regularizes the TLB setup in the CPU so that ARM is no longer a
special case with extra objects.

Change-Id: I739b82578ff74f8f9777cd7e34cd5227b47b186c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21842
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch: Remove the "interrupts.hh" switching header file.

That switching header is no longer necessary since everything outside
of the ISA can use the BaseInterrupts class.

Change-Id: Ie3ed45c38fec24234ff51fb05ba94f6f3cd02afd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20832
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch: Make a base class for Interrupts.

That abstracts the ISA further from the CPU, getting us a small step
closer to being able to build in more than one ISA at a time.

Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

dev-arm: Check for gem5 extensions in GicV2

Using GicV2 without setting the gem5_extensions parameter in a
config  with more than 8 is not allowed to prevent overflow of
the 8-bit mask.

Change-Id: I780c6985e8f44ed780b4f74f9a27805124e23a7b
Signed-off-by: Tiago Mück <tiago.muck@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19288
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Added GTests for base/bitfield.hh

In addition to the tests, a more detailed explanation of how
"insertBits(..)" functions has been included in its doxygen
documentation. The previous explanation was ambigious and led to
confusion.

Change-Id: I2ae8608733ebaa8f8f726cbb3a2cd8639b69c6b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21700
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch: Get rid of the unused GenericTLB.

Nothing is using it, and it's actually not use*able* at the moment
because it doesn't have implementations for all the pure virtual
methods that exist in the BaseTLB class.

Change-Id: I03d47c2e116f354c7247a2fa19a9f33dfe4c5eec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21841
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Turn the stage 2 ARM MMUs from params to children.

These aren't referred to in the C++, so there's no reason for them to
be parameters. By making them children, they can still be modified,
replaced wholesale, or even replaced by an entirely different object
to, for instance, mask them when they're not needed.

Change-Id: Ic7f144a3cd3d1fca12fec220918aa72af885f61c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21839
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Turn the local APIC Interrupts class into a SimObject.

It will no longer be a PioDevice or a ClockedObject, but will carry
forward the little bits and pieces of those classes that it was using.
Those are a PIO port for memory mapped register accesses, and a clock
domain parameter for setting the apic tick frequency.

This brings the x86 Interrupts class in line with the Interrupts of the
other ISAs so that they can inherit from a standard base class.

Change-Id: I6b25fa21911b39a756e0cf9408c5489a81d6ca56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20829
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Added GTests for base/atomicio.cc

Change-Id: I586a06c70f4e7331b4a31208ef7831e8473509c5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21699
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add classes that encapsulate a channel address

There are cases where the memory system needs to reason about
channel-local addresses. These are currently represented using the
Addr and AddrRange classes. This is not ideal since it doesn't provide
any type safety when working with global addresses and channel-local
addresses. This is particularly problematic when porting existing
components to work in multi-channel configurations.

This changeset introduces the new ChannelAddr and ChannelAddrRange
classes. These classes encapsulate channel-local addresses in a
contiguous address space. These can, for example, be used in a memory
controller to represent a flat address space when calculating timings
or in a sectored cache.

Change-Id: I45d4061ebc8507a10d0a4577b28796dc5ec7a469
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21600
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Delete the MessageReq and MessageResp memory commands.

Now that Message*Port is gone, there are no users of these two memory
commands. They can now be deleted, simplifying the memory system
slightly.

Change-Id: If157dade4a3fb2610756c2ee81dc0c3fac670a26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20824
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Don't force the ArmISA::TLB in vtophys.cc.

The only reason the TLB pointer is being cast to an ArmISA::TLB is so
that it can call a version of translateFunctional which takes more
arguments, when the standard version of translateFunctional just calls
that underlying function with the same arguments.

Change-Id: I3ffd3a8ecc2dda91ddca77f516e2b2ac7313a227
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21840
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

cpu: Clean up some style issues in pc_event.(hh|cc).

The record_t typedef isn't all that helpful, and is also not consistent
with gem5 style. The map_t style is more useful but is also not
compliant. This change eliminates the first typedef and replaces the
second with a type called Map.

There are some other small style fixups added in as well, like making
the member variable pc_map pcMap.

Change-Id: I8ffea529004fd6d5b42fdc60250804e2e4987e88
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21781
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Get rid of load count based events.

This was initially added in 2003 and only supported in the simple CPUs.
It's oddly specific since there are no other similar event queues for,
for instance, stores, branches, system calls, etc.

Given that this seems like a historical oddity which is only partially
supported and would be very hard to support on more diverse CPU types
like KVM or fast model which don't generally have hooks for counts of
specific instruction types.

Change-Id: I29209b7ffcf896cf424b71545c9c7546f439e2b9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21780
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add addIntlvBits to AddrRange

This method performs the opposite operation of removeIntlvBits and can
be used to transform a channel-local address to a global PA.

Change-Id: I2fab587d7c094597e52422305775ac7f31efba34
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21599
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Using scoped string in DPRINTFNR

We would otherwise need to add a using namespace std wherever we
use DPRINTFNR.

Change-Id: I30bf9ba474408133abded66141f6dc96dfdba8d6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21821
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Fix gem5.fast compilation

Change-Id: I86c83e8622ae5a88ff802ccb1cb919194c1251ef
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21820
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,base,sim: Move Process loader hooks into the Process class.

This code was originally in the ObjectFile class, but not all object
files will become Processes. All Processes will ultimately come from
ObjectFiles though, so it makes more sense to put that class there.

Change-Id: Ie73e4cdecbb51ce53d24cf68911a6cfc0685d771
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21468
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Use a std::function to handle MSI completion.

This removes the recvResponse callback from the IntMasterPort, and
makes it easier to handle the default case where we just need to clean
up the Packet.

Change-Id: I8bcbfee0aaf68b12310d773f925c399fc87ea65d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20828
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

arch,base: Restructure the object file loaders.

This change creates a distinction between object files which hold
executable code, and flat files which don't. The first type of files
have entry points, symbols, etc., while the others are just blobs which
can be shoved into memory. Rather than have those aspects but stub
them out, this change creates a new base class which simply doesn't
have them.

This change also restructures the ELF loader since it's main function
was quite long and doing multiple jobs.

It stops passing the architecture and operating system to the
ObjectFile constructor, since those might not be known at the very top
of the constructor. Instead, those default to Uknown*, and then are
filled in in the constructor body if appropriate. This removes a lot
of plumbing that was hard to actually use in practice.

It also introduces a mechanism to collect generic object file formats
so that they can be tried one by one by the general createObjectFile
function, rather than listing them all there one by one. It's unlikely
that new types of object files will need to be added in a modular way
without being able to modify the core loader code, but it's cleaner to
have that abstraction and modularization like is already there for
process loaders.

Finally, to make it possible to share the code which handles zipped
files for both true object files and also files which will be loaded
into memory but are just blobs, that mechanism is pulled out into a
new class called ImageFileData. It holds a collection of segments
which are set up by the object file and may refer to regions of the
original file, buffers maintained elsewhere, or even nothing to support
bss-es. shared_ptr is used to make it easier to keep track of that
information without having to do so explicitly or worry about deleting
a buffer before everyone was done using it.

Change-Id: I92890266f2ba0a703803cccad675a3ab41f2c4af
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21467
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

cpu: Delete the unused sched_break_pc(_sys) functions.

Change-Id: I2adae2858897e665fd28cfe9de3fdcf95ffc2a2e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21779
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Make LFENCE a serializing instruction

According to the Intel SDM, no instruction following an LFENCE can begin
execution until after the LFENCE has executed. (This is
less strict than an actual serializing instruction, such as CPUID.)

Serializing instructions (per intel SDM Volume 3A Chapter 8.3) ensure
that no future instruction is fetched until after the serializing
instruction is completed.

By contrast, LFENCE (and other memory-ordering instructions) allows
future instructions to have been fetched; it just prohibits them from
being executed.

Change-Id: If89fcb552192326ab69a581f57d71c95cf5d90e7
Signed-off-by: Isaac Richter <isaac.richter@rochester.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10321
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Carve out a portion of VExpress_GEM5 for the bootloader

This patch is carving out a portion of VExpress_GEM5 memory for the
bootloader. Prior to this patch this was only happening
conditionally/dynamically via the setupBootLoader call.  With this patch
the region is always present and the setupBootLoader doesn't instantiate
memory, it is only setting up some bootloader parameters.

Change-Id: Iaa5cdf471b14e8faa37353a25631bf7c6fc64afc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21604
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add simpleSystem helper to generate devices.SimpleSystem

This patch will make it possible to generate a SimpleSystem inheriting
from a configurable base class. More practically it will be possible to
inherit from a baremetal System (ArmSystem) rather than from a
LinuxArmSystem

Change-Id: I11553ae8045519059e159c555c6c9141bb4519b7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21603
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim,cpu: Get rid of the unused instEventQueue.

This queue was set up to allow triggering events based on the total
number of instructions executed at the system level, and was added in
a change which added a number of things to support McPAT. No code
checked into gem5 actually schedules an event on that queue, and no
code in McPAT (which seems to have gone dormant) either downloadable
from github or found in ext modify gem5 in a way that makes it use
the instEventQueue.

Also, the KVM CPU does not interact with the instEventQueue correctly.
While it does check the per-thread instruction event queue when
deciding how long to run, it does not check the instEventQueue. It will
poke it to run events when it stops for other reasons, but it may (and
likely will) have run beyond the point where it was supposed to stop.

Since this queue doesn't seem to actually be used for anything, isn't
being used properly in all cases anyway, and adds overhead to all the
CPU models, this change eliminates it.

Change-Id: I0e126df14788c37a6d58ca9e1bb2686b70e60d88
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21783
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tiago Mück <tiago.muck@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: De-x86ify the IntMasterPort.

The devices which host an IntMasterPort are very specific to x86 at the
moment, but the ports don't have to be. This change moves
responsibilities around so that the x86 specific aspects are handled
in the device, and the ports themselves are ISA agnostic.

Change-Id: I50141b66895be7d8f6303605505002ef424af7fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20827
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

Tests: Added GTests for base/callback.cc

Change-Id: Icebd0fdec4be86e0f0fd86ef58f52ddbfdf8d714
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21619
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Simplify and consolidate the code that assembles an MSI on x86.

There is no interrupt response message, and so no need for a function
which would construct one. The other functions which construct the
request can be consolidated since the work being done by each is
incremental. The template parameters can be used to support multiple
types and offsets in a single function, and since that function also
doesn't have to do much work, it makes sense to do everything in one
shot.

Change-Id: I41b202a263a697c5ada6817f3ab2a4728281b894
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20826
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

fastmodel: Expose all CPU communication ports from the GIC.

The unconnected CPU ports/sockets still need to be connected for TLM to
be happy, so this change also adds a terminator module which finds all
unbound sockets, creates pair sockets for them to connect to, binds
everything together, and implements the target interface with a dummy
stub that will complain and crash gem5 if it ever gets called.

This will allow us to use the same GIC model to connect an arbitrary
number of cores, up to the architected limit of 256.

Change-Id: Iaa83fe4f023217dc91a3734b31f764fc4176130e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21500
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Updating contributing.md to discuss Gerrit guidelines

Change-Id: I2449d4b0384f33d9635fc2a314a24341816dab1d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21419
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: set the second chance to false when inserting a block

Modify second chance replacement policy so that entries are inserted
without a second chance. Previously, the second chance bit was set
to true when a cache line was inserted. So the cache line would gain
its second chance when inserting. This is wrong because the cache
block will only get a second chance when it hits.

Here's a quoted citation for the second chance replacement policy:
"Whenever the algorithm examines a  page entry, it extracts the associated
usage bit and enters it into the high-order position of a k-bit shift
register after shifting the contents of the register one bit-position
lower. Then if the shift register is nonzero, the page is retained; if the
shift register is zero, the page is replaced by the new page. In either
case the usage bit for the page is turned off and the circular list
pointer is advanced."
(A Paging Experiment with the Multics System, FJ Corbato, 1968)

Change-Id: I0d07e56aa16c67dd36e0d490c3f457f91e46f320
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20882
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-cache: Fixed a bug in MRU replacement policy

The lastTouchTick is set to 0 when instantiate. This will cause the
candidate[0] to get evicted over and over again in MRU replacement
policy. To resolve this, break the search loop whenever it finds a
cold cache line.

Change-Id: I33aa57ebe0efca15986f62c3ae10a146bd2b779f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20881
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>

x86: Stop using and delete the x86 IntDevice class.

Most of its functionality has been exported already. This change makes
the two classes which were inheriting IntDevice create an IntMasterPort
themselves.

Change-Id: I73d17cd79cf8252b0e26dd2576f552bf9054adf4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20825
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,base: Separate the idea of a memory image and object file.

A memory image can be described by an object file, but an object file
is more than a memory image. Also, it makes sense to manipulate a
memory image to, for instance, change how it's loaded into memory. That
takes on larger implications (relocations, the entry point, symbols,
etc.) when talking about the whole object file, and also modifies
aspects which may not need to change. For instance if an image needs
to be loaded into memory at addresses different from what's in the
object file, but other things like symbols need to stay unmodified.

Change-Id: Ia360405ffb2c1c48e0cc201ac0a0764357996a54
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21466
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-ruby: Allow Ruby to use all replacement policies in Classic

Add support in Ruby to use all replacement policies in Classic.
Furthermore, if new replacement policies are added to the
Classic system, the Ruby system will recognize new policies
without any other changes in Ruby system. The following list
all the major changes:

  * Make Ruby cache entries (AbstractCacheEntry) inherit from
    Classic cache entries (ReplaceableEntry). By doing this,
    replacement policies can use cache entries from Ruby caches.
    AccessPermission and print function are moved from
    AbstractEntry to AbstractCacheEntry, so AbstractEntry is no
    longer needed.

  * DirectoryMemory and all SLICC files are changed to use
    AbstractCacheEntry as their cache entry interface. So do the
    python files in mem/slicc/ast which check the entry
    interface.

  * "main='false'" argument is added to the protocol files where
    the DirectoryEntry is defined. This change helps
    differentiate DirectoryEntry from CacheEntry because they are
    both the instances of AbstractCacheEntry now.

  * Use BaseReplacementPolicy in Ruby caches instead of
    AbstractReplacementPolicy so that Ruby caches will recognize
    the replacement policies from Classic.

  * Add getLastAccess() and useOccupancy() function to Classic
    system so that Ruby caches can use them. Move lastTouchTick
    to ReplacementData struct because it's needed by
    getLastAccess() to return the correct value.

  * Add a 2-dimensional array of ReplacementData in Ruby caches
    to store information for different replacement policies. Note
    that, unlike Classic caches, where policy information is
    stored in cache entries, the policy information needs to be
    stored in a new 2-dimensional array. This is due to Ruby
    caches deleting the cache entry every time the corresponding
    cache line get evicted.

Change-Id: Idff6fdd2102a552c103e9d5f31f779aae052943f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20879
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,base: Stop loading the interpreter in ElfObject.

The interpreter is a separate object file, and while it's convenient to
hide loading it in the code which loads the main object file, it breaks
the conceptual abstraction since you only asked it to load the main
object file.

Also, this makes every object file format reimplement the idea of
loading the interpreter. Admittedly only ELF recognizes and sets up
an interpreter, but other formats conceptually could too.

This does move that limitted hypothetical redundancy out of the object
file formats and moves it into the process objects, but I think
conceptually that's where it belongs. It would also probably be pretty
easy to add a method to the base Process class that would handle
loading an image and also the interpreter image.

This change does not (yet) separate reading symbol tables.

Change-Id: I4a165eac599a9bcd30371a162379e833c4cc89b4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21465
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch-arm: Move generateDtb to ArmSystem

This is aligning with the fact that dtb autogeneration is already
possible with an ArmSystem.

Change-Id: I72149927ee70d29458f8718a03845bb293c12145
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21602
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm, configs: Remove RealViewPBX platform

This is an old unused platform. We should support VExpress_GEM5 based
platforms only.

Change-Id: If9c29047b2d068992dfbbe0dc268c70b788cce5f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21601
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch, base: Stop assuming object files have three segments.

The ObjectFile class has hardcoded assumptions that there are three
segments, text, bss and data. There are some files which have one
"segment" like raw files, where the entire file's contents are
considered a single segment. There are also ELF files which can have
an arbitrary number of segments, and those segments can hold any
number of sections, including the text, data and/or bss sections.

Removing this assumption frees up some object file formats from having
to twist themselves to fit in that structure, possibly introducing
ambiguities when some segments may fulfill multiple roles.

Change-Id: I976e06a3a90ef852b17a6485e2595b006b2090d5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21463
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

fastmodel: Export GICV3Comms directly.

This lets us avoid having to have two levels of bridging and twice as
many ports on both the CPU and GIC side. The direct communication ports
can be instantiated and connected using array syntax, where the bridges
require instantiating each bridge individually and wiring them up one
at a time with a lot of boilerplate/duplicate code.

Change-Id: I815ee47bcd19994e46a5220e0c23e89c497d7aa5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21050
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

tests, misc: Updating TESTING.md to describe running unit tests

Previously we did not have any documentation discussing how gem5's GTests
were built and executed. TESTING.md has thereby been updated to highlight
how this is done. These unit tests should be run prior to each new
submission to Gerrit. This has been noted in TESTING.md also.

Change-Id: If5867fa0a2e4f6ea0921191a51e779c19a28117a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21479
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Migrated refcnt.cc test from src/unitttest to a gtest

refcnt.cc was previously tested in src/unittest/refcnttest.cc. This has
now been translated into a GTest as faithfully to the original as
possible.

Change-Id: I51f7a3d1e0a85b128c4eebd97cfe79b87406dc29
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21499
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

system-arm: Initialize ICC_SRE_EL3 register of all CPUs

Fix a bug that only CPU0 initialized ICC_SRE_EL3 register.

Change-Id: I625c9a25bada80b864e5eb5a8b8be14ee324b801
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21539
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-mips,arch-riscv,base: Get rid of the unused HexFile class.

A pointer to it was set up in the MIPS and RISCV system classes, but
nothing ever set that pointer. The class was put in base/loader, but
didn't have anything to do (as far as I can see) with loading anything
it had a loadSegments method, but was not a subclass of ObjectFile.

Change-Id: I4b711a31df20e20ffc306709227f60aa020fca15
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21464
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

base: Rename Section to Segment, and some of its members.

ELF is, in my opinion, the most important object file format gem5
currently understands, and in ELF terminolgy the blob of data that
needs to be loaded into memory to a particular location is called a
segment. A section is a software level view of what's in a region
of memory, and a single segment may contain multiple sections which
happen to follow each other in memory.

Change-Id: Ib810c5050723d5a96bd7550515b08ac695fb1b02
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21462
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

base: Get rid of the unused global pointer in object files.

This was only ever read from Alpha, and nothing ever set it.
It defaulted to zero, so this change just propogates that value through
to the Alpha Process class.

Change-Id: I569cf9d61a37322dbd88de1038a2af74c64bbe7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21461
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Ensure %p format arguments are printed as pointers.

If the %p format is used, char * arguments should be printed as the
hex value of their pointer, not as strings. Unfortunately blindly
passing them to an ostream using << will not do that. This change adds
some casting in that case to ensure that they're treated as numbers and
not as strings.

Change-Id: If02bae6d5e468b352266702fcba62b6beddffcbd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21459
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Make CortexA76x1's interrupts use gem5's mechanisms.

This makes it easier to wire up CPUs to the interrupt controller, and
makes things more modular.

Change-Id: I8d3ab26e4bb588b8efb198ed145d0f58b7ee04cb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21049
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Isolate ISA related object lists

Some objects are not compiled when using NULL ISA, and therefore
their object lists cannot exist.

Change-Id: I93ec576229916c892de50bb6c73cd602e18a3654
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21439
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

kvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCR

Those registers are 32-bit instead of 64 in the KVM API.

The Linux kernel 5.2 linux/Documentation/virtual/kvm/api.txt contains:

    0x6020 0000 0010 00d4 FPSR        32  fp_regs.fpsr
    0x6020 0000 0010 00d5 FPCR        32  fp_regs.fpcr

The register itself is 64-bit in the ARM manual, but the top 32 are
RES0.

This fixes the following error when running ARM KVM early in the
simulation:

panic: KVM: Failed to set register (0x60300000001000d4) value
(errno: 22)

Change-Id: I8fe6e12df4809992173200a42e3ce5414748bdad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21300
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

config: skip access to branchPred in ARM KVM

Prevents runtime error:

AttributeError: object 'ArmV8KvmCPU' has no attribute 'branchPred'

Change-Id: Ic5765fd560381cbacc2fa2fd2e6f79d98433c535
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21299
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: ELF segment types are not bitfields.

The ELF segment type had been checked by bitwise &-ing it with the
PT_LOAD constant to check if it was loadable. This is incorrect. The
value is a flat integer, with different values selecting different
types of segments.

Change-Id: I644dd985bda4ad2d992557c90ffe8048c0ae6aac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21460
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

kvm: Rename gettid() to build with glibc 2.30+

glibc 2.30 introduced the function gettid() in sys/types.h to return the
caller's thread ID. In order to avoid conflicts, the already present
gettid() functions have been renamed to sysGettid(). This fixes a
compilation error with X86 arch.

Change-Id: I76c971465fc4b50e4decde8303185439082b2378
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21379
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Remove unused variable

The variable *sys in dram_ctrl.cc was only used in an assert() check,
therefore it has been removed to allow building gem5.fast without
errors. A typo in a comment in abstract_mem.hh has also been corrected.

Change-Id: I2663545449ecfdb5a27c3574b79dd42beb4a49c8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21380
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

tests: Fix a minor bug in fixture.py

debug is a part of test_log object.

Signed-off-by: Ayaz Akram <yazakram@ucdavis.edu>
Change-Id: I56d950483c1d86b76b4f652741d2323c1b078e3e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19768
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev, misc: Fixing "may be used unitialized" compilation error

When compiling using "scons build/X86/base", "error: 'tx_queue_size'
may be used uninitialized in this function" is received (cc1plus:
all warnings treated as errors). tx_queue_size is now initialized
to zero to avoid this compilation error.

Change-Id: I0e2a4fd9ad6053c4c4124c83da9a7919778bcc52
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21399
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: Fix invalid delete of params on clone

The params pointer is kept by the SimObject and should not be deleted
until gem5 exits. Added a to do to remember this object is leaked.

Change-Id: I46cc23a09e4e9b6bc2fdcd961148324c41820815
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18068
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>

arch-arm: Annotate CM flag in AA64 CM Instructions

DC ZVA instruction is not classified as a cache maintenance instruction,
and therefore its execution cannot cause this field to be set to 1.

Change-Id: I0f30db1e6fc629dc52293edfb2bac4cf99ee49cc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21306
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm: Set CM bit in DataAbort

The CM bit in a DataAbort ISS indicates whether the Data Abort came from
a cache maintenance or address translation instruction.

Change-Id: I8888520446550581c8dd0507a8989935db7047be
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21305
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Mark System::getThreadContext method as const

Change-Id: Ic0ce1b098cfe0ce6ea37986a8a55002a5c18a66c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21304
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Improve fault message on SMMUv3 translation fault

Change-Id: Ib1d7ae73951b52f2378f8bd50e804d3237f74074
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21303
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Fix address used to update the SMMUv3 Walk Cache

Last level of SMMUv3 WalkCache should store the address without an offset.

Change-Id: I1046bd8210500c2c38802acd41a4403e52fd3c90
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21302
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Create helper for sending events (SEV)

Events can be generated by devices, so we need an interface devices
can use to notify events to PEs.

Change-Id: I330575e7d116388d5f9260ef4400b0feaa861f3e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21301
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU.

This was to support port proxies and getInstPort and getDataPort. With
some recent upstream changes, getInstPort and getDataPort are only used
for CPU switching which we can't support (TLM ports are bound
permanently), and with the sendFunctional delegate for port proxies,
we don't need to have a traditional gem5 port lying around.

This gets rid of the "mem" port and all its plumbing.

Change-Id: Ic68a40a26b24aa05b33da0510c9f4b7621cbf578
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21048
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

fastmodel: Implement a custom sendFunctional for CortexA76x1.

Change-Id: I28094620106a8edd90e1144b4fb87ae5729ebf32
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21047
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

x86: Switch from MessageReq and Resp to WriteReq and Resp.

Originally MessageReq was intended to mark a packet as a holding a
message destined for a particular recipient and which would not
interact with other packets.

This is similar to the way a WriteReq would behave if writing to a
device register which needs to be updated atomically. Also, while the
memory system *could* recognize a MessageReq and know that it didn't
need to interact with other packets, that was never implemented.

Change-Id: Ie54301d1d8820e206d6bae96e200ae8c71d2d784
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20823
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

fastmodel: Let the EVS set an attribute for getSendFunctional to return.

The iris CPU model doesn't necessarily know the best way to send
functional packets (what port? what type is that port?), but only has
a generic sc_module pointer to the EVS and so can't call specialized
methods on it. There also isn't any common base class for EVSes to cast
into in a generic way.

This attribute mechanism lets the EVS set up its own sendFunctional
implementation however it needs to using facilities that are built
into generic sc_objects.

Change-Id: I69bf364908c2a5360bd6ce7d3e49ce67c6f771b0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21046
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

style: normalize filename in SortedIncludes.fix()

The filename affects the sorting result. Therefore check(),
which normalizes the filename, detects an invalid sorting
of includes, but fix() fails to fix the corresponding includes.

Change-Id: I7d5a941c9ebea853004922d19e3b84f8ded2afa6
Signed-off-by: Georg Kotheimer <georg.kotheimer@mailbox.tu-dresden.de>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/10742
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

fastmodel: Add a gem5Cpu attribute to the CortexA76x1.

This attribute is to let the fast model EVS CPU find and talk to the
gem5 CPU in case it needs a pointer to one of its ThreadContexts for
instance.

Also move the code that finds the clock period attribute/event to the
constructor. gem5 guarantees that the EVS is constructed before its
pointer is passed to the iris CPU wrapper, and so the EVS will have
had a chance to install those controls if it's going to.

Change-Id: I389ef0ba0f9d528140f40444baa5091a9ec338cd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21045
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Add a utility class which makes it easier to watch signals.

These signals come from the exported virtual subsystem and could signal
interrupts, etc. The new SignalReceiver class makes it easier to watch
those signals and perform some behavior when they change without having
to bring along a lot of systemc baggage.

Change-Id: I09651de1dd0e7340a61779aaf080c695ce299fd4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21043
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

fastmodel: Pull out and simplify the interrupt mechanism in the GIC.

This change pulls out the SPI and PPI command structures and replaces
them with a custom protocol which can deliver a SPI or PPI without
having to bundle their parameters into a structure.

Change-Id: I8f15c8b3182bd6560bf5ef0345b0bc64173def85
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21042
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix invalid whenReady

When a writeback needs to be allocated the whenReady field of the
block is not set, and therefore its access latency calculation
uses the previously invalidated value (MaxTick), significantly
delaying execution.

This is fixed by assuming that the data write portion of a write
access is done regardless of previous writes, and that only the
tag latency is important for the critical path latency calculation.

Change-Id: I739132a2deab6eb4c46d084f4ee6dd65177873fd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20068
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

configs: Port PlatformConfig to the common object list

Port PlatformConfig to use the common object list.

Change-Id: If62e596bf1f28b49994da3a2800450d163383755
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20593
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

configs: Port MemConfig to the common object list

Port MemConfig to use the common object list.

Change-Id: If421c2745ac3431718a5170314045b456fc64a90
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20592
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

configs: Port HWPConfig to the common object list

Port HWPConfig to use the common object list.

Change-Id: I86db6b872808f754193dbf5814dd6c951c8f1980
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20591
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

configs: Port BPConfig to use the common object list

Port BPConfig to use the common object list.

Change-Id: I5cbd1c67cf743778bc59b5aa3c3dea5ab397b66d
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20590
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>

configs: Port CPUConfig to use the common object list

Factor out ObjectList functionality from CPUConfig.

Change-Id: I34ca55142e14559e584d38b6cca3aa5c20923521
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20589
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

configs: Create a basic ObjectList

There are multiple files that reimplement the same functionality
of listing and getting available modules for class instantiation.
Create a base class that can be derived and reduce code duplication.

Change-Id: I96bf47b1ffd10893691b0b95591969b38894dd65
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20588
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Remove is_atomic_cpu check

Commit 224f2d50a9873d054f486d7661d947db76f4cf68 removed all instances
of is_atomic_cpu.

Change-Id: I1101fbdbc16dc5d093ab87d3817308176559a548
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20659
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

mem-ruby: Remove inexistent functions from Util

Remove forward declaration of inexistent functions from RubySlicc_Util.sm.

Change-Id: I548bd75cb570371fbdaccf914c5eb9a7b92313d1
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21086
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Make bitSelect use bits<Addr>

There is no need to replicate bits<Addr>' functionality.

As a side effect, ADDRESS_WIDTH is no longer used and was removed

Change-Id: Ia5679f3976c81f779665d82cb758850092f2a293
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21085
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Fix maskLowOrderBits

The function was wrong when number = 63. Also, use the more reliable
src/base/bitfield.hh's mbits when posible.

maskLowOrderBits has only been kept because SLICC does not accept
a templated function.

Change-Id: I8dd680da02ceb9e614e2f9cbf8f1ac52cead8d45
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21084
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Remove shiftLowOrderBits

There is no need to encapsulate a shift operation.

Change-Id: Ie711d8d4975d1d9dde656cc2284a048410cfdadb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21083
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Remove maskHighOrderBits

Function was not being used. If needed, src/base/bitfield.hh's
mbits can be used instead:

maskHighOrderBits(addr, pos) == mbits<Addr>(addr, 64-pos, 0)

Change-Id: I3abd041f8d256ec157ba7502182d8588721c2a05
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21082
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Remove bitRemove

bitRemove is not being used anywhere. If needed, can be used
as src/base/bitfield.hh's bits:

bitRemove(addr, small, big) ==
    ((bits<Addr>(addr, 63, big + 1) << small) |
    bits<Addr>(addr, small, 0))

Change-Id: I45fd3bc0271ccb659d6a94e3dd00ca095dfd6aa7
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21081
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Make use of DRAMCtrl::AddrMap in the traffic generators

Use the enum defined in the memory controller rather than custom
strings and int that are later converted to the DRAMCtrl::AddrMap
enum.

Change-Id: Ie5b19f915f9990fd2b7505d4d1b17b6fc2100f9e
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21080
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added line wrapping functionality for Sim-Object desc

Descriptions were previously printed on one line, unless explicitly broken
when writing the description of the Sim-Object. In this commit, line
wrapping is enabled when printing these descriptions. Developers, when
writing the Sim-Object descriptions, may now over multiple lines with
triple double-quotes and still have the description output correctly when
viewing the Sim-Objects within the CLI.

E.g.: X86System previously had the following load_addr_mask component which
was output as:

load_addr_mask
            default: 18446744073709551615
               desc: Address to mask loading binaries with, if 0, system \
auto-calculates the mask to be the most restrictive, otherwise it obeys a \
custom mask.

This was defined by the developer via:

load_addr_mask = Param.UInt64(0xffffffffffffffff,
            "Address to mask loading binaries with, if 0, system "
            "auto-calculates the mask to be the most restrictive, "
            "otherwise it obeys a custom mask.")

This is now displayed as:

load_addr_mask
            default: 18446744073709551615
               desc: Address to mask loading binaries with, if 0,
                     system auto-calculates the mask to be the most
                     restrictive, otherwise it obeys a custom mask.

JiraID: Gem5-57
Built: Linux (GCC)
Tested: Ran quick tests for X86, ARM, and RISC-V
Change-Id: If012304e50af60f6ba10c1fa2b44da8bac1c09cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21179
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

mem: Use new-style stats in the XBar models

Migrate to new-world stats with an explicit hierarchy in all of the
XBar models.

Change-Id: I18b6746a1303ca415638e6d382fb4757607f1123
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21141
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

mem-cache: Switch to new-style stats

This change puts cache and tag stats into a Stats::Group struct. This
makes it easier to identify stat updates (they are prefixed with
stat.) and adds hierarchy information for output formats that need it.

Change-Id: I2b8e9138f1cb977abb445ec864d80a79b588481d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21140
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Convert DRAM controller to new-style stats

Note that this changes the stat format used by the DRAM
controller. Previously, it would have a structure looking a bit like
this:

  - system
    - dram: Main DRAM controller
    - dram_0: Rank 0
    - dram_1: Rank 1

This structure can't be replicated with new-world stats since stats
are confined to the SimObject name space. This means that the new
structure looks like this:

  - system
    - dram: Main DRAM controller
      - rank0: Rank 0
      - rank1: Rank 1

Change-Id: I7435cfaf137c94b0c18de619d816362dd0da8125
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21142
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Wendy Elsasser <wendy.elsasser@arm.com>