PR 78534 Change character length from int to size_t

In order to handle large character lengths on (L)LP64 targets, switch
the GFortran character length from an int to a size_t.

This is an ABI change, as procedures with character arguments take
hidden arguments with the character length.

I also changed the _size member in vtables from int to size_t, as
there were some cases where character lengths and sizes were
apparently mixed up and caused regressions otherwise. Although I
haven't tested, this might enable very large derived types as well.

Also, as there are some places in the frontend were negative character
lengths are used as special flag values, in the frontend the character
length is handled as a signed variable of the same size as a size_t,
although in the runtime library it really is size_t.

I haven't changed the character length variables for the co-array
intrinsics, as this is something that may need to be synchronized with
OpenCoarrays.

This is v5 of the patch. v4 was applied but caused breakage on big
endian targets. These have been fixed and tested, thanks to access to
the GCC compile farm.

Overview of v4 of the patch: v3 was applied but had to reverted due to
breaking bootstrap. The fix is in resolve.c:resolve_charlen, where
it's necessary to check that an expression is constant before using
mpz_sgn.

Overview of v3 of the patch: All the issues pointed out by FX's review
of v2 have been fixed. In particular, there are now new functions
gfc_mpz_get_hwi and gfc_mpz_set_hwi, similar to the GMP functions
mpz_get_si and mpz_set_si, except that they get/set a HOST_WIDE_INT
instead of a long value. Similarly, gfc_get_int_expr now takes a
HOST_WIDE_INT instead of a long, gfc_extract_long is replaced by
gfc_extract_hwi. Also, the preliminary work to handle
gfc_charlen_type_node being unsigned has been removed.

Regtested on x86_64-pc-linux-gnu, i686-pc-linux-gnu and
powerpc64-unknown-linux-gnu. Also regtested all three targets by
modifying gfortran-dg.exp to also test with "-g -flto", no new
failures observed.

frontend:

2018-01-05  Janne Blomqvist  <jb@gcc.gnu.org>

PR fortran/78534
PR fortran/66310
* array.c (got_charlen): Use gfc_charlen_int_kind.
* class.c (gfc_find_derived_vtab): Use gfc_size_kind instead of
hardcoded kind.
(find_intrinsic_vtab): Likewise.
* decl.c (match_char_length): Use gfc_charlen_int_kind.
(add_init_expr_to_sym): Use gfc_charlen_t and gfc_charlen_int_kind.
(gfc_match_implicit): Use gfc_charlen_int_kind.
* dump-parse-tree.c (show_char_const): Use gfc_charlen_t and size_t.
(show_expr): Use HOST_WIDE_INT_PRINT_DEC.
* expr.c (gfc_get_character_expr): Length parameter of type
gfc_charlen_t.
(gfc_get_int_expr): Value argument of type HOST_WIDE_INT.
(gfc_extract_hwi): New function.
(simplify_const_ref): Make string_len of type gfc_charlen_t.
(gfc_simplify_expr): Use HOST_WIDE_INT for substring refs.
* frontend-passes.c (optimize_trim): Use gfc_charlen_int_kind.
* gfortran.h (gfc_mpz_get_hwi): New prototype.
(gfc_mpz_set_hwi): Likewise.
(gfc_charlen_t): New typedef.
(gfc_expr): Use gfc_charlen_t for character lengths.
(gfc_size_kind): New extern variable.
(gfc_extract_hwi): New prototype.
(gfc_get_character_expr): Use gfc_charlen_t for character length.
(gfc_get_int_expr): Use HOST_WIDE_INT type for value argument.
* gfortran.texi: Update description of hidden string length argument.
* iresolve.c (check_charlen_present): Use gfc_charlen_int_kind.
(gfc_resolve_char_achar): Likewise.
(gfc_resolve_repeat): Pass string length directly without
temporary, use gfc_charlen_int_kind.
(gfc_resolve_transfer): Use gfc_charlen_int_kind.
* match.c (select_intrinsic_set_tmp): Use HOST_WIDE_INT for charlen.
* misc.c (gfc_mpz_get_hwi): New function.
(gfc_mpz_set_hwi): New function.
* module.c (atom_int): Change type from int to HOST_WIDE_INT.
(parse_integer): Don't complain about large integers.
(write_atom): Use HOST_WIDE_INT for integers.
(mio_integer): Handle integer type mismatch.
(mio_hwi): New function.
(mio_intrinsic_op): Use HOST_WIDE_INT.
(mio_array_ref): Likewise.
(mio_expr): Likewise.
* primary.c (match_substring): Use gfc_charlen_int_kind.
* resolve.c (resolve_substring_charlen): Use gfc_charlen_int_kind.
(resolve_character_operator): Likewise.
(resolve_assoc_var): Likewise.
(resolve_select_type): Use HOST_WIDE_INT for charlen, use snprintf.
(resolve_charlen): Use mpz_sgn to determine sign.
* simplify.c (gfc_simplify_repeat): Use HOST_WIDE_INT/gfc_charlen_t
instead of long.
* symbol.c (generate_isocbinding_symbol): Use gfc_charlen_int_kind.
* target-memory.c (size_character): Length argument of type
gfc_charlen_t.
(gfc_encode_character): Likewise.
(gfc_interpret_character): Use gfc_charlen_t.
* target-memory.h (gfc_encode_character): Modify prototype.
* trans-array.c (gfc_trans_array_ctor_element): Use existing type.
(get_array_ctor_var_strlen): Use gfc_conv_mpz_to_tree_type.
(trans_array_constructor): Use existing type.
(get_array_charlen): Likewise.
* trans-const.c (gfc_conv_mpz_to_tree_type): New function.
* trans-const.h (gfc_conv_mpz_to_tree_type): New prototype.
* trans-decl.c (gfc_trans_deferred_vars): Use existing type.
(add_argument_checking): Likewise.
* trans-expr.c (gfc_class_len_or_zero_get): Build const of type
gfc_charlen_type_node.
(gfc_conv_intrinsic_to_class): Use gfc_charlen_int_kind instead of
4, fold_convert to correct type.
(gfc_conv_class_to_class): Build const of type size_type_node for
size.
(gfc_copy_class_to_class): Likewise.
(gfc_conv_string_length): Use same type in expression.
(gfc_conv_substring): Likewise, use HOST_WIDE_INT for charlen.
(gfc_conv_string_tmp): Make sure len is of the right type.
(gfc_conv_concat_op): Use same type in expression.
(gfc_conv_procedure_call): Likewise.
(fill_with_spaces): Comment out memset() block due to spurious
-Wstringop-overflow warnings.
(gfc_trans_string_copy): Use gfc_charlen_type_node.
(alloc_scalar_allocatable_for_subcomponent_assignment):
fold_convert to right type.
(gfc_trans_subcomponent_assign): Likewise.
(trans_class_vptr_len_assignment): Build const of correct type.
(gfc_trans_pointer_assignment): Likewise.
(alloc_scalar_allocatable_for_assignment): fold_convert to right
type in expr.
(trans_class_assignment): Build const of correct type.
* trans-intrinsic.c (gfc_conv_associated): Likewise.
(gfc_conv_intrinsic_repeat): Do calculation in sizetype.
* trans-io.c (gfc_build_io_library_fndecls): Use
gfc_charlen_type_node for character lengths.
(set_string): Convert to right type in assignment.
* trans-stmt.c (gfc_trans_label_assign): Build const of
gfc_charlen_type_node.
(trans_associate_var): Likewise.
(gfc_trans_character_select): Likewise.
(gfc_trans_allocate): Likewise, don't typecast strlen result.
(gfc_trans_deallocate): Don't typecast strlen result.
* trans-types.c (gfc_size_kind): New variable.
(gfc_init_types): Determine gfc_charlen_int_kind and gfc_size_kind
from size_type_node.
* trans-types.h: Fix comment.

testsuite:

2018-01-05  Janne Blomqvist  <jb@gcc.gnu.org>

PR fortran/78534
PR fortran/66310
* gfortran.dg/char_cast_1.f90: Update scan pattern.
* gfortran.dg/dependency_49.f90: Likewise.
* gfortran.dg/repeat_4.f90: Use integers of kind C_SIZE_T.
* gfortran.dg/repeat_7.f90: New test for PR 66310.
* gfortran.dg/scan_2.f90: Handle potential cast in assignment.
* gfortran.dg/string_1.f90: Limit to ilp32 targets.
* gfortran.dg/string_1_lp64.f90: New test.
* gfortran.dg/string_3.f90: Limit to ilp32 targets.
* gfortran.dg/string_3_lp64.f90: New test.

libgfortran:

2019-01-05  Janne Blomqvist  <jb@gcc.gnu.org>

PR fortran/78534
* intrinsics/args.c (getarg_i4): Use gfc_charlen_type.
(get_command_argument_i4): Likewise.
(get_command_i4): Likewise.
* intrinsics/chmod.c (chmod_internal): Likewise.
* intrinsics/env.c (get_environment_variable_i4): Likewise.
* intrinsics/extends_type_of.c (struct vtype): Use size_t for size
member.
* intrinsics/gerror.c (gerror): Use gfc_charlen_type.
* intrinsics/getlog.c (getlog): Likewise.
* intrinsics/hostnm.c (hostnm_0): Likewise.
* intrinsics/string_intrinsics_inc.c (string_len_trim): Rework to
work if gfc_charlen_type is unsigned.
(string_scan): Likewise.
* io/transfer.c (transfer_character): Modify prototype.
(transfer_character_write): Likewise.
(transfer_character_wide): Likewise.
(transfer_character_wide_write): Likewise.
(transfer_array): Typecast to avoid signed-unsigned comparison.
* io/unit.c (is_trim_ok): Use gfc_charlen_type.
* io/write.c (namelist_write): Likewise.
* libgfortran.h (gfc_charlen_type): Change typedef to size_t.

From-SVN: r256284

PR libstdc++/83626 handle ENOENT due to filesystem race

PR libstdc++/83626
* src/filesystem/ops.cc (remove(const path&, error_code&)): Do not
report an error for ENOENT.
(remove_all(const path&)): Fix type of result variable.
(remove_all(const path&, error_code&)): Use non-throwing increment
for directory iterator. Call POSIX remove directly to avoid redundant
calls to symlink_status. Do not report errors for ENOENT.
* src/filesystem/std-ops.cc: Likewise.
* testsuite/27_io/filesystem/operations/remove_all.cc: Test throwing
overload.
* testsuite/experimental/filesystem/operations/remove_all.cc:
Likewise.

From-SVN: r256283

re PR target/83604 (ICE in copy_to_mode_reg, at explow.c:630)

PR target/83604
* config/i386/i386-builtin.def
(__builtin_ia32_vgf2p8affineinvqb_v64qi,
__builtin_ia32_vgf2p8affineqb_v64qi, __builtin_ia32_vgf2p8mulb_v64qi):
Require also OPTION_MASK_ISA_AVX512F in addition to
OPTION_MASK_ISA_GFNI.
(__builtin_ia32_vgf2p8affineinvqb_v16qi_mask,
__builtin_ia32_vgf2p8affineqb_v16qi_mask): Require
OPTION_MASK_ISA_AVX512VL instead of OPTION_MASK_ISA_SSE in addition
to OPTION_MASK_ISA_GFNI.
(__builtin_ia32_vgf2p8mulb_v32qi_mask): Require
OPTION_MASK_ISA_AVX512VL in addition to OPTION_MASK_ISA_GFNI and
OPTION_MASK_ISA_AVX512BW.
(__builtin_ia32_vgf2p8mulb_v16qi_mask): Require
OPTION_MASK_ISA_AVX512VL instead of OPTION_MASK_ISA_AVX512BW in
addition to OPTION_MASK_ISA_GFNI.
(__builtin_ia32_vgf2p8affineinvqb_v16qi,
__builtin_ia32_vgf2p8affineqb_v16qi, __builtin_ia32_vgf2p8mulb_v16qi):
Require OPTION_MASK_ISA_SSE2 instead of OPTION_MASK_ISA_SSE in addition
to OPTION_MASK_ISA_GFNI.
* config/i386/i386.c (def_builtin): Change to builtin isa/isa2 being
a requirement for all ISAs rather than any of them with a few
exceptions.
(ix86_add_new_builtins): Clear OPTION_MASK_ISA_64BIT from isa before
processing.
(ix86_expand_builtin): Require all ISAs from builtin's isa and isa2
bitmasks to be enabled with 3 exceptions, instead of requiring any
enabled ISA with lots of exceptions.
* config/i386/sse.md (vgf2p8affineinvqb_<mode><mask_name>,
vgf2p8affineqb_<mode><mask_name>, vgf2p8mulb_<mode><mask_name>):
Change avx512bw in isa attribute to avx512f.
* config/i386/sgxintrin.h: Add license boilerplate.
* config/i386/vaesintrin.h: Likewise.  Fix macro spelling __AVX512F
to __AVX512F__ and __AVX512VL to __AVX512VL__.
(_mm256_aesdec_epi128, _mm256_aesdeclast_epi128, _mm256_aesenc_epi128,
_mm256_aesenclast_epi128): Enable temporarily avx if __AVX__ is not
defined.
* config/i386/gfniintrin.h (_mm_gf2p8mul_epi8,
_mm_gf2p8affineinv_epi64_epi8, _mm_gf2p8affine_epi64_epi8): Enable
temporarily sse2 rather than sse if not enabled already.

* gcc.target/i386/sse-26.c: New test.

From-SVN: r256281

re PR target/83604 (ICE in copy_to_mode_reg, at explow.c:630)

PR target/83604
* config/i386/sse.md (VI248_VLBW): Rename to ...
(VI248_AVX512VL): ... this.  Don't guard V32HI with TARGET_AVX512BW.
(vpshrd_<mode><mask_name>, vpshld_<mode><mask_name>,
vpshrdv_<mode>, vpshrdv_<mode>_mask, vpshrdv_<mode>_maskz,
vpshrdv_<mode>_maskz_1, vpshldv_<mode>, vpshldv_<mode>_mask,
vpshldv_<mode>_maskz, vpshldv_<mode>_maskz_1): Use VI248_AVX512VL
mode iterator instead of VI248_VLBW.

* gcc.target/i386/pr83604.c: New test.

From-SVN: r256280

ipa-fnsummary.c (record_modified_bb_info): Add OP.

* ipa-fnsummary.c (record_modified_bb_info): Add OP.
(record_modified): Skip clobbers; add debug output.
(param_change_prob): Use sreal frequencies.

From-SVN: r256279

Revert DECL_USER_ALIGN part of r241959

r241959 included code to stop the vectoriser increasing the alignment of
a "user-aligned" variable.  This wasn't the main purpose of the patch,
but was done for consistency with pass_increase_alignment, and was
needed to make the testcase work.

The documentation for the aligned attribute says:

  This attribute specifies a minimum alignment for the variable or
  structure field, measured in bytes.

so I think it's reasonable for the vectoriser to increase the
alignment further, if that helps us to vectorise code.  It's also
useful if the "user" alignment actually came from an earlier pass
rather than the source code.

A possible counterexample came up when this was discussed on the lists.
Users who are trying to collate things from several translation units
into a single section can use:

  __attribute__((section ("whatever"), aligned(N)))

and would not want extra padding.  It turns out that the supported way
of doing that is to add a "used" attribute, which works even when no
"aligned" attribute is given.

2018-01-05  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* tree-vect-data-refs.c (vect_compute_data_ref_alignment): Don't
punt for user-aligned variables.

gcc/testsuite/
* gcc.dg/vect/vect-align-4.c: New test.
* gcc.dg/vect/vect-nb-iter-ub-2.c (cc): Remove alignment attribute
and redefine as a structure with an unaligned member "b".
(foo): Update accordingly.

From-SVN: r256277

Make chrec_contains_symbols true for POLY_INT_CST

2018-01-05  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* tree-chrec.c (chrec_contains_symbols): Return true for
POLY_INT_CST.

From-SVN: r256276

[PATCH PR82439][simplify-rtx] Simplify (x | y) == x -> (y & ~x) == 0

This patch add support for the missing transformation of
(x | y) == x -> (y & ~x) == 0. The transformation for (x & y) == x case
already exists in simplify-rtx.c since 2014 as of r218503 and this patch
only adds a couple of extra patterns for the IOR case. This benefits
targets that have the BICS instruction to generate better code. For
targets that do not have the BICS instructions, it still results in
no worse code generation and gives out 2 instructions.

ChangeLog Entries:

*** gcc/ChangeLog ***

2018-01-05  Sudakshina Das  <sudi.das@arm.com>

PR target/82439
* simplify-rtx.c (simplify_relational_operation_1): Add simplifications
of (x|y) == x for BICS pattern.

*** gcc/testsuite/ChangeLog ***

2018-01-05  Sudakshina Das  <sudi.das@arm.com>

PR target/82439
* gcc.target/aarch64/bics_5.c: New test.
* gcc.target/arm/bics_5.c: Likewise.

From-SVN: r256275

re PR tree-optimization/83605 (ICE: verify_gimple failed (error: dead STMT in EH table))

PR tree-optimization/83605
* gimple-ssa-strength-reduction.c: Include tree-eh.h.
(find_candidates_dom_walker::before_dom_children): Ignore stmts that
can throw.

* gcc.dg/pr83605.c: New test.

From-SVN: r256274

RTEMS/EPIPHANY: Add RTEMS support

gcc/
* config.gcc (epiphany-*-elf*): Add (epiphany-*-rtems*) configuration.
* config/epiphany/rtems.h: New file.

libgcc/
* config.host (epiphany-*-elf*): Add (epiphany-*-rtems*)
configuration.

From-SVN: r256273

Daily bump.

From-SVN: r256272

PR libstdc++/83626 Don't throw for remove("") and remove_all("")

PR libstdc++/83626
* src/filesystem/ops.cc (remove(const path&, error_code&))): Remove
redundant call to ec.clear().
(remove_all(const path&, error_code&))): Do not return an error for
non-existent paths.
* src/filesystem/std-ops.cc: Likewise.
* testsuite/27_io/filesystem/operations/remove.cc: New test.
* testsuite/27_io/filesystem/operations/remove_all.cc: Fix expected
results for non-existent paths.
* testsuite/experimental/filesystem/operations/remove.cc: New test.
* testsuite/experimental/filesystem/operations/remove_all.cc: Fix
expected results for non-existent paths.

From-SVN: r256269

re PR target/83554 (ICE: in ix86_mitigate_rop, at config/i386/i386.c:41274 with -mmitigate-rop)

PR target/83554
* config/i386/i386.md (*<rotate_insn>hi3_1 splitter): Use
QIreg_operand instead of register_operand predicate.
* config/i386/i386.c (ix86_rop_should_change_byte_p,
set_rop_modrm_reg_bits, ix86_mitigate_rop): Use -mmitigate-rop in
comments instead of -fmitigate[-_]rop.

* gcc.target/i386/pr83554.c: New test.

Co-Authored-By: Uros Bizjak <ubizjak@gmail.com>
From-SVN: r256268

Avoid Solaris/SPARC comparison failures with Solaris as (PR bootstrap/81926)

PR bootstrap/81926
* cgraphunit.c (symbol_table::compile): Switch to text_section
before calling assembly_start debug hook.
* run-rtl-passes.c (run_rtl_passes): Likewise.
Include output.h.

From-SVN: r256267

re PR other/82352 (comdat-local function called by void h::i() outside its comdat)

PR ipa/82352
* g++.dg/ipa/pr82352.C (size_t): Define to __SIZE_TYPE__ instead of
long unsigned int.

From-SVN: r256266

re PR fortran/83683 (eoshift accepts wrong-length boundary)

2018-01-04  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/83683
PR fortran/45689
* check.c (gfc_check_eoshift): Check for string length and
for conformance of boundary.
* intrinsic.c (add_functions): Add gfc_simplify_eoshift.
* intrinsic.h: Add prototype for gfc_simplify_eoshift.
* simplify.c (gfc_simplify_eoshift): New function.

2018-01-04  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/83683
PR fortran/45689
* gfortran.dg/eoshift_8.f90: New test.
* gfortran.dg/simplify_eoshift_1.f90: New test.

From-SVN: r256265

Protect second call to extract_range_from_multiplicative_op_1

Following on from:

        * tree-vrp.c (extract_range_from_multiplicative_op_1): Assert
        for VR_RANGE only; don't allow VR_ANTI_RANGE.
        (extract_range_from_binary_expr_1): Don't call
        extract_range_from_multiplicative_op_1 if !range_int_cst_p.

there was a later call to extract_range_from_multiplicative_op_1 too,
that used a negative test for a symbolic (!is_gimple_min_invariant)
range rather than a positive test for an integer range.

2017-11-04  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* tree-vrp.c (extract_range_from_binary_expr_1): Check
range_int_cst_p rather than !symbolic_range_p before calling
extract_range_from_multiplicative_op_1.

From-SVN: r256262

tree-ssa-math-opts.c (execute_cse_reciprocals_1): Remove redundant test in assertion.

* tree-ssa-math-opts.c (execute_cse_reciprocals_1): Remove
redundant test in assertion.

From-SVN: r256260

Document machine_mode wrapper classes

2018-01-04  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* doc/rtl.texi: Document machine_mode wrapper classes.

From-SVN: r256259

Add tree_fits_uhwi_p tests to BIT_FIELD_REF folder

The first BIT_FIELD_REF folding pattern assumed without checking that
operands satisfy tree_fits_uhwi_p.  The second pattern does check this:

      /* On constants we can use native encode/interpret to constant
         fold (nearly) all BIT_FIELD_REFs.  */
      if (CONSTANT_CLASS_P (arg0)
          && can_native_interpret_type_p (type)
          && BITS_PER_UNIT == 8
          && tree_fits_uhwi_p (op1)
          && tree_fits_uhwi_p (op2))

so this patch adds the checks to the first pattern too.  This is needed
for POLY_INT_CST bit positions.

2018-01-04  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* fold-const.c (fold_ternary_loc): Check tree_fits_uhwi_p before
using tree_to_uhwi.

From-SVN: r256258

Allow VEC_PERM_EXPR folding to fail

tree-ssa-forwprop.c was asserting that a VEC_PERM_EXPR fold on three
VECTOR_CSTs would always succeed, but it's possible for it to fail
with variable-length vectors.

2017-12-22  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* tree-ssa-forwprop.c (is_combined_permutation_identity): Allow
the VEC_PERM_EXPR fold to fail.

From-SVN: r256257

re PR debug/83585 (Assembler messages: Error: can't resolve `.text' {.text section} - `.LCOLDB0' {.text.unlikely section})

PR debug/83585
* bb-reorder.c (insert_section_boundary_note): Set has_bb_partition
to switched_sections.

* gcc.dg/pr83585.c: New test.

From-SVN: r256256

[PR c++/83667] Fix tree_dump ICE

https://gcc.gnu.org/ml/gcc-patches/2018-01/msg00218.html
PR c++/83667
* g++.dg/ipa/pr83667.C: Fix regex, require alias.

From-SVN: r256254

PR83680: Inverted test in arm_vectorize_vec_perm_const

2018-01-04  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
PR target/83680
* config/arm/arm.c (arm_vectorize_vec_perm_const): Fix inverted
test for d.testing.

From-SVN: r256251

re PR target/83387 (PowerPC64: Infinite loops in do_reload() with -msoft-float)

PR target/83387
* config/rs6000/rs6000.c (rs6000_discover_homogeneous_aggregate): Do not
allow arguments in FP registers if TARGET_HARD_FLOAT is false.

From-SVN: r256250

Avoid redundant calls to filesystem::status_known

* include/bits/fs_ops.h (exists(const path&, error_code&))): Only
check status_known once.
* include/experimental/bits/fs_ops.h: Likewise.

From-SVN: r256243

re PR debug/83666 (ICE: SIGFPE with -O2 -g --param=sccvn-max-scc-size=10)

PR debug/83666
* cfgexpand.c (expand_dbeug_expr) <case BIT_FIELD_REF>: Punt if mode
is BLKmode and bitpos not zero or mode change is needed.

* gcc.dg/pr83666.c: New test.

From-SVN: r256232

PR libstdc++/83607 specialize Boyer-Moore searchers for std::byte

PR libstdc++/83607
* include/std/functional (__is_byte_like): New trait.
(__is_std_equal_to): Remove.
(__boyer_moore_base_t): Use __is_byte_like instead of
__is_std_equal_to.
* include/experimental/functional (__is_std_equal_to): Remove.
(__boyer_moore_base_t): Use __is_byte_like instead of
__is_std_equal_to.
* testsuite/20_util/function_objects/83607.cc: New test.

From-SVN: r256231

Bump copyright year

From-SVN: r256230

PR83675: Restore TARGET_VIS2 check for SPARC vec_perm_const

I'd missed a TARGET_VIS2 condition when replacing vec_perm_const_optab
with TARGET_VECTORIZE_VEC_PERM_CONST in r256093.

2018-01-04  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
PR target/83675
* config/sparc/sparc.c (sparc_vectorize_vec_perm_const): Require
TARGET_VIS2.

From-SVN: r256229

re PR rtl-optimization/83628 (performance regression when accessing arrays on alpha)

PR target/83628
* config/alpha/alpha.md (*sadd<modesuffix>): Use ASHIFT
instead of MULT rtx.  Update all corresponding splitters.
(*saddl_se): Ditto.
(*ssub<modesuffix>): Ditto.
(*ssubl_se): Ditto.
(*cmp_sadd_di): Update split patterns.
(*cmp_sadd_si): Ditto.
(*cmp_sadd_sidi): Ditto.
(*cmp_ssub_di): Ditto.
(*cmp_ssub_si): Ditto.
(*cmp_ssub_sidi): Ditto.
* config/alpha/predicates.md (const23_operand): New predicate.
* config/alpha/alpha.c (alpha_rtx_costs) [PLUS, MINUS]:
Look for ASHIFT, not MULT inner operand.
(alpha_split_conditional_move): Update for *sadd<modesuffix> change.

testsuite/ChangeLog:

PR target/83628
* gcc.target/alpha/pr83628-1.c: New test.
* gcc.target/alpha/pr83628-2.c: Ditto.

From-SVN: r256228

Add version to intermediate gcov file (PR gcov-profile/83669).

2018-01-04  Martin Liska  <mliska@suse.cz>

PR gcov-profile/83669
* gcov.c (output_intermediate_file): Add version to intermediate
gcov file.
* doc/gcov.texi: Document new field 'version' in intermediate
file format. Fix location of '-k' option of gcov command.

From-SVN: r256227

Be careful about comdat boundary in ICF (PR ipa/82352).

2018-01-04  Martin Liska  <mliska@suse.cz>

PR ipa/82352
* ipa-icf.c (sem_function::merge): Do not cross comdat boundary.
2018-01-04  Martin Liska  <mliska@suse.cz>

PR ipa/82352
* g++.dg/ipa/pr82352.C: New test.

From-SVN: r256226

vect-opt-info-1.c: Moved to ...

* gcc.dg/vect-opt-info-1.c: Moved to ...
* gcc.dg/vect/nodump-vect-opt-info-1.c: ... here.  Only run on
vect_int targets, use dg-additional-options instead of dg-options and
use relative line numbers instead of absolute.

From-SVN: r256225

* gnatvsn.ads: Bump copyright year.

From-SVN: r256224

Daily bump.

From-SVN: r256222

* gimple-ssa-sprintf.c (parse_directive): Cast second dir.len to uhwi.

From-SVN: r256219

PR tree-optimization/83655 - ICE on an invalid call to memcpy declared with no prototype

gcc/testsuite/ChangeLog:

PR tree-optimization/83655
* gcc.dg/Wrestrict-5.c: New test.
* c-c++-common/builtins.c: New test.

gcc/ChangeLog:

PR tree-optimization/83655
* gimple-ssa-warn-restrict.c (wrestrict_dom_walker::check_call): Avoid
checking calls with invalid arguments.

From-SVN: r256218

PR tree-optimization/83603 - ICE in builtin_memref at gcc/gimple-ssa-warn-restrict.c:238

gcc/ChangeLog:

PR tree-optimization/83603
* calls.c (maybe_warn_nonstring_arg): Avoid accessing function
arguments past the endof the argument list in functions declared
without a prototype.
* gimple-ssa-warn-restrict.c (wrestrict_dom_walker::check_call):
Avoid checking when arguments are null.

gcc/testsuite/ChangeLog:

PR tree-optimization/83603
* gcc.dg/Wrestrict-4.c: New test.

From-SVN: r256217

Make vectorizable_load/store handle IFN_MASK_LOAD/STORE

After the previous patches, it's easier to see that the remaining
inlined transform code in vectorizable_mask_load_store is just a
cut-down version of the VMAT_CONTIGUOUS handling in vectorizable_load
and vectorizable_store.  This patch therefore makes those functions
handle masked loads and stores instead.

This makes it easier to handle more forms of masked load and store
without duplicating logic from the unmasked forms.  It also helps with
support for fully-masked loops.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* tree-vect-stmts.c (vect_get_store_rhs): New function.
(vectorizable_mask_load_store): Delete.
(vectorizable_call): Return false for masked loads and stores.
(vectorizable_store): Handle IFN_MASK_STORE.  Use vect_get_store_rhs
instead of gimple_assign_rhs1.
(vectorizable_load): Handle IFN_MASK_LOAD.
(vect_transform_stmt): Don't set is_store for call_vec_info_type.

From-SVN: r256216

Split gather load handling out of vectorizable_{mask_load_store,load}

vectorizable_mask_load_store and vectorizable_load used the same
code to build a gather load call, except that the former also
vectorised a mask argument and used it for both the merge and mask
inputs.  The latter instead used a merge input of zero and a mask
input of all-ones.  This patch splits it out into a subroutine.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* tree-vect-stmts.c (vect_build_gather_load_calls): New function,
split out from..,
(vectorizable_mask_load_store): ...here.
(vectorizable_load): ...and here.

From-SVN: r256215

Split out gather load mask building

This patch splits out the code to build an all-bits-one or all-bits-zero
input to a gather load.  The catch is that both masks can have
floating-point type, in which case they are implicitly treated in
the same way as an integer bitmask.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* tree-vect-stmts.c (vect_build_all_ones_mask)
(vect_build_zero_merge_argument): New functions, split out from...
(vectorizable_load): ...here.

From-SVN: r256214

Split rhs checking out of vectorizable_{,mask_load_}store

This patch splits out the rhs checking code that's common to both
vectorizable_mask_load_store and vectorizable_store.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* tree-vect-stmts.c (vect_check_store_rhs): New function,
split out from...
(vectorizable_mask_load_store): ...here.
(vectorizable_store): ...and here.

From-SVN: r256213

Split mask checking out of vectorizable_mask_load_store

This patch splits the mask argument checking out of
vectorizable_mask_load_store, so that a later patch can use it in both
vectorizable_load and vectorizable_store.  It also adds dump messages
for false returns.  This is mostly useful for the TYPE_VECTOR_SUBPARTS
check, which can fail if pattern recognition didn't convert the mask
properly.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* tree-vect-stmts.c (vect_check_load_store_mask): New function,
split out from...
(vectorizable_mask_load_store): ...here.

From-SVN: r256212

Make vect_model_store_cost take a vec_load_store_type

This patch makes vect_model_store_cost take a vec_load_store_type
instead of a vect_def_type.  It's a wash on its own, but it helps
with later patches.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* tree-vectorizer.h (vec_load_store_type): Moved from tree-vec-stmts.c
(vect_model_store_cost): Take a vec_load_store_type instead of a
vect_def_type.
* tree-vect-stmts.c (vec_load_store_type): Move to tree-vectorizer.h.
(vect_model_store_cost): Take a vec_load_store_type instead of a
vect_def_type.
(vectorizable_mask_load_store): Update accordingly.
(vectorizable_store): Likewise.
* tree-vect-slp.c (vect_analyze_slp_cost_1): Update accordingly.

From-SVN: r256211

Move code that stubs out IFN_MASK_LOADs

vectorizable_mask_load_store replaces scalar IFN_MASK_LOAD calls with
dummy assignments, so that they never survive vectorisation.  This patch
moves the code to vect_transform_loop instead, so that we only change
the scalar statements once all of them have been vectorised.

This makes it easier to handle other types of functions that need
stubbing out, and also makes it easier to handle groups and patterns.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* tree-vect-loop.c (vect_transform_loop): Stub out scalar
IFN_MASK_LOAD calls here rather than...
* tree-vect-stmts.c (vectorizable_mask_load_store): ...here.

From-SVN: r256210

Use extract_bit_field_as_subreg for vectors

extract_bit_field_1 tries to use vec_extract to extract part of a
vector.  However, if that pattern isn't defined or if the operands
aren't suitable, another good approach is to try a direct subreg
reference.  This is particularly useful for multi-vector modes on
SVE (e.g. when extracting one vector from an LD2 result).

The function would go on to try the same thing anyway, but only
if there is an integer mode with the same size as the vector mode,
which isn't true for SVE modes (and doesn't seem a good thing to
require in general).  Even when there is an integer mode, doing the
operation on the original modes avoids some unnecessary bitcasting.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* expmed.c (extract_bit_field_1): For vector extracts,
fall back to extract_bit_field_as_subreg if vec_extract
isn't available.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256209

Improve spilling for variable-width slots

Once SVE is enabled, a general AArch64 spill slot offset will be

  A + B * VL

where A is a constant and B is a multiple of the SVE vector length.
The offsets in SVE load and store instructions are a multiple of VL
(and so can encode some values of B), while offsets for standard AArch64
load and store instructions aren't (and encode some values of A).

We therefore get better spill code if variable-sized slots are grouped
together separately from constant-sized slots, and if variable-sized
slots are not reused for constant-sized data.  Then, spills to the
constant-sized slots can add B * VL to the offset first, creating a
common anchor point for spills with the same B component but different
A components.  Similarly, spills to variable-sized slots can add A to
the offset first, creating a common anchor point for spills with the same
A component but different B components.

This patch implements the sorting and grouping side of the optimisation.
A later patch creates the anchor points.

The patch is a no-op on other targets.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* lra-spills.c (pseudo_reg_slot_compare): Sort slots by whether
they are variable or constant sized.
(assign_stack_slot_num_and_sort_pseudos): Don't reuse variable-sized
slots for constant-sized data.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256208

Improve vectorization COND_EXPR <bool op bool, ...>

This patch allows us to recognise:

    ... = bool1 != bool2 ? x : y

as equivalent to:

    bool tmp = bool1 ^ bool2;
    ... = tmp ? x : y

For the latter we were already able to find the natural number
of vector units for tmp based on the types that feed bool1 and
bool2, whereas with the former we would simply treat bool1 and
bool2 as vectorised 8-bit values, possibly requiring them to
be packed and unpacked from their natural width.

This is used by a later SVE patch.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* tree-vect-patterns.c (vect_recog_mask_conversion_pattern): When
handling COND_EXPRs with boolean comparisons, try to find a better
basis for the mask type than the boolean itself.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256207

Allow the target to set MAX_BITSIZE_MODE_ANY_MODE

The default value of MAX_BITSIZE_MODE_ANY_MODE is calculated
from the initial mode sizes specified in the modes.def file.
The target needs to be able to override it if ADJUST_BYTESIZE
& co. can choose a bigger size.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* doc/rtl.texi (MAX_BITSIZE_MODE_ANY_MODE): Describe how the default
is calculated and how it can be overridden.
* genmodes.c (max_bitsize_mode_any_mode): New variable.
(create_modes): Initialize it from MAX_BITSIZE_MODE_ANY_MODE,
if defined.
(emit_max_int): Use it to set the output MAX_BITSIZE_MODE_ANY_MODE,
if nonzero.

From-SVN: r256206

[AArch64] Rewrite aarch64_simd_valid_immediate

This patch reworks aarch64_simd_valid_immediate so that
it's easier to add SVE support.  The main changes are:

- make simd_immediate_info easier to construct
- replace the while (1) { ... break; } blocks with checks that use
  the full 64-bit value of the constant
- treat floating-point modes as integers if they aren't valid
  as floating-point values

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* config/aarch64/aarch64-protos.h (aarch64_output_simd_mov_immediate):
Remove the mode argument.
(aarch64_simd_valid_immediate): Remove the mode and inverse
arguments.
* config/aarch64/iterators.md (bitsize): New iterator.
* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<mode>, and<mode>3)
(ior<mode>3): Update calls to aarch64_output_simd_mov_immediate.
* config/aarch64/constraints.md (Do, Db, Dn): Update calls to
aarch64_simd_valid_immediate.
* config/aarch64/predicates.md (aarch64_reg_or_orr_imm): Likewise.
(aarch64_reg_or_bic_imm): Likewise.
* config/aarch64/aarch64.c (simd_immediate_info): Replace mvn
with an insn_type enum and msl with a modifier_type enum.
Replace element_width with a scalar_mode.  Change the shift
to unsigned int.  Add constructors for scalar_float_mode and
scalar_int_mode elements.
(aarch64_vect_float_const_representable_p): Delete.
(aarch64_can_const_movi_rtx_p)
(aarch64_simd_scalar_immediate_valid_for_move)
(aarch64_simd_make_constant): Update call to
aarch64_simd_valid_immediate.
(aarch64_advsimd_valid_immediate_hs): New function.
(aarch64_advsimd_valid_immediate): Likewise.
(aarch64_simd_valid_immediate): Remove mode and inverse
arguments.  Rewrite to use the above.  Use const_vec_duplicate_p
to detect duplicated constants and use aarch64_float_const_zero_rtx_p
and aarch64_float_const_representable_p on the result.
(aarch64_output_simd_mov_immediate): Remove mode argument.
Update call to aarch64_simd_valid_immediate and use of
simd_immediate_info.
(aarch64_output_scalar_simd_mov_immediate): Update call
accordingly.

gcc/testsuite/
* gcc.target/aarch64/vect-movi.c (movi_float_lsl24): New function.
(main): Call it.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256205

Add support for adjusting the number of units in a mode

We already allow the target to change the size and alignment of a mode.
This patch does the same thing for the number of units, which is needed
to give command-line control of the SVE vector length.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* machmode.h (mode_precision): Prefix with CONST_MODE_PRECISION.
(mode_nunits): Likewise CONST_MODE_NUNITS.
* machmode.def (ADJUST_NUNITS): Document.
* genmodes.c (mode_data::need_nunits_adj): New field.
(blank_mode): Update accordingly.
(adj_nunits): New variable.
(print_maybe_const_decl): Replace CATEGORY with a NEEDS_ADJ
parameter.
(emit_mode_size_inline): Set need_bytesize_adj for all modes
listed in adj_nunits.
(emit_mode_nunits_inline): Set need_nunits_adj for all modes
listed in adj_nunits.  Don't emit case statements for such modes.
(emit_insn_modes_h): Emit definitions of CONST_MODE_NUNITS
and CONST_MODE_PRECISION.  Make CONST_MODE_SIZE expand to
nothing if adj_nunits is nonnull.
(emit_mode_precision, emit_mode_nunits): Use print_maybe_const_decl.
(emit_mode_unit_size, emit_mode_base_align, emit_mode_ibit)
(emit_mode_fbit): Update use of print_maybe_const_decl.
(emit_move_size): Likewise.  Treat the array as non-const
if adj_nunits.
(emit_mode_adjustments): Handle adj_nunits.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256204

Allow targets to pick a vector prefix other than "V"

Originally the SVE port used the names for 256-bit vectors, as the
next available increment after Advanced SIMD.  However, that was
always a bit of a hack and is bound to confuse people new to the code.

Nothing actually requires vector modes to have names of the form
V<nunits><mode>, and after talking it over with the AArch64 maintainers,
we agreed to switch to things like:

    VNx16QI

instead.  This patch lets targets pick this kind of prefix.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* machmode.def (VECTOR_MODES_WITH_PREFIX): Document.
* genmodes.c (VECTOR_MODES_WITH_PREFIX): New macro.
(VECTOR_MODES): Use it.
(make_vector_modes): Take the prefix as an argument.

From-SVN: r256203

Add support for MODE_VECTOR_BOOL

This patch adds a new mode class to represent vectors of booleans.
GET_MODE_BITSIZE (m) / GET_MODE_NUNITS (m) determines the number
of bits that are used to represent each boolean; this can be 1
for a fully-packed representation or greater than 1 for an unpacked
representation.  In the latter case, the value of bits other than
the lowest is not significant.

These are used by the SVE port to represent predicates.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* mode-classes.def (MODE_VECTOR_BOOL): New mode class.
* machmode.h (INTEGRAL_MODE_P, VECTOR_MODE_P): Return true
for MODE_VECTOR_BOOL.
* machmode.def (VECTOR_BOOL_MODE): Document.
* genmodes.c (VECTOR_BOOL_MODE): New macro.
(make_vector_bool_mode): New function.
(complete_mode, emit_mode_wider, emit_mode_adjustments): Handle
MODE_VECTOR_BOOL.
* lto-streamer-in.c (lto_input_mode_table): Likewise.
* rtx-vector-builder.c (rtx_vector_builder::find_cached_value):
Likewise.
* stor-layout.c (int_mode_for_mode): Likewise.
* tree.c (build_vector_type_for_mode): Likewise.
* varasm.c (output_constant_pool_2): Likewise.
* emit-rtl.c (init_emit_once): Make sure that CONST1_RTX (BImode) and
CONSTM1_RTX (BImode) are the same thing.  Initialize const_tiny_rtx
for MODE_VECTOR_BOOL.
* expr.c (expand_expr_real_1): Use VECTOR_MODE_P instead of a list
of mode class checks.
* tree-vect-generic.c (expand_vector_operation): Use VECTOR_MODE_P
instead of a list of mode class checks.
(expand_vector_scalar_condition): Likewise.
(type_for_widest_vector_mode): Handle BImode as an inner mode.

gcc/c-family/
* c-common.c (c_common_type_for_mode): Handle MODE_VECTOR_BOOL.

gcc/fortran/
* trans-types.c (gfc_type_for_mode): Handle MODE_VECTOR_BOOL.

gcc/go/
* go-lang.c (go_langhook_type_for_mode): Handle MODE_VECTOR_BOOL.

gcc/lto/
* lto-lang.c (lto_type_for_mode): Handle MODE_VECTOR_BOOL.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256202

poly_int: GET_MODE_SIZE

This patch changes GET_MODE_SIZE from unsigned short to poly_uint16.
The non-mechanical parts were handled by previous patches.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* machmode.h (mode_size): Change from unsigned short to
poly_uint16_pod.
(mode_to_bytes): Return a poly_uint16 rather than an unsigned short.
(GET_MODE_SIZE): Return a constant if ONLY_FIXED_SIZE_MODES,
or if measurement_type is not polynomial.
(fixed_size_mode::includes_p): Check for constant-sized modes.
* genmodes.c (emit_mode_size_inline): Make mode_size_inline
return a poly_uint16 rather than an unsigned short.
(emit_mode_size): Change the type of mode_size from unsigned short
to poly_uint16_pod.  Use ZERO_COEFFS for the initializer.
(emit_mode_adjustments): Cope with polynomial vector sizes.
* lto-streamer-in.c (lto_input_mode_table): Use bp_unpack_poly_value
for GET_MODE_SIZE.
* lto-streamer-out.c (lto_write_mode_table): Use bp_pack_poly_value
for GET_MODE_SIZE.
* auto-inc-dec.c (try_merge): Treat GET_MODE_SIZE as polynomial.
* builtins.c (expand_ifn_atomic_compare_exchange_into_call): Likewise.
* caller-save.c (setup_save_areas): Likewise.
(replace_reg_with_saved_mem): Likewise.
* calls.c (emit_library_call_value_1): Likewise.
* combine-stack-adj.c (combine_stack_adjustments_for_block): Likewise.
* combine.c (simplify_set, make_extraction, simplify_shift_const_1)
(gen_lowpart_for_combine): Likewise.
* convert.c (convert_to_integer_1): Likewise.
* cse.c (equiv_constant, cse_insn): Likewise.
* cselib.c (autoinc_split, cselib_hash_rtx): Likewise.
(cselib_subst_to_values): Likewise.
* dce.c (word_dce_process_block): Likewise.
* df-problems.c (df_word_lr_mark_ref): Likewise.
* dwarf2cfi.c (init_one_dwarf_reg_size): Likewise.
* dwarf2out.c (multiple_reg_loc_descriptor, mem_loc_descriptor)
(concat_loc_descriptor, concatn_loc_descriptor, loc_descriptor)
(rtl_for_decl_location): Likewise.
* emit-rtl.c (gen_highpart, widen_memory_access): Likewise.
* expmed.c (extract_bit_field_1, extract_integral_bit_field): Likewise.
* expr.c (emit_group_load_1, clear_storage_hints): Likewise.
(emit_move_complex, emit_move_multi_word, emit_push_insn): Likewise.
(expand_expr_real_1): Likewise.
* function.c (assign_parm_setup_block_p, assign_parm_setup_block)
(pad_below): Likewise.
* gimple-fold.c (optimize_atomic_compare_exchange_p): Likewise.
* gimple-ssa-store-merging.c (rhs_valid_for_store_merging_p): Likewise.
* ira.c (get_subreg_tracking_sizes): Likewise.
* ira-build.c (ira_create_allocno_objects): Likewise.
* ira-color.c (coalesced_pseudo_reg_slot_compare): Likewise.
(ira_sort_regnos_for_alter_reg): Likewise.
* ira-costs.c (record_operand_costs): Likewise.
* lower-subreg.c (interesting_mode_p, simplify_gen_subreg_concatn)
(resolve_simple_move): Likewise.
* lra-constraints.c (get_reload_reg, operands_match_p): Likewise.
(process_addr_reg, simplify_operand_subreg, curr_insn_transform)
(lra_constraints): Likewise.
(CONST_POOL_OK_P): Reject variable-sized modes.
* lra-spills.c (slot, assign_mem_slot, pseudo_reg_slot_compare)
(add_pseudo_to_slot, lra_spill): Likewise.
* omp-low.c (omp_clause_aligned_alignment): Likewise.
* optabs-query.c (get_best_extraction_insn): Likewise.
* optabs-tree.c (expand_vec_cond_expr_p): Likewise.
* optabs.c (expand_vec_perm_var, expand_vec_cond_expr): Likewise.
(expand_mult_highpart, valid_multiword_target_p): Likewise.
* recog.c (offsettable_address_addr_space_p): Likewise.
* regcprop.c (maybe_mode_change): Likewise.
* reginfo.c (choose_hard_reg_mode, record_subregs_of_mode): Likewise.
* regrename.c (build_def_use): Likewise.
* regstat.c (dump_reg_info): Likewise.
* reload.c (complex_word_subreg_p, push_reload, find_dummy_reload)
(find_reloads, find_reloads_subreg_address): Likewise.
* reload1.c (eliminate_regs_1): Likewise.
* rtlanal.c (for_each_inc_dec_find_inc_dec, rtx_cost): Likewise.
* simplify-rtx.c (avoid_constant_pool_reference): Likewise.
(simplify_binary_operation_1, simplify_subreg): Likewise.
* targhooks.c (default_function_arg_padding): Likewise.
(default_hard_regno_nregs, default_class_max_nregs): Likewise.
* tree-cfg.c (verify_gimple_assign_binary): Likewise.
(verify_gimple_assign_ternary): Likewise.
* tree-inline.c (estimate_move_cost): Likewise.
* tree-ssa-forwprop.c (simplify_vector_constructor): Likewise.
* tree-ssa-loop-ivopts.c (add_autoinc_candidates): Likewise.
(get_address_cost_ainc): Likewise.
* tree-vect-data-refs.c (vect_enhance_data_refs_alignment): Likewise.
(vect_supportable_dr_alignment): Likewise.
* tree-vect-loop.c (vect_determine_vectorization_factor): Likewise.
(vectorizable_reduction): Likewise.
* tree-vect-stmts.c (vectorizable_assignment, vectorizable_shift)
(vectorizable_operation, vectorizable_load): Likewise.
* tree.c (build_same_sized_truth_vector_type): Likewise.
* valtrack.c (cleanup_auto_inc_dec): Likewise.
* var-tracking.c (emit_note_insn_var_location): Likewise.
* config/arc/arc.h (ASM_OUTPUT_CASE_END): Use as_a <scalar_int_mode>.
(ADDR_VEC_ALIGN): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256201

poly_int: GET_MODE_BITSIZE

This patch changes GET_MODE_BITSIZE from an unsigned short
to a poly_uint16.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* machmode.h (mode_to_bits): Return a poly_uint16 rather than an
unsigned short.
(GET_MODE_BITSIZE): Return a constant if ONLY_FIXED_SIZE_MODES,
or if measurement_type is polynomial.
* calls.c (shift_return_value): Treat GET_MODE_BITSIZE as polynomial.
* combine.c (make_extraction): Likewise.
* dse.c (find_shift_sequence): Likewise.
* dwarf2out.c (mem_loc_descriptor): Likewise.
* expmed.c (store_integral_bit_field, extract_bit_field_1): Likewise.
(extract_bit_field, extract_low_bits): Likewise.
* expr.c (convert_move, convert_modes, emit_move_insn_1): Likewise.
(optimize_bitfield_assignment_op, expand_assignment): Likewise.
(store_expr_with_bounds, store_field, expand_expr_real_1): Likewise.
* fold-const.c (optimize_bit_field_compare, merge_ranges): Likewise.
* gimple-fold.c (optimize_atomic_compare_exchange_p): Likewise.
* reload.c (find_reloads): Likewise.
* reload1.c (alter_reg): Likewise.
* stor-layout.c (bitwise_mode_for_mode, compute_record_mode): Likewise.
* targhooks.c (default_secondary_memory_needed_mode): Likewise.
* tree-if-conv.c (predicate_mem_writes): Likewise.
* tree-ssa-strlen.c (handle_builtin_memcmp): Likewise.
* tree-vect-patterns.c (adjust_bool_pattern): Likewise.
* tree-vect-stmts.c (vectorizable_simd_clone_call): Likewise.
* valtrack.c (dead_debug_insert_temp): Likewise.
* varasm.c (mergeable_constant_section): Likewise.
* config/sh/sh.h (LOCAL_ALIGNMENT): Use as_a <fixed_size_mode>.

gcc/ada/
* gcc-interface/misc.c (enumerate_modes): Treat GET_MODE_BITSIZE
as polynomial.

gcc/c-family/
* c-ubsan.c (ubsan_instrument_shift): Treat GET_MODE_BITSIZE
as polynomial.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256200

poly_int: expand_assignment

This patch makes the CONCAT handing in expand_assignment cope with
polynomial mode sizes.  The mode of the CONCAT must be complex,
so we can base the tests on the sizes of the real and imaginary
components.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* expr.c (expand_assignment): Cope with polynomial mode sizes
when assigning to a CONCAT.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256199

poly_int: GET_MODE_PRECISION

This patch changes GET_MODE_PRECISION from an unsigned short
to a poly_uint16.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* machmode.h (mode_precision): Change from unsigned short to
poly_uint16_pod.
(mode_to_precision): Return a poly_uint16 rather than an unsigned
short.
(GET_MODE_PRECISION): Return a constant if ONLY_FIXED_SIZE_MODES,
or if measurement_type is not polynomial.
(HWI_COMPUTABLE_MODE_P): Turn into a function.  Optimize the case
in which the mode is already known to be a scalar_int_mode.
* genmodes.c (emit_mode_precision): Change the type of mode_precision
from unsigned short to poly_uint16_pod.  Use ZERO_COEFFS for the
initializer.
* lto-streamer-in.c (lto_input_mode_table): Use bp_unpack_poly_value
for GET_MODE_PRECISION.
* lto-streamer-out.c (lto_write_mode_table): Use bp_pack_poly_value
for GET_MODE_PRECISION.
* combine.c (update_rsp_from_reg_equal): Treat GET_MODE_PRECISION
as polynomial.
(try_combine, find_split_point, combine_simplify_rtx): Likewise.
(expand_field_assignment, make_extraction): Likewise.
(make_compound_operation_int, record_dead_and_set_regs_1): Likewise.
(get_last_value): Likewise.
* convert.c (convert_to_integer_1): Likewise.
* cse.c (cse_insn): Likewise.
* expr.c (expand_expr_real_1): Likewise.
* lra-constraints.c (simplify_operand_subreg): Likewise.
* optabs-query.c (can_atomic_load_p): Likewise.
* optabs.c (expand_atomic_load): Likewise.
(expand_atomic_store): Likewise.
* ree.c (combine_reaching_defs): Likewise.
* rtl.h (partial_subreg_p, paradoxical_subreg_p): Likewise.
* rtlanal.c (nonzero_bits1, lsb_bitfield_op_p): Likewise.
* tree.h (type_has_mode_precision_p): Likewise.
* ubsan.c (instrument_si_overflow): Likewise.

gcc/ada/
* gcc-interface/misc.c (enumerate_modes): Treat GET_MODE_PRECISION
as polynomial.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256198

poly_int: TYPE_VECTOR_SUBPARTS

This patch changes TYPE_VECTOR_SUBPARTS to a poly_uint64.  The value is
encoded in the 10-bit precision field and was previously always stored
as a simple log2 value.  The challenge was to use this 10 bits to
encode the number of elements in variable-length vectors, so that
we didn't need to increase the size of the tree.

In practice the number of vector elements should always have the form
N + N * X (where X is the runtime value), and as for constant-length
vectors, N must be a power of 2 (even though X itself might not be).
The patch therefore uses the low 8 bits to encode log2(N) and bit
8 to select between constant-length and variable-length vectors.
Targets without variable-length vectors continue to use the old scheme.

A new valid_vector_subparts_p function tests whether a given number
of elements can be encoded.  This is false for the vector modes that
represent an LD3 or ST3 vector triple (which we want to treat as arrays
of vectors rather than single vectors).

Most of the patch is mechanical; previous patches handled the changes
that weren't entirely straightforward.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* tree.h (TYPE_VECTOR_SUBPARTS): Turn into a function and handle
polynomial numbers of units.
(SET_TYPE_VECTOR_SUBPARTS): Likewise.
(valid_vector_subparts_p): New function.
(build_vector_type): Remove temporary shim and take the number
of units as a poly_uint64 rather than an int.
(build_opaque_vector_type): Take the number of units as a
poly_uint64 rather than an int.
* tree.c (build_vector_from_ctor): Handle polynomial
TYPE_VECTOR_SUBPARTS.
(type_hash_canon_hash, type_cache_hasher::equal): Likewise.
(uniform_vector_p, vector_type_mode, build_vector): Likewise.
(build_vector_from_val): If the number of units is variable,
use build_vec_duplicate_cst for constant operands and
VEC_DUPLICATE_EXPR otherwise.
(make_vector_type): Remove temporary is_constant ().
(build_vector_type, build_opaque_vector_type): Take the number of
units as a poly_uint64 rather than an int.
(check_vector_cst): Handle polynomial TYPE_VECTOR_SUBPARTS and
VECTOR_CST_NELTS.
* cfgexpand.c (expand_debug_expr): Likewise.
* expr.c (count_type_elements, categorize_ctor_elements_1): Likewise.
(store_constructor, expand_expr_real_1): Likewise.
(const_scalar_mask_from_tree): Likewise.
* fold-const-call.c (fold_const_reduction): Likewise.
* fold-const.c (const_binop, const_unop, fold_convert_const): Likewise.
(operand_equal_p, fold_vec_perm, fold_ternary_loc): Likewise.
(native_encode_vector, vec_cst_ctor_to_array): Likewise.
(fold_relational_const): Likewise.
(native_interpret_vector): Likewise.  Change the size from an
int to an unsigned int.
* gimple-fold.c (gimple_fold_stmt_to_constant_1): Handle polynomial
TYPE_VECTOR_SUBPARTS.
(gimple_fold_indirect_ref, gimple_build_vector): Likewise.
(gimple_build_vector_from_val): Use VEC_DUPLICATE_EXPR when
duplicating a non-constant operand into a variable-length vector.
* hsa-brig.c (hsa_op_immed::emit_to_buffer): Handle polynomial
TYPE_VECTOR_SUBPARTS and VECTOR_CST_NELTS.
* ipa-icf.c (sem_variable::equals): Likewise.
* match.pd: Likewise.
* omp-simd-clone.c (simd_clone_subparts): Likewise.
* print-tree.c (print_node): Likewise.
* stor-layout.c (layout_type): Likewise.
* targhooks.c (default_builtin_vectorization_cost): Likewise.
* tree-cfg.c (verify_gimple_comparison): Likewise.
(verify_gimple_assign_binary): Likewise.
(verify_gimple_assign_ternary): Likewise.
(verify_gimple_assign_single): Likewise.
* tree-pretty-print.c (dump_generic_node): Likewise.
* tree-ssa-forwprop.c (simplify_vector_constructor): Likewise.
(simplify_bitfield_ref, is_combined_permutation_identity): Likewise.
* tree-vect-data-refs.c (vect_permute_store_chain): Likewise.
(vect_grouped_load_supported, vect_permute_load_chain): Likewise.
(vect_shift_permute_load_chain): Likewise.
* tree-vect-generic.c (nunits_for_known_piecewise_op): Likewise.
(expand_vector_condition, optimize_vector_constructor): Likewise.
(lower_vec_perm, get_compute_type): Likewise.
* tree-vect-loop.c (vect_determine_vectorization_factor): Likewise.
(get_initial_defs_for_reduction, vect_transform_loop): Likewise.
* tree-vect-patterns.c (vect_recog_bool_pattern): Likewise.
(vect_recog_mask_conversion_pattern): Likewise.
* tree-vect-slp.c (vect_supported_load_permutation_p): Likewise.
(vect_get_constant_vectors, vect_transform_slp_perm_load): Likewise.
* tree-vect-stmts.c (perm_mask_for_reverse): Likewise.
(get_group_load_store_type, vectorizable_mask_load_store): Likewise.
(vectorizable_bswap, simd_clone_subparts, vectorizable_assignment)
(vectorizable_shift, vectorizable_operation, vectorizable_store)
(vectorizable_load, vect_is_simple_cond, vectorizable_comparison)
(supportable_widening_operation): Likewise.
(supportable_narrowing_operation): Likewise.
* tree-vector-builder.c (tree_vector_builder::binary_encoded_nelts):
Likewise.
* varasm.c (output_constant): Likewise.

gcc/ada/
* gcc-interface/utils.c (gnat_types_compatible_p): Handle
polynomial TYPE_VECTOR_SUBPARTS.

gcc/brig/
* brigfrontend/brig-to-generic.cc (get_unsigned_int_type): Handle
polynomial TYPE_VECTOR_SUBPARTS.
* brigfrontend/brig-util.h (gccbrig_type_vector_subparts): Likewise.

gcc/c-family/
* c-common.c (vector_types_convertible_p, c_build_vec_perm_expr)
(convert_vector_to_array_for_subscript): Handle polynomial
TYPE_VECTOR_SUBPARTS.
(c_common_type_for_mode): Check valid_vector_subparts_p.
* c-pretty-print.c (pp_c_initializer_list): Handle polynomial
VECTOR_CST_NELTS.

gcc/c/
* c-typeck.c (comptypes_internal, build_binary_op): Handle polynomial
TYPE_VECTOR_SUBPARTS.

gcc/cp/
* constexpr.c (cxx_eval_array_reference): Handle polynomial
VECTOR_CST_NELTS.
(cxx_fold_indirect_ref): Handle polynomial TYPE_VECTOR_SUBPARTS.
* call.c (build_conditional_expr_1): Likewise.
* decl.c (cp_finish_decomp): Likewise.
* mangle.c (write_type): Likewise.
* typeck.c (structural_comptypes): Likewise.
(cp_build_binary_op): Likewise.
* typeck2.c (process_init_constructor_array): Likewise.

gcc/fortran/
* trans-types.c (gfc_type_for_mode): Check valid_vector_subparts_p.

gcc/lto/
* lto-lang.c (lto_type_for_mode): Check valid_vector_subparts_p.
* lto.c (hash_canonical_type): Handle polynomial TYPE_VECTOR_SUBPARTS.

gcc/go/
* go-lang.c (go_langhook_type_for_mode): Check valid_vector_subparts_p.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256197

poly_int: vect_permute_load/store_chain

The GET_MODE_NUNITS patch made vect_grouped_store_supported and
vect_grouped_load_supported check for a constant number of elements,
so vect_permute_store_chain and vect_permute_load_chain can assert
for that.  This patch adds commentary to that effect; the actual
asserts will be added by a later, more mechanical, patch.

The patch also reorganises the function so that the asserts
are linked specifically to code that builds permute vectors
element-by-element.  This allows a later patch to add support
for some variable-length permutes.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* tree-vect-data-refs.c (vect_permute_store_chain): Reorganize
so that both the length == 3 and length != 3 cases set up their
own permute vectors.  Add comments explaining why we know the
number of elements is constant.
(vect_permute_load_chain): Likewise.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256196

poly_int: GET_MODE_NUNITS

This patch changes GET_MODE_NUNITS from unsigned char
to poly_uint16, although it remains a macro when compiling
target code with NUM_POLY_INT_COEFFS == 1.

We can handle permuted loads and stores for variable nunits if
the number of statements is a power of 2, but not otherwise.

The to_constant call in make_vector_type goes away in a later patch.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* machmode.h (mode_nunits): Change from unsigned char to
poly_uint16_pod.
(ONLY_FIXED_SIZE_MODES): New macro.
(pod_mode::measurement_type, scalar_int_mode::measurement_type)
(scalar_float_mode::measurement_type, scalar_mode::measurement_type)
(complex_mode::measurement_type, fixed_size_mode::measurement_type):
New typedefs.
(mode_to_nunits): Return a poly_uint16 rather than an unsigned short.
(GET_MODE_NUNITS): Return a constant if ONLY_FIXED_SIZE_MODES,
or if measurement_type is not polynomial.
* genmodes.c (ZERO_COEFFS): New macro.
(emit_mode_nunits_inline): Make mode_nunits_inline return a
poly_uint16.
(emit_mode_nunits): Change the type of mode_nunits to poly_uint16_pod.
Use ZERO_COEFFS when emitting initializers.
* data-streamer.h (bp_pack_poly_value): New function.
(bp_unpack_poly_value): Likewise.
* lto-streamer-in.c (lto_input_mode_table): Use bp_unpack_poly_value
for GET_MODE_NUNITS.
* lto-streamer-out.c (lto_write_mode_table): Use bp_pack_poly_value
for GET_MODE_NUNITS.
* tree.c (make_vector_type): Remove temporary shim and make
the real function take the number of units as a poly_uint64
rather than an int.
(build_vector_type_for_mode): Handle polynomial nunits.
* dwarf2out.c (loc_descriptor, add_const_value_attribute): Likewise.
* emit-rtl.c (const_vec_series_p_1): Likewise.
(gen_rtx_CONST_VECTOR): Likewise.
* fold-const.c (test_vec_duplicate_folding): Likewise.
* genrecog.c (validate_pattern): Likewise.
* optabs-query.c (can_vec_perm_var_p, can_mult_highpart_p): Likewise.
* optabs-tree.c (expand_vec_cond_expr_p): Likewise.
* optabs.c (expand_vector_broadcast, expand_binop_directly): Likewise.
(shift_amt_for_vec_perm_mask, expand_vec_perm_var): Likewise.
(expand_vec_cond_expr, expand_mult_highpart): Likewise.
* rtlanal.c (subreg_get_info): Likewise.
* tree-vect-data-refs.c (vect_grouped_store_supported): Likewise.
(vect_grouped_load_supported): Likewise.
* tree-vect-generic.c (type_for_widest_vector_mode): Likewise.
* tree-vect-loop.c (have_whole_vector_shift): Likewise.
* simplify-rtx.c (simplify_unary_operation_1): Likewise.
(simplify_const_unary_operation, simplify_binary_operation_1)
(simplify_const_binary_operation, simplify_ternary_operation)
(test_vector_ops_duplicate, test_vector_ops): Likewise.
(simplify_immed_subreg): Use GET_MODE_NUNITS on a fixed_size_mode
instead of CONST_VECTOR_NUNITS.
* varasm.c (output_constant_pool_2): Likewise.
* rtx-vector-builder.c (rtx_vector_builder::build): Only include the
explicit-encoded elements in the XVEC for variable-length vectors.

gcc/ada/
* gcc-interface/misc.c (enumerate_modes): Handle polynomial
GET_MODE_NUNITS.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256195

Use partial_subreg_p in curr_insn_transform

Use partial_subreg_p in code that was added since the initial patch
that introduced this function.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* lra-constraints.c (curr_insn_transform): Use partial_subreg_p.

From-SVN: r256194

Add a fixed_size_mode_pod class

This patch adds a POD version of fixed_size_mode.  The only current use
is for storing the __builtin_apply and __builtin_result register modes,
which were made fixed_size_modes by the previous patch.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* coretypes.h (fixed_size_mode): Declare.
(fixed_size_mode_pod): New typedef.
* builtins.h (target_builtins::x_apply_args_mode)
(target_builtins::x_apply_result_mode): Change type to
fixed_size_mode_pod.
* builtins.c (apply_args_size, apply_result_size, result_vector)
(expand_builtin_apply_args_1, expand_builtin_apply)
(expand_builtin_return): Update accordingly.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256193

Directly operate on CONST_VECTOR encoding

This patch makes some pieces of code operate directly on the new
CONST_VECTOR encoding.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* cse.c (hash_rtx_cb): Hash only the encoded elements.
* cselib.c (cselib_hash_rtx): Likewise.
* expmed.c (make_tree): Build VECTOR_CSTs directly from the
CONST_VECTOR encoding.

From-SVN: r256192

re PR target/83641 (-fstack-clash-protection generates incorrect CFI on i386)

PR target/83641
* config/i386/i386.c (ix86_adjust_stack_and_probe_stack_clash): For
noreturn probe, use gen_pop instead of ix86_emit_restore_reg_using_pop,
only set RTX_FRAME_RELATED_P on both the push and pop if cfa_reg is sp
and add REG_CFA_ADJUST_CFA notes in that case to both insns.

PR target/83641
* config/i386/i386.c (ix86_adjust_stack_and_probe_stack_clash): Do not
explicitly probe *sp in a noreturn function if there were any callee
register saves or frame pointer is needed.

PR target/83641
* gcc.target/i386/stack-check-17.c: New test.
* gcc.target/i386/stack-check-12.c: Drop unnecessary asm.

From-SVN: r256191

re PR debug/83621 (ICE: in simplify_subreg, at simplify-rtx.c:6293 with -O -g)

PR debug/83621
* cfgexpand.c (expand_debug_expr): Return NULL if mode is
BLKmode for ternary, binary or unary expressions.

* gcc.dg/pr83621.c: New test.

From-SVN: r256190

re PR debug/83645 (ICE: in get_insn_template, at final.c:2100 with -gstatement-frontiers)

PR debug/83645
* var-tracking.c (delete_vta_debug_insn): New inline function.
(delete_vta_debug_insns): Add USE_CFG argument, if true, walk just
insns from get_insns () to NULL instead of each bb separately.
Use delete_vta_debug_insn.  No longer static.
(vt_debug_insns_local, variable_tracking_main_1): Adjust
delete_vta_debug_insns callers.
* rtl.h (delete_vta_debug_insns): Declare.
* final.c (rest_of_handle_final): Call delete_vta_debug_insns
instead of variable_tracking_main.

* gcc.dg/pr83645.c: New test.

From-SVN: r256189

PR c/83559 - -Wsuggest-attribute=const conflicts with -Wattributes warning about const attribute on function returning void

gcc/ChangeLog:

PR c/83559
* doc/extend.texi (attribute const): Fix a typo.
* ipa-pure-const.c ((warn_function_const, warn_function_pure): Avoid
issuing -Wsuggest-attribute for void functions.

gcc/testsuite/ChangeLog:

PR c/83559
* gcc.dg/const-2.c: New test.
* gcc.dg/pure-3.c: New test.

From-SVN: r256188

gimple-ssa-warn-restrict.c (builtin_memref::builtin_memref): Use offset_int::from instead of wide_int::to_shwi.

gcc/ChangeLog:

* gimple-ssa-warn-restrict.c (builtin_memref::builtin_memref): Use
offset_int::from instead of wide_int::to_shwi.
(maybe_diag_overlap): Remove assertion.
Use HOST_WIDE_INT_PRINT_DEC instead of %lli.
* gimple-ssa-sprintf.c (format_directive): Same.
(parse_directive): Same.
(sprintf_dom_walker::compute_format_length): Same.
(try_substitute_return_value): Same.

gcc/testsuite/ChangeLog:

* gcc.dg/Wrestrict-3.c: New test.

From-SVN: r256187

re PR c++/83555 (Unnecessary null check when static_cast is used with references.)

PR c++/83555
* typeck.c (build_static_cast_1): For static casts to reference types,
call build_base_path with flag_delete_null_pointer_checks as nonnull
instead of always false.  When -fsanitize=null, call
ubsan_maybe_instrument_reference on the NULL reference INTEGER_CST.
* cp-gimplify.c (cp_genericize_r): Don't walk subtrees of UBSAN_NULL
call if the first argument is INTEGER_CST with REFERENCE_TYPE.

* g++.dg/opt/pr83555.C: New test.
* g++.dg/ubsan/pr83555.C: New test.

From-SVN: r256186

Protect optional's deduction guide with the feature macro

* include/std/optional: Use the feature macro.

From-SVN: r256185

Fix warning in gcc.dg/plugin/expensive_selftests_plugin.c with !CHECKING_P

gcc/testsuite/ChangeLog:
* gcc.dg/plugin/expensive-selftests-1.c: Update regexp to handle
the !CHECKING_P case by expecting a note.
* gcc.dg/plugin/expensive_selftests_plugin.c (plugin_init): Issue
a note for the !CHECKING_P case, and move the return statement
outside of #if CHECKING_P guard.

From-SVN: r256183

re PR middle-end/83654 (-fstack-clash-protection probes below the stack pointer for VLA with constant size)

PR middle-end/83654
* explow.c (anti_adjust_stack_and_probe_stack_clash): Test a
non-constant residual for zero at runtime and avoid probing in
that case.  Reorganize code for trailing problem to mirror handling
of the residual.

PR middle-end/83654
* gcc.target/i386/stack-check-18.c: New test.
* gcc.target/i386/stack-check-19.c: New test.

From-SVN: r256182

PR tree-optimization/83501 - strlen(a) not folded after strcpy(a, "...")

gcc/testsuite/ChangeLog:
* c-c++-common/Warray-bounds-3.c: Remove xfail.

From-SVN: r256181

re PR tree-optimization/83501 (strlen(a) not folded after strcpy(a, "..."))

2018-01-03  Prathamesh Kulkarni  <prathamesh.kulkarni@linaro.org>

PR tree-optimization/83501
* tree-ssa-strlen.c (get_string_cst): New.
(handle_char_store): Call get_string_cst.

testsuite/
* gcc.dg/tree-ssa/pr83501.c: New test.

From-SVN: r256180

[PR c++/83667] Fix tree_dump ICE

https://gcc.gnu.org/ml/gcc-patches/2018-01/msg00148.html
PR c++/83667
* method.c (make_alias_for): Copy DECL_CONTEXT.

PR c++/83667
* g++.dg/ipa/pr83667.C: New.

From-SVN: r256179

Clean-up EH after strlen transformation (PR tree-optimization/83593).

2018-01-03  Martin Liska  <mliska@suse.cz>

PR tree-optimization/83593
* tree-ssa-strlen.c: Include tree-cfg.h.
(strlen_check_and_optimize_stmt): Add new argument cleanup_eh.
(strlen_dom_walker): Add new member variable m_cleanup_cfg.
(strlen_dom_walker::strlen_dom_walker): Initialize m_cleanup_cfg
to false.
(strlen_dom_walker::before_dom_children): Call
gimple_purge_dead_eh_edges. Dump tranformation with details
dump flags.
(strlen_dom_walker::before_dom_children): Update call by adding
new argument cleanup_eh.
(pass_strlen::execute): Return TODO_cleanup_cfg if needed.
2018-01-03  Martin Liska  <mliska@suse.cz>

PR tree-optimization/83593
* gcc.dg/pr83593.c: New test.

From-SVN: r256178

Do not inline variadic thunks (PR ipa/83549).

2018-01-03  Martin Liska  <mliska@suse.cz>

PR ipa/83549
* cif-code.def (VARIADIC_THUNK): New enum value.
* ipa-fnsummary.c (compute_fn_summary): Do not inline variadic
thunks.
2018-01-03  Martin Liska  <mliska@suse.cz>

PR ipa/83549
* g++.dg/ipa/pr83549.C: New test.

From-SVN: r256177

re PR c++/83592 (Annoying -Wparentheses warnings)

PR c++/83592
* decl.c (grokdeclarator): Don't warn about MVP in typename context.

* g++.dg/warn/mvp2.C: New test.

From-SVN: r256176

re PR preprocessor/83602 (ICE in cpp_macro_definition_location(cpp_hashnode*) on invalid code)

PR preprocessor/83602
* name-lookup.c (lookup_name_fuzzy): Don't use macro_use_before_def
for builtin macros.

* g++.dg/cpp/pr83602.C: New test.

From-SVN: r256175

re PR c++/83634 (ICE in useless_type_conversion_p, at gimple-expr.c:86)

PR c++/83634
* cp-gimplify.c (cp_fold) <case NOP_EXPR>: If the operand folds to
error_mark_node, return error_mark_node.

* g++.dg/parse/pr83634.C: New test.

From-SVN: r256174

re PR fortran/83664 (Eoshift accepts missing boundary for non-default types)

2018-01-03  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/83664
* check.c (gfc_check_eoshift): Error for missing boundary if array
is not one of the standard types.

2018-01-03  Thomas Koenig  <tkoenig@gcc.gnu.org>

PR fortran/83664
* gfortran.dg/eoshift_7.f90: New test.

From-SVN: r256171

x86: don't use AVX512BW vmovdqu variants without -mavx512bw

Simply mirror the MODE_XI logic of handling unaligned operands in
mov<mode>_internal into MODE_TI / MODE_OI handling.

gcc/
2018-01-03  Jan Beulich  <jbeulich@suse.com>

* sse.md (mov<mode>_internal): Tighten condition for when to use
vmovdqu<ssescalarsize> for TI and OI modes.

gcc/testsuite/
2018-01-03  Jan Beulich  <jbeulich@suse.com>

* gcc.target/i386/avx512vl-no-vmovdqu8.c,
gcc.target/i386/avx512vl-no-vmovdqu16.c: New.

From-SVN: r256170

Update copyright years.

From-SVN: r256169

* update-copyright.py: Skip pdt-5.f03 in gfortran.dg subdir.

From-SVN: r256168

Handle noipa attribute in IPA visibility (PR ipa/83594).

2018-01-03  Martin Liska  <mliska@suse.cz>

PR ipa/83594
* ipa-visibility.c (function_and_variable_visibility): Skip
functions with noipa attribure.
2018-01-03  Martin Liska  <mliska@suse.cz>

PR ipa/83594
* gcc.dg/ipa/pr83594.c: New test.

From-SVN: r256167

gcc.c (process_command): Update copyright notice dates.

gcc/
* gcc.c (process_command): Update copyright notice dates.
* gcov-dump.c (print_version): Ditto.
* gcov.c (print_version): Ditto.
* gcov-tool.c (print_version): Ditto.
* gengtype.c (create_file): Ditto.
* doc/cpp.texi: Bump @copying's copyright year.
* doc/cppinternals.texi: Ditto.
* doc/gcc.texi: Ditto.
* doc/gccint.texi: Ditto.
* doc/gcov.texi: Ditto.
* doc/install.texi: Ditto.
* doc/invoke.texi: Ditto.
gcc/fortran/
* gfortranspec.c (lang_specific_driver): Update copyright notice
dates.
* gfc-internals.texi: Bump @copying's copyright year.
* gfortran.texi: Ditto.
* intrinsic.texi: Ditto.
* invoke.texi: Ditto.
gcc/ada/
  * gnat_ugn.texi: Bump @copying's copyright year.
  * gnat_rm.texi: Likewise.
gcc/go/
* gccgo.texi: Bump @copyrights-go year.
libitm/
* libitm.texi: Bump @copying's copyright year.
libgomp/
* libgomp.texi: Bump @copying's copyright year.
libquadmath/
* libquadmath.texi: Bump @copying's copyright year.

From-SVN: r256166

poly_int: vector_builder element count

This patch changes the number of elements in a vector being built
by a vector_builder from unsigned int to poly_uint64.  The case
in which it isn't a constant is the one that motivated adding
the vector encoding in the first place.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* vector-builder.h (vector_builder::m_full_nelts): Change from
unsigned int to poly_uint64.
(vector_builder::full_nelts): Update prototype accordingly.
(vector_builder::new_vector): Likewise.
(vector_builder::encoded_full_vector_p): Handle polynomial full_nelts.
(vector_builder::operator ==): Likewise.
(vector_builder::finalize): Likewise.
* int-vector-builder.h (int_vector_builder::int_vector_builder):
Take the number of elements as a poly_uint64 rather than an
unsigned int.
* vec-perm-indices.h (vec_perm_indices::m_nelts_per_input): Change
from unsigned int to poly_uint64.
(vec_perm_indices::vec_perm_indices): Update prototype accordingly.
(vec_perm_indices::new_vector): Likewise.
(vec_perm_indices::length): Likewise.
(vec_perm_indices::nelts_per_input): Likewise.
(vec_perm_indices::input_nelts): Likewise.
* vec-perm-indices.c (vec_perm_indices::new_vector): Take the
number of elements per input as a poly_uint64 rather than an
unsigned int.  Use the original encoding for variable-length
vectors, rather than clamping each individual element.
For the second and subsequent elements in each pattern,
clamp the step and base before clamping their sum.
(vec_perm_indices::series_p): Handle polynomial element counts.
(vec_perm_indices::all_in_range_p): Likewise.
(vec_perm_indices_to_tree): Likewise.
(vec_perm_indices_to_rtx): Likewise.
* tree-vect-stmts.c (vect_gen_perm_mask_any): Likewise.
* tree-vector-builder.c (tree_vector_builder::new_unary_operation)
(tree_vector_builder::new_binary_operation): Handle polynomial
element counts.  Return false if we need to know the number
of elements at compile time.
* fold-const.c (fold_vec_perm): Punt if the number of elements
isn't known at compile time.

From-SVN: r256165

poly_int: vec_perm_indices element type

This patch changes the vec_perm_indices element type from HOST_WIDE_INT
to poly_int64, so that it can represent indices into a variable-length
vector.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>

gcc/
* vec-perm-indices.h (vec_perm_builder): Change element type
from HOST_WIDE_INT to poly_int64.
(vec_perm_indices::element_type): Update accordingly.
(vec_perm_indices::clamp): Handle polynomial element_types.
* vec-perm-indices.c (vec_perm_indices::series_p): Likewise.
(vec_perm_indices::all_in_range_p): Likewise.
(tree_to_vec_perm_builder): Check for poly_int64 trees rather
than shwi trees.
* vector-builder.h (vector_builder::stepped_sequence_p): Handle
polynomial vec_perm_indices element types.
* int-vector-builder.h (int_vector_builder::equal_p): Likewise.
* fold-const.c (fold_vec_perm): Likewise.
* optabs.c (shift_amt_for_vec_perm_mask): Likewise.
* tree-vect-generic.c (lower_vec_perm): Likewise.
* tree-vect-slp.c (vect_transform_slp_perm_load): Likewise.
* config/aarch64/aarch64.c (aarch64_evpc_tbl): Cast d->perm
element type to HOST_WIDE_INT.

From-SVN: r256164

poly_int: memrefs_conflict_p

The xsize and ysize arguments to memrefs_conflict_p are encode such
that:

- 0 means the size is unknown
- >0 means the size is known
- <0 means that the negative of the size is a worst-case size after
  alignment

In other words, the sign effectively encodes a boolean; it isn't
meant to be taken literally.  With poly_ints these correspond to:

- must_eq (..., 0)
- may_gt (..., 0)
- may_lt (..., 0)

respectively.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* alias.c (addr_side_effect_eval): Take the size as a poly_int64
rather than an int.  Use plus_constant.
(memrefs_conflict_p): Take the sizes as poly_int64s rather than ints.
Take the offset "c" as a poly_int64 rather than a HOST_WIDE_INT.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256163

poly_int: struct_value_size

This patch makes calls.c treat struct_value_size (one of the
operands to a call pattern) as polynomial.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* calls.c (emit_call_1, expand_call): Change struct_value_size from
a HOST_WIDE_INT to a poly_int64.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256162

poly_int: load_register_parameters

This patch makes load_register_parameters cope with polynomial sizes.
The requirement here is that any register parameters with non-constant
sizes must either have a specific mode (e.g. a variable-length vector
mode) or must be represented with a PARALLEL.  This is in practice
already a requirement for parameters passed in vector registers,
since the default behaviour of splitting parameters into words doesn't
make sense for them.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* calls.c (load_register_parameters): Cope with polynomial
mode sizes.  Require a constant size for BLKmode parameters
that aren't described by a PARALLEL.  If BLOCK_REG_PADDING
forces a parameter to be padded at the lsb end in order to
fill a complete number of words, require the parameter size
to be ordered wrt UNITS_PER_WORD.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256161

poly_int: alter_reg

This patch makes alter_reg cope with polynomial mode sizes.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* reload1.c (spill_stack_slot_width): Change element type
from unsigned int to poly_uint64_pod.
(alter_reg): Treat mode sizes as polynomial.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256160

poly_int: reloading complex subregs

This patch splits out a condition that is common to both push_reload
and reload_inner_reg_of_subreg.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* reload.c (complex_word_subreg_p): New function.
(reload_inner_reg_of_subreg, push_reload): Use it.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256159

poly_int: process_alt_operands

This patch makes process_alt_operands check that the mode sizes
are ordered, so that match_reload can validly treat them as subregs
of one another.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* lra-constraints.c (process_alt_operands): Reject matched
operands whose sizes aren't ordered.
(match_reload): Refer to this check here.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256158

poly_int: expand_ifn_atomic_compare_exchange_into_call

This patch makes the mode size assumptions in
expand_ifn_atomic_compare_exchange_into_call a bit more
explicit, so that a later patch can add a to_constant () call.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* builtins.c (expand_ifn_atomic_compare_exchange_into_call): Assert
that the mode size is in the set {1, 2, 4, 8, 16}.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256157

poly_int: adjust_mems

This patch makes the var-tracking.c handling of autoinc addresses
cope with polynomial mode sizes.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* var-tracking.c (adjust_mems): Treat mode sizes as polynomial.
Use plus_constant instead of gen_rtx_PLUS.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256156

poly_int: PUSH_ROUNDING

PUSH_ROUNDING is difficult to convert to a hook since there is still
a lot of conditional code based on it.  It isn't clear that a direct
conversion with checks for null hooks is the right thing to do.

Rather than untangle that, this patch converts all implementations
that do something to out-of-line functions that have the same
interface as a hook would have.  This should at least help towards
any future hook conversion.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* config/cr16/cr16-protos.h (cr16_push_rounding): Declare.
* config/cr16/cr16.h (PUSH_ROUNDING): Move implementation to...
* config/cr16/cr16.c (cr16_push_rounding): ...this new function.
* config/h8300/h8300-protos.h (h8300_push_rounding): Declare.
* config/h8300/h8300.h (PUSH_ROUNDING): Move implementation to...
* config/h8300/h8300.c (h8300_push_rounding): ...this new function.
* config/i386/i386-protos.h (ix86_push_rounding): Declare.
* config/i386/i386.h (PUSH_ROUNDING): Move implementation to...
* config/i386/i386.c (ix86_push_rounding): ...this new function.
* config/m32c/m32c-protos.h (m32c_push_rounding): Take and return
a poly_int64.
* config/m32c/m32c.c (m32c_push_rounding): Likewise.
* config/m68k/m68k-protos.h (m68k_push_rounding): Declare.
* config/m68k/m68k.h (PUSH_ROUNDING): Move implementation to...
* config/m68k/m68k.c (m68k_push_rounding): ...this new function.
* config/pdp11/pdp11-protos.h (pdp11_push_rounding): Declare.
* config/pdp11/pdp11.h (PUSH_ROUNDING): Move implementation to...
* config/pdp11/pdp11.c (pdp11_push_rounding): ...this new function.
* config/stormy16/stormy16-protos.h (xstormy16_push_rounding): Declare.
* config/stormy16/stormy16.h (PUSH_ROUNDING): Move implementation to...
* config/stormy16/stormy16.c (xstormy16_push_rounding): ...this new
function.
* expr.c (emit_move_resolve_push): Treat the input and result
of PUSH_ROUNDING as a poly_int64.
(emit_move_complex_push, emit_single_push_insn_1): Likewise.
(emit_push_insn): Likewise.
* lra-eliminations.c (mark_not_eliminable): Likewise.
* recog.c (push_operand): Likewise.
* reload1.c (elimination_effects): Likewise.
* rtlanal.c (nonzero_bits1): Likewise.
* calls.c (store_one_arg): Likewise.  Require the padding to be
known at compile time.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256155

poly_int: emit_single_push_insn_1

This patch makes emit_single_push_insn_1 cope with polynomial mode sizes.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* expr.c (emit_single_push_insn_1): Treat mode sizes as polynomial.
Use plus_constant instead of gen_rtx_PLUS.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256154

poly_int: set_inc_state

This trivial patch makes auto-inc-dec.c:set_inc_state take a poly_int64.

2018-01-03  Richard Sandiford  <richard.sandiford@linaro.org>
    Alan Hayward  <alan.hayward@arm.com>
    David Sherwood  <david.sherwood@arm.com>

gcc/
* auto-inc-dec.c (set_inc_state): Take the mode size as a poly_int64
rather than an int.

Co-Authored-By: Alan Hayward <alan.hayward@arm.com>
Co-Authored-By: David Sherwood <david.sherwood@arm.com>
From-SVN: r256153