targets/dri-swrast: convert to gallium megadrivers :)

Export the approapriate new symbol, and keep backwards compat
via the megadriver_stub helper library.

Our next step would be to unify dri/drm and dri/sw, leading to
a complete megadrivers solution, and having a single library
that provides dri across all targets.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Thomas Helland <thomashelland90 at gmail.com>
Acked-by: Tom Stellard <thomas.stellard@amd.com>

scons: build and use a single dri_common library

Rather than building two identical ones for dri-vmwgfx and dri-swrast
build a single library, and drop some duplication in the build.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Thomas Helland <thomashelland90 at gmail.com>
Acked-by: Tom Stellard <thomas.stellard@amd.com>

st/dri/drm: remove __driDriverExtensions and driDriverAPI

... and use libmegadriver_stub as their provider.
Teach scons how to build the library archive and use it.

v2: scons: fix build on a drm-less system.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Thomas Helland <thomashelland90 at gmail.com>
Acked-by: Tom Stellard <thomas.stellard@amd.com>

targets/dri: cleanup conversion leftovers

With all the users converted to __driGetExtensions_* we can
have only a single inclusion of the required header + define.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Thomas Helland <thomashelland90 at gmail.com>
Acked-by: Tom Stellard <thomas.stellard@amd.com>

targets/dri: update scons build to handle __driDriverGetExtensions_vmwgfx

Cc: Jose Fonseca <jfonseca@vmware.com>
Cc: Brian Paul <brianp@vmware.com>
Cc: Jakob Bornecrantz <jakob@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Thomas Helland <thomashelland90 at gmail.com>
Acked-by: Tom Stellard <thomas.stellard@amd.com>

targets/dri: Add __driDriverGetExtensions_vmwgfx

Identical to previous commits - will bring us a step closer
to megadrivers.

Cc: Jose Fonseca <jfonseca@vmware.com>
Cc: Brian Paul <brianp@vmware.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Thomas Helland <thomashelland90 at gmail.com>
Acked-by: Tom Stellard <thomas.stellard@amd.com>

targets/dri: Add __driDriverGetExtensions_i965 symbol

Identical to previous commits - will bring us a step closer
to megadrivers.

Cc: Chia-I Wu <olv@lunarg.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Thomas Helland <thomashelland90 at gmail.com>
Acked-by: Tom Stellard <thomas.stellard@amd.com>

targets/dri: Add __driDriverGetExtensions_i915 symbol

Identical to previous commits - will bring us a step closer
to megadrivers.

Cc: Stephane Marchesin <stephane.marchesin@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Thomas Helland <thomashelland90 at gmail.com>
Acked-by: Tom Stellard <thomas.stellard@amd.com>

targets/dri: Add __driDriverGetExtensions_freedreno symbol

Identical to previous two commits - will bring us a step closer
to megadrivers.

Cc: Rob Clark <robclark@freedesktop.org>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Thomas Helland <thomashelland90 at gmail.com>
Acked-by: Tom Stellard <thomas.stellard@amd.com>

targets/dri: Add __driDriverGetExtensions_(r300|r600|radeonsi) symbols

The symbol is introduced by the mesa megadrivers, and
adding gallium support for it will allow us to merge
st/dri/drm and st/dri/sw. Resulting in a single dri library
across all of gallium.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Thomas Helland <thomashelland90 at gmail.com>
Acked-by: Tom Stellard <thomas.stellard@amd.com>

targets/dri: Add __driDriverGetExtensions_nouveau symbol

The symbol is introduced by the mesa megadrivers, and adding
gallium support for it will allow us to merge st/dri/drm and
st/dri/sw. Resulting in a single dri library across gallium.

v2: Rebase on top of gallium dri3.

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Rob Clark <robclark@freedesktop.org>
Tested-by: Thomas Helland <thomashelland90 at gmail.com>
Acked-by: Tom Stellard <thomas.stellard@amd.com>

tgsi: add interpolation location modifier support to text parser

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa/st: add per sample shading state to fp key and set interpolation

This enables a gallium driver not to care about the semantics of
ARB_sample_shading vs ARB_gpu_shader5 sample attributes. When
ARB_sample_shading-style sample shading is enabled, all of the fp inputs
are marked for interpolation at the sample location.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

gallium: switch dedicated centroid field to interpolation location

The new location field can be either center, centroid, or sample, which
indicates the location that the shader should interpolate at.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

meta: Call glObjectLabel before linking.

i965 precompiles shaders at link time, and prints a disassembly if
INTEL_DEBUG=vs,gs,fs, including the shader name.  However, blit shaders
were showing up as "unnamed" since we hadn't set a name prior to
linking.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

ff_fragment_shader: Access glsl_types directly.

Originally, we didn't have direct accessors for all of the GLSL types,
so the only way to get at them was to use the symbol table.  Now, we
can just get at them directly, which is simpler and faster.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>

st/mesa: add PIPE_FORMAT_R10G10B10A2_UNORM to format_map table

as a candidate for the GL_RGB10_A2 internal texture format.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: add some missing MESA/PIPE_FORMAT_R10G10B10A2_UNORM switch cases

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glsl/glcpp: Don't choke on an empty pragma

The lexer was insisting that there be at least one character after "#pragma"
and before the end of the line. This caused an error for a line consisting
only of "#pragma" which volates at least the following sentence from the GLSL
ES Specification 3.00.4:

The scope as well as the effect of the optimize and debug pragmas is
implementation-dependent except that their use must not generate an
error. [Page 12 (Page 28 of PDF)]

and likely the following sentence from that specification and also in
GLSLangSpec 4.30.6:

If an implementation does not recognize the tokens following #pragma,
then it will ignore that pragma.

Add a "make check" test to ensure no future regressions.

This change fixes at least part of the following Khronos GLES3 CTS test:

preprocessor.pragmas.pragma_vertex

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl/glcpp: Promote "extra token at end of directive" from warning to error

We've always warned about this case, but a recent confromance test expects
this to be an error that causes compilation to fail. Make it so.

Also add a "make check" test to ensure these errors are generated.

This fixes the following Khronos GLES3 conformance tests:

invalid_conditionals.tokens_after_ifdef_vertex
invalid_conditionals.tokens_after_ifdef_fragment
invalid_conditionals.tokens_after_ifndef_vertex
invalid_conditionals.tokens_after_ifndef_fragment

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl/glcpp: Once again report undefined macro name in error message.

While writing the previous commit message, I just felt bad documenting the
shortcoming of the change, (that undefined macro names would not be reported
in error messages).

Fix this by preserving the first-encounterd undefined macro name and reporting
that in any resulting error message.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl/glcpp: Add short-circuiting for || and && in #if/#elif for OpenGL ES.

The GLSL ES Specification 3.00.4 says:

#if, #ifdef, #ifndef, #else, #elif, and #endif are defined to operate
        as for C++ except for the following:
...
• Undefined identifiers not consumed by the defined operator do not
  default to '0'. Use of such identifiers causes an error.

[Page 11 (page 127 of the PDF file)]

as well as:

The semantics of applying operators in the preprocessor match those
standard in the C++ preprocessor with the following exceptions:

• The 2nd operand in a logical and ('&&') operation is evaluated if
  and only if the 1st operand evaluates to non-zero.

• The 2nd operand in a logical or ('||') operation is evaluated if
  and only if the 1st operand evaluates to zero.

If an operand is not evaluated, the presence of undefined identifiers
in the operand will not cause an error.

(Note that neither of these deviations from C++ preprocessor behavior apply to
non-ES GLSL, at least as of specfication version 4.30.6).

The first portion of this, (generating an error for an undefined macro in an
(short-circuiting to squelch errors), was not implemented previously, but is
implemented in this commit.

A test is added for "make check" to ensure this behavior.

Note: The change as implemented does make the error message a bit less
precise, (it just states that an undefined macro was encountered, but not the
name of the macro).

This commit fixes the following Khronos GLES3 conformance test:

undefined_identifiers.valid_undefined_identifier_1_vertex
undefined_identifiers.valid_undefined_identifier_1_fragment
undefined_identifiers.valid_undefined_identifier_2_vertex
undefined_identifiers.valid_undefined_identifier_2_fragment

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

glsl/glcpp: Fix glcpp to properly lex entire "preprocessing numbers"

The preprocessor defines a notions of a "preprocessing number" that
starts with either a digit or a decimal point, and continues with zero
or more of digits, decimal points, identifier characters, or the sign
symbols, ('-' and '+').

Prior to this change, preprocessing numbers were lexed as some
combination of OTHER and IDENTIFIER tokens. This had the problem of
causing undesired macro expansion in some cases.

We add tests to ensure that the undesired macro expansion does not
happen in cases such as:

#define e +1
#define xyz -2

int n = 1e;
int p = 1xyz;

In either case these macro definitions have no effect after this
change, so that the numeric literals, (whether valid or not), will be
passed on as-is from the preprocessor to the compiler proper.

This fixes the following Khronos GLES3 CTS tests:

preprocessor.basic.correct_phases_vertex
preprocessor.basic.correct_phases_fragment

v2. Thanks to Anuj Phogat for improving the original regular expression,
(which accepted a '+' or '-', where these are only allowed after one of
[eEpP]. I also expanded the test to exercise this.

v3. Also fixed regular expression to require at least one digit at the
beginning (after an optional period). Otherwise, a string such as ".xyz" was
getting sucked up as a preprocessing number, (where obviously this should be a
field access). Again, I expanded the test to exercise this.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

glsl/glcpp: Fix glcpp to catch garbage after #if 1 ... #else

Previously, a line such as:

#else garbage

would flag an error if it followed "#if 0", but not if it followed "#if 1".

We fix this by setting a new bit of state (lexing_else) that allows the lexer
to defer switching to the <SKIP> start state until after the NEWLINE following
the #else directive.

A new test case is added for:

#if 1
#else garbage
#endif

which was untested before, (and did not generate the desired error).

This fixes the following Khronos GLES3 CTS tests:

tokens_after_else_vertex
        tokens_after_else_fragment

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

glsl/glcpp: Fixup glcpp tests for redefining a macro with whitespace changes.

Previously, the test suite was expecting the compiler to allow a redefintion
of a macro with whitespace added, but gcc is more strict and allows only for
changes in the amounts of whitespace, (but insists that whitespace exist or
not in exactly the same places).

See: https://gcc.gnu.org/onlinedocs/cpp/Undefining-and-Redefining-Macros.html:

 These definitions are effectively the same:

      #define FOUR (2 + 2)
      #define FOUR         (2    +    2)
      #define FOUR (2 /* two */ + 2)

 but these are not:

      #define FOUR (2 + 2)
      #define FOUR ( 2+2 )
      #define FOUR (2 * 2)
      #define FOUR(score,and,seven,years,ago) (2 + 2)

This change adjusts the existing "redefine-macro-legitimate" test to work with
the more strict understanding, and adds a new "redefine-whitespace" test to
verify that changes in the position of whitespace are flagged as errors.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

glsl/glcpp: Fix preprocessor error condition for macro redefinition

This patch specifically fixes redefinition condition for white space
changes. #define and #undef functionality in GLSL follows the standard
for C++ preprocessors for macro definitions.

From https://gcc.gnu.org/onlinedocs/cpp/Undefining-and-Redefining-Macros.html:

These definitions are effectively the same:

     #define FOUR (2 + 2)
     #define FOUR         (2    +    2)
     #define FOUR (2 /* two */ + 2)

but these are not:

     #define FOUR (2 + 2)
     #define FOUR ( 2+2 )
     #define FOUR (2 * 2)
     #define FOUR(score,and,seven,years,ago) (2 + 2)

Fixes Khronos GLES3 CTS tests;
invalid_object_whitespace_vertex
invalid_object_whitespace_fragment

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Carl Worth <cworth@cworth.org>

glsl/glcpp: Add test to ensure compiler won't allow #undef for some builtins

Currently verifying that an #undef of __FILE__, __LINE__, or __VERSION__ will
generate an error.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

glsl/glcpp: Do not allow undefining the built-in macros

Fixes piglit tests in spec/glsl-es-3.00/compile:
undef-__FILE__.vert
undef-GL_ES.vert
undef-__LINE__.vert
undef-__VERSION__.vert

Also, fixes Khronos GLES3 CTS tests:
undefine_invalid_object_1_vertex
undefine_invalid_object_1_fragment
undefine_invalid_object_2_vertex
undefine_invalid_object_2_fragment

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Carl Worth <cworth@cworth.org>

gallium/u_blitter: fix some shader memory leaks

The _msaa shaders weren't getting freed.
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

tgsi: properly parse indirect dimension references (e.g. for UBOs)

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Brian Paul <brianp@vmware.com>

radeonsi: fix order of r600_need_dma_space and r600_context_bo_reloc

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: fix geometry shader memory leak

Spotted by Charmaine Lee.
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>

mesa: fix geometry shader memory leaks

Spotted by Charmaine Lee.
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

st/mesa: minor simplification of some state atom assignments

st/mesa: minor fix-up in st_GetSamplePosition()

If the driver doesn't implement get_sample_position(), let's return
some non-garbage values.

mesa: use float to silence MSVC warning in _mesa_GetMultisamplefv()

nvc0: allocate more space before a counter is configured

On nvc0, a counter can have up to 6 sources instead of only one
for nve4+. This fixes a crash when a counter uses more than
one source.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

nv50/ir: use unordered_set instead of list to keep track of var uses

The set of variable uses does not need to be ordered in any way, and
removing/adding elements is a fairly common operation in various
optimization passes.

This shortens runtime of piglit test fp-long-alu to ~22s from ~4h

Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

i965/disasm: Fix disassembly of the any16h/all16h predicates.

BRW_PREDICATE_ALIGN1_ANY16H was incorrectly being disassembled as
"all16h", and ALL16H would probably print as "(null)".

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

glsl: Fix the foreach_in_list_reverse macro.

We clearly don't want to start at the head and walk backwards; we want
to start at the last real element before the tail sentinel.  If the list
is empty, tail_pred will be the head sentinel, and we'll stop.

Nothing uses this function, so I guess nobody noticed it was broken.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

radeonsi: mark MSAA config state as dirty at the beginning of CS

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=81020

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

gallium: fix u_default_transfer_inline_write for textures

This doesn't fix any known issue. In fact, radeon drivers ignore all
the discard flags for textures and implicitly do "discard range"
for any write transfer.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

i965: Remove artificial dependency between math instructions.

... on Gen6+. I'm not actually sure which class Gen6 fits into.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Track dependencies in instruction scheduling per reg offset.

Previously instruction scheduling tracked dependencies on a per-register
basis. This meant that there was an artificial dependency between
interpolation instructions writing into the same virtual register.

Instruction scheduling would insert a number of instructions between the
two instructions in this example, when they are actually independent.

   linterp vgrf8+0.0:F, hw_reg2:F, hw_reg3:F, hw_reg6:F
   linterp vgrf8+1.0:F, hw_reg2:F, hw_reg3:F, hw_reg6+16:F

This lead to cases where the first texture coordinate is interpolated at
the beginning of the shader, but the second is done immediately before
the texture operation that uses it as a source.

After this change, the artificial dependency is removed and the
interpolation instructions are scheduled together.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

configure: Don't special case Cygwin to use gnu99, define _XOPEN_SOURCE instead

Revert "build: Build on Cygwin with gnu99 instead of c99." and define
_XOPEN_SOURCE appropriately.

This reverts commit 53e36d333c9b619c1a5fe9a8d2d08665654b0234.

Since Cygwin 1.7.18 (April 2013), it's headers correctly prototype strtoll()
when using -std=c99, and correctly prototype strdup() when _XOPEN_SOURCE is
defined appropriately, so this workaround is no longer needed.

Signed-off-by: Jon TURNEY <jon.turney@dronecode.org.uk>
Cc: Vinson Lee <vlee@freedesktop.org>

ilo: fix fence reference counting

The old code was complicated, and was wrong when *ptr is NULL.

i965: Extend compute-to-mrf pass to understand blocks of MOVs

The current compute-to-mrf pass doesn't handle blocks of MOVs.  Shaders
that end with a texture fetch follwed by an fb write are left like this:

0x00000000: pln(8)          g6<1>F          g4<0,1,0>F      g2<8,8,1>F      { align1 WE_normal 1Q compacted };
0x00000008: pln(8)          g7<1>F          g4.4<0,1,0>F    g2<8,8,1>F      { align1 WE_normal 1Q compacted };
0x00000010: send(8)         g2<1>UW         g6<8,8,1>F
                            sampler (1, 0, 0, 1) mlen 2 rlen 4              { align1 WE_normal 1Q };
0x00000020: mov(8)          g113<1>F        g2<8,8,1>F                      { align1 WE_normal 1Q compacted };
0x00000028: mov(8)          g114<1>F        g3<8,8,1>F                      { align1 WE_normal 1Q compacted };
0x00000030: mov(8)          g115<1>F        g4<8,8,1>F                      { align1 WE_normal 1Q compacted };
0x00000038: mov(8)          g116<1>F        g5<8,8,1>F                      { align1 WE_normal 1Q compacted };
0x00000040: sendc(8)        null            g113<8,8,1>F
                            render ( RT write, 0, 4, 12) mlen 4 rlen 0      { align1 WE_normal 1Q EOT };

This patch lets compute-to-mrf recognize blocks of MOVs and match them to
instructions (typically SEND) that writes multiple registers.  With this,
the above shader becomes:

0x00000000: pln(8)          g6<1>F          g4<0,1,0>F      g2<8,8,1>F      { align1 WE_normal 1Q compacted };
0x00000008: pln(8)          g7<1>F          g4.4<0,1,0>F    g2<8,8,1>F      { align1 WE_normal 1Q compacted };
0x00000010: send(8)         g113<1>UW       g6<8,8,1>F
                            sampler (1, 0, 0, 1) mlen 2 rlen 4              { align1 WE_normal 1Q };
0x00000020: sendc(8)        null            g113<8,8,1>F
                            render ( RT write, 0, 20, 12) mlen 4 rlen 0     { align1 WE_normal 1Q EOT };

which is the bulk of the shader db results:

total instructions in shared programs: 987040 -> 986720 (-0.03%)
instructions in affected programs:     844 -> 524 (-37.91%)
GAINED:                                0
LOST:                                  0

The optimization also applies to MRT shaders that write the same
color value to multiple RTs, in which case we can eliminate four MOVs in
a similar fashion.  See fbo-drawbuffers2-blend in piglit for an example.

No measurable performance impact.  No piglit regressions.

Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>

nvc0/ir: fill offset in properly for TXD

Apparently TXD wants its offset differently than TEX, accepting it in
the upper bits of the layer index. Unclear what happens when this is
combined with indirect sampler indexing.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

nvc0/ir: use manual TXD when offsets are involved

Something about how we're implementing offsets for TXD is wrong, just
flip to the generic quadop-based implementation in that case.

This is the minimal fix appropriate for backporting.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>

nvc0/ir: do quadops on the right texture coordinates for TXD

handleTEX moves the layer as the first argument. This makes sure that
the quadops deal with the texture coordinates.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>

nv50/ir: ignore bias for samplerCubeShadow on nv50

Unfortunately there's no good way to do this on the nv50 shader isa.
Dropping the bias seems preferable to doing the compare post-filtering.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>

nv50/ir: retrieve shadow compare from first arg

This can only happen with texture(samplerCubeShadow, bias), where the
compare will be in the first argument.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: <mesa-stable@lists.freedesktop.org>

docs: Import 10.2.3 release notes

And add a news item.

i965/fs: Disable unlit_centroid_workaround on Haswell.

Although the HSW PRM shows it, the BSpec lists this workaround as being
for Ivybridge only.

total instructions in shared programs: 1994951 -> 1993675 (-0.06%)
instructions in affected programs:     27325 -> 26049 (-4.67%)

i965/vec4: Perform CSE on CMP(N) instructions.

Port of commit b16b3c87 to the vec4 code.

No shader-db improvements, but might as well. The fs backend saw an
improvement because it's scalar and multiple identical CMP instructions
were generated by the SEL peepholes.

i965/vec4: Don't emit null MOVs in CSE.

Port of commit 219b43c6 to the vec4 code.

i965/vec4: Improve CSE performance by expiring some available expressions.

Port of commit 5daf867f to the vec4 code.

i965/vec4: Add basic common subexpression elimination.

[mattst88]: Modified to perform CSE on instructions with
            the same writemask. Offered no improvement before.

total instructions in shared programs: 1995633 -> 1995185 (-0.02%)
instructions in affected programs:     14410 -> 13962 (-3.11%)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Fix warnings introduced in commit e24ef5ab.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

gallium/radeon: use PRIX64 instead of PRIu64

We want hex values here, not decimals.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

i965: Move assembly annotation functions to intel_asm_annotation.c.

It's C. Compile it as such.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Rename intel_asm_printer -> intel_asm_annotation.

The #ifndef include guards already said the right thing :)

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Make backend_instruction usable from C.

With a hack to place an exec_node in the struct in C to be at the same
location as the inherited exec_node in C++.

Acked-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965/cfg: Make cfg_t usable from C.

Acked-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Repack backend_instruction struct.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Make a brw_predicate enum.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Make a brw_conditional_mod enum.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Move common fields into backend_instruction.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Use enum brw_reg_type for register types.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Move is_zero/one/null/accumulator into backend_reg.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Make a common backend_reg class.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Drop imm union from visitor register classes.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

i965: Use immediate storage in brw_reg for visitor regs.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>

docs: add news item for mesa-demos 8.2.0 release

glsl: Fix merging of layout(invocations) with other qualifiers

If another layout qualifier appeared to the left of `invocations` in the
GS input layout declaration, the invocation count would be dropped on
the floor.

Fixes the piglit tests:

spec/ARB_transform_feedback3/arb_transform_feedback3-ext_interleaved_two_bufs_gs_max
spec/ARB_gpu_shader5/arb_gpu_shader5-invocation-id
spec/ARB_gpu_shader5/compiler/correct-multiple-layout-qualifier-invocations.geom
spec/ARB_gpu_shader5/execution/invocations-conflicting

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

nvc0: add a memory barrier when there are persistent UBOs

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>

nv50: do an explicit flush on draw when there are persistent buffers

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>

nv50: disable dedicated ubo upload method

The hardware allows multiple simultaneous renders with the same
memory-backed constbufs but with each invocation having different
values. However in order for that to work, the data has to be streamed
in via the right constbuf slot. We weren't doing that for UBOs.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2 10.1" <mesa-stable@lists.freedesktop.org>

gallium: rename PIPE_CAP_TGSI_VS_LAYER to also have _VIEWPORT

Now that this cap is used to determine the availability of both, adjust
its name to reflect the new reality.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa/st: enable AMD_vertex_shader_viewport_index

The assumption is that any driver capable of emitting layer from the
vertex shader and supporting viewports should be able to also handle
emitting viewport index from the vertex shader.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Tobias Droste <tdroste@gmx.de>

r600g: allow vs to write to gl_ViewportIndex

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Tobias Droste <tdroste@gmx.de>

svga: Don't unnecessarily reemit BindGBShader commands v2

The Linux winsys can no longer relocate shader code, so avoid
reemitting BindGBShader commands. They are costly.

v2: Correctly handle errors from SVGA3D_BindGBShader()

Reported-by: Michael Banack <banackm@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Tested-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>

radeon/llvm: Allocate space for kernel metadata operands

Previously, we were assuming that kernel metadata nodes only had 1 operand.

Kernels which have attributes can have more than 1, e.g.:
!0 = metadata !{void (i32 addrspace(1)*)* @testKernel, metadata !1}
!1 = metadata !{metadata !"work_group_size_hint", i32 4, i32 1, i32 1}

Attempting to get the kernel without the correct number of attributes led
to memory corruption and luxrays crashing out.

Fixes the cl/program/execute/attributes.cl piglit test.

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76223
CC: "10.2" <mesa-stable@lists.freedesktop.org>

glsl: fix duplicated layout qualifier detection for GS

This patch fixes the duplicated layout qualifier detection
for geometry shader's layout qualifiers.

Also it makes the detection code more legible by defining
allowed_duplicates_mask variable.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80778
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

svga: add switch cases for PIPE_SHADER_CAP_DOUBLES

Signed-off-by: Brian Paul <brianp@vmware.com>

st/xa: Don't close the drm fd on failure v2

If XA fails to initialize with pipe_loader enabled, the pipe_loader's
cleanup function will close the drm file descriptor. That's pretty bad
because the file descriptor will probably be the X server driver's only
connection to drm. Temporarily solve this by dup()'ing the file descriptor
before handing it over to the pipe loader.

This fixes freedesktop.org bugzilla bug #80645.

v2: Fix CC addresses.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>

Revert "radeonsi: Use dma_copy when possible for si_blit."

This reverts commit 5d5c20920e0e570742a497aa047e99a2fa3c04f2.

Caused visual corruption, see e.g.
https://bugs.freedesktop.org/show_bug.cgi?id=80827#c1

i965: expose AMD_vertex_shader_viewport_index on gen7+

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>

glsl: add support for AMD_vertex_shader_viewport_index

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Tested-by: Tobias Droste <tdroste@gmx.de>

mesa: add support for AMD_vertex_shader_viewport_index

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Tested-by: Tobias Droste <tdroste@gmx.de>

mesa/st: enable ARB_fragment_layer_viewport

If multiple viewports are supported, that implies the presence of a GS
and layered rendering, so we can enable ARB_fragment_layer_viewport as
well.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

i965/gen6: Add a spec citation about push constant packet requirements.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Add a comment about null renderbuffer surfaces and why they exist.

I noticed this when trying to find comments about pull constant buffers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Update a ton of comments about constant buffers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Merge VS/GS and WM pull constant buffer upload paths.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/gen6+: Merge VS/GS and WM push constant buffer upload paths.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Move dispatch_grf_start_reg and first_curbe_grf into stage_prog_data.

I wanted to access this value from stage-generic code, so stop storing it
under two different names.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Fix state flags for gen4/5 CURBE.

If we had some NOS affecting VS compilation that resulted in optimization
changing the set of constants to be uploaded, we might not have reuploaded
the constants.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Remove a dead define.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Reuse libdrm's header for AUB definitions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>