bugzilla-daemon [Mon, 25 May 2020 23:41:36 +0000 (23:41 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Luke Kenneth Casson Leighton [Mon, 25 May 2020 23:40:10 +0000 (00:40 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
Cole Poirier [Mon, 25 May 2020 23:22:35 +0000 (16:22 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
bugzilla-daemon [Mon, 25 May 2020 23:06:24 +0000 (23:06 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 22:53:02 +0000 (22:53 +0000)]
[libre-riscv-dev] [Bug 337] Convention for register outputs in *OutputData structures is to use "Data"
Luke Kenneth Casson Leighton [Mon, 25 May 2020 22:45:39 +0000 (23:45 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
Cole Poirier [Mon, 25 May 2020 22:11:16 +0000 (15:11 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
bugzilla-daemon [Mon, 25 May 2020 21:36:58 +0000 (21:36 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
Luke Kenneth Casson Leighton [Mon, 25 May 2020 21:35:17 +0000 (22:35 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
Cole Poirier [Mon, 25 May 2020 21:06:47 +0000 (14:06 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
bugzilla-daemon [Mon, 25 May 2020 21:03:04 +0000 (21:03 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Mon, 25 May 2020 20:56:03 +0000 (20:56 +0000)]
[libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
Luke Kenneth Casson Leighton [Mon, 25 May 2020 19:40:43 +0000 (20:40 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
Jacob Lifshay [Mon, 25 May 2020 19:30:29 +0000 (12:30 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
bugzilla-daemon [Mon, 25 May 2020 19:09:44 +0000 (19:09 +0000)]
[libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
bugzilla-daemon [Mon, 25 May 2020 19:00:32 +0000 (19:00 +0000)]
[libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
Luke Kenneth Casson Leighton [Mon, 25 May 2020 18:47:16 +0000 (19:47 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
Luke Kenneth Casson Leighton [Mon, 25 May 2020 18:29:56 +0000 (19:29 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
Cesar Strauss [Mon, 25 May 2020 17:41:57 +0000 (14:41 -0300)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
Michael Nolan [Mon, 25 May 2020 16:39:22 +0000 (12:39 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
bugzilla-daemon [Mon, 25 May 2020 15:32:01 +0000 (15:32 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 15:25:43 +0000 (15:25 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 15:14:34 +0000 (15:14 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Luke Kenneth Casson Leighton [Mon, 25 May 2020 14:27:56 +0000 (15:27 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
bugzilla-daemon [Mon, 25 May 2020 14:23:26 +0000 (14:23 +0000)]
[libre-riscv-dev] [Bug 352] New: virtual (dependency-tracked) regfile needed
Tobias Platen [Mon, 25 May 2020 14:20:57 +0000 (16:20 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
bugzilla-daemon [Mon, 25 May 2020 14:07:14 +0000 (14:07 +0000)]
[libre-riscv-dev] [Bug 351] New: create a "block" (mass) regfile port (read and write) onto an array-based regfile
bugzilla-daemon [Mon, 25 May 2020 13:55:49 +0000 (13:55 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Luke Kenneth Casson Leighton [Mon, 25 May 2020 12:30:19 +0000 (13:30 +0100)]
[libre-riscv-dev] daily kan-ban update 25may2020
bugzilla-daemon [Mon, 25 May 2020 11:57:49 +0000 (11:57 +0000)]
[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA
bugzilla-daemon [Mon, 25 May 2020 11:46:13 +0000 (11:46 +0000)]
[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA
bugzilla-daemon [Mon, 25 May 2020 10:43:52 +0000 (10:43 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 10:36:10 +0000 (10:36 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Mon, 25 May 2020 09:42:25 +0000 (09:42 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 07:28:45 +0000 (07:28 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 04:05:03 +0000 (04:05 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 04:03:04 +0000 (04:03 +0000)]
[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA
bugzilla-daemon [Mon, 25 May 2020 02:41:26 +0000 (02:41 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Mon, 25 May 2020 02:29:11 +0000 (02:29 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 02:21:01 +0000 (02:21 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 01:31:48 +0000 (01:31 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 01:27:14 +0000 (01:27 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 01:19:55 +0000 (01:19 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 00:56:02 +0000 (00:56 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 00:42:30 +0000 (00:42 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Mon, 25 May 2020 00:22:11 +0000 (00:22 +0000)]
[libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline
bugzilla-daemon [Mon, 25 May 2020 00:14:31 +0000 (00:14 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 00:14:31 +0000 (00:14 +0000)]
[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA
bugzilla-daemon [Mon, 25 May 2020 00:14:04 +0000 (00:14 +0000)]
[libre-riscv-dev] [Bug 318] fix LDSTCompUnit
bugzilla-daemon [Mon, 25 May 2020 00:14:04 +0000 (00:14 +0000)]
[libre-riscv-dev] [Bug 350] LDSTCompUnit also needs to support zeroing on RA
bugzilla-daemon [Mon, 25 May 2020 00:13:41 +0000 (00:13 +0000)]
[libre-riscv-dev] [Bug 350] New: LDSTCompUnit also needs to support zeroing on RA
bugzilla-daemon [Sun, 24 May 2020 21:51:56 +0000 (21:51 +0000)]
[libre-riscv-dev] [Bug 349] privileged-instruction decoding function needed
bugzilla-daemon [Sun, 24 May 2020 21:51:22 +0000 (21:51 +0000)]
[libre-riscv-dev] [Bug 349] New: privileged-instruction decoding function needed
bugzilla-daemon [Sun, 24 May 2020 21:49:44 +0000 (21:49 +0000)]
[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed
bugzilla-daemon [Sun, 24 May 2020 21:46:58 +0000 (21:46 +0000)]
[libre-riscv-dev] [Bug 348] New: POWER9 SPR pipeline needed
bugzilla-daemon [Sun, 24 May 2020 20:48:11 +0000 (20:48 +0000)]
[libre-riscv-dev] [Bug 333] investigate why CR pipeline code took 100% CPU and locked up generating ILANG
bugzilla-daemon [Sun, 24 May 2020 20:48:11 +0000 (20:48 +0000)]
[libre-riscv-dev] [Bug 345] define POWER9 regfiles
bugzilla-daemon [Sun, 24 May 2020 20:47:22 +0000 (20:47 +0000)]
[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline
bugzilla-daemon [Sun, 24 May 2020 20:41:42 +0000 (20:41 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 20:40:42 +0000 (20:40 +0000)]
[libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
bugzilla-daemon [Sun, 24 May 2020 20:29:54 +0000 (20:29 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 20:29:06 +0000 (20:29 +0000)]
[libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
bugzilla-daemon [Sun, 24 May 2020 19:57:47 +0000 (19:57 +0000)]
[libre-riscv-dev] [Bug 347] add setb (to CR pipeline?)
bugzilla-daemon [Sun, 24 May 2020 20:01:47 +0000 (20:01 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 19:57:47 +0000 (19:57 +0000)]
[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline
bugzilla-daemon [Sun, 24 May 2020 19:57:09 +0000 (19:57 +0000)]
[libre-riscv-dev] [Bug 347] New: add setb (to CR pipeline?)
bugzilla-daemon [Sun, 24 May 2020 19:39:25 +0000 (19:39 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Luke Kenneth Casson Leighton [Sun, 24 May 2020 19:30:33 +0000 (20:30 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 24may2020
bugzilla-daemon [Sun, 24 May 2020 19:29:45 +0000 (19:29 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Sun, 24 May 2020 19:25:15 +0000 (19:25 +0000)]
[libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline
Tobias Platen [Sun, 24 May 2020 19:23:09 +0000 (21:23 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 24may2020
bugzilla-daemon [Sun, 24 May 2020 19:20:03 +0000 (19:20 +0000)]
[libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline
bugzilla-daemon [Sun, 24 May 2020 18:33:28 +0000 (18:33 +0000)]
[libre-riscv-dev] [Bug 335] Formal Correctness Proof for Branch pipeline
bugzilla-daemon [Sun, 24 May 2020 18:26:59 +0000 (18:26 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Sun, 24 May 2020 18:25:00 +0000 (18:25 +0000)]
[libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
bugzilla-daemon [Sun, 24 May 2020 18:24:28 +0000 (18:24 +0000)]
[libre-riscv-dev] [Bug 197] Formal correctness proof needed of the 6600-style Out-of-Order execution engine
bugzilla-daemon [Sun, 24 May 2020 18:21:43 +0000 (18:21 +0000)]
[libre-riscv-dev] [Bug 331] Formal Correctness Proof for LOGICAL pipeline
bugzilla-daemon [Sun, 24 May 2020 18:16:39 +0000 (18:16 +0000)]
[libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
bugzilla-daemon [Sun, 24 May 2020 18:13:01 +0000 (18:13 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Sun, 24 May 2020 17:57:50 +0000 (17:57 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Sun, 24 May 2020 16:45:13 +0000 (16:45 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
bugzilla-daemon [Sun, 24 May 2020 15:33:16 +0000 (15:33 +0000)]
[libre-riscv-dev] [Bug 346] New: simplified test link between compunits and regfile
Luke Kenneth Casson Leighton [Sun, 24 May 2020 15:30:16 +0000 (16:30 +0100)]
[libre-riscv-dev] idea for testing pipelines
bugzilla-daemon [Sun, 24 May 2020 15:07:49 +0000 (15:07 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 14:55:52 +0000 (14:55 +0000)]
[libre-riscv-dev] [Bug 345] New: define POWER9 regfiles
bugzilla-daemon [Sun, 24 May 2020 14:44:32 +0000 (14:44 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 14:37:24 +0000 (14:37 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 14:27:44 +0000 (14:27 +0000)]
[libre-riscv-dev] [Bug 344] New: missing mtmsr and mfsprd
Luke Kenneth Casson Leighton [Sun, 24 May 2020 14:17:00 +0000 (15:17 +0100)]
[libre-riscv-dev] daily kan-ban update 24may2020
bugzilla-daemon [Sun, 24 May 2020 14:00:28 +0000 (14:00 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 13:46:48 +0000 (13:46 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 13:11:48 +0000 (13:11 +0000)]
[libre-riscv-dev] [Bug 314] Create POWER9 Condition Register pipeline
bugzilla-daemon [Sun, 24 May 2020 12:11:31 +0000 (12:11 +0000)]
[libre-riscv-dev] [Bug 337] Convention for register outputs in *OutputData structures is to use "Data"
bugzilla-daemon [Sun, 24 May 2020 03:43:22 +0000 (03:43 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 24 May 2020 03:41:42 +0000 (03:41 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Sun, 24 May 2020 03:33:37 +0000 (03:33 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Sun, 24 May 2020 03:33:37 +0000 (03:33 +0000)]
[libre-riscv-dev] [Bug 343] compalu_multi write requests need to hook into Data.ok
bugzilla-daemon [Sun, 24 May 2020 03:33:20 +0000 (03:33 +0000)]
[libre-riscv-dev] [Bug 343] New: compalu_multi write requests need to hook into Data.ok
bugzilla-daemon [Sun, 24 May 2020 01:46:13 +0000 (01:46 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Luke Kenneth Casson Leighton [Sun, 24 May 2020 01:01:28 +0000 (02:01 +0100)]
[libre-riscv-dev] Fwd: [OpenPOWER-HDL-Cores] POWER9 ISA opcode usage statistics
projects / libre-riscv-dev.git / log