anv: Split anv_extensions.py into two files

The new anv_extensions_gen.py is the code generator while the old
anv_extensions.py file is purely declarative.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

anv/meson: Make anv_entrypoints_gen.py depend on anv_extensions.py

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

ac: fix image load store for GLSL_SAMPLER_DIM_3D

Fixes the following piglit tests:

arb_shader_image_load_store/layer/image3d/layered binding test
arb_shader_image_load_store/max-size/image3d max size test/2048x8x8x1
arb_shader_image_load_store/max-size/image3d max size test/8x2048x8x1
arb_shader_image_load_store/max-size/image3d max size test/8x8x2048x1
arb_shader_image_load_store/semantics/imageload/vertex shader/rgba32f/image3d test

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: image size builtin for GLSL_SAMPLER_DIM_3D

This is what radeonsi does. Fixes remaing piglit subtest in:

./bin/arb_shader_image_size-builtin --quick -auto -fbo

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

swr: refactor swr_create_screen to allow for proper cleanup on error

This makes the following changes to address cleanup issues:
- Error conditions now return NULL instead of calling exit()
- swr_creen is now freed upon error, rather than leak.
- Library handle from dlopen is now closed upon swr_screen destruction

v2: Added additional context in commit msg and remove unnecessary "PUBLIC"
v3: Fix typo in commit message.

Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Cc: Bruce Cherniak <bruce.cherniak@intel.com>
Cc: Tim Rowley <timothy.o.rowley@intel.com>
cc: mesa-stable@lists.freedesktop.org

intel: Add Geminilake brand strings

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>

ac: fix ac_build_varying_gather_values() for packed layouts

This fixes a segfault for varyings not starting at component 0.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: remove arrays when when querying sampler info

Fixes the following ARB_arrays_of_arrays piglit tests:

basic-imagestore-const-uniform-index
basic-imagestore-mixed-const-non-const-uniform-index
basic-imagestore-mixed-const-non-const-uniform-index2
basic-imagestore-non-const-uniform-index

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

glsl: add image and sampler (un)packing support to glsl to nir

This is needed for ARB_bindless_texture support.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

nir: add image and sampler type to glsl_get_bit_size()

These are needed for ARB_bindless_texture support.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: fix emit vertex stream parameter

Fixes the following piglit test on radeonsi:

./bin/arb_enhanced_layouts-gs-stream-location-aliasing

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: add support for gl_HelperInvocation

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/radeonsi: add emit primitive to the abi

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: add generic emit primitive helper

This will be shared by the tgsi and nir backends.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac: add stream handling to visit_end_primitive()

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/nir: fix fs output index

Fixes the following piglit tests:

arb_blend_func_extended-fbo-extended-blend
arb_blend_func_extended-fbo-extended-blend-explicit
arb_blend_func_extended-fbo-extended-blend-explicit_gles3
arb_blend_func_extended-fbo-extended-blend-pattern
arb_blend_func_extended-fbo-extended-blend-pattern_gles2
arb_blend_func_extended-fbo-extended-blend-pattern_gles3
arb_blend_func_extended-fbo-extended-blend_gles3
ext_framebuffer_multisample/alpha-to-coverage-dual-src-blend
ext_framebuffer_multisample/alpha-to-one-dual-src-blend

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/nir/radeonsi: add ARB_shader_ballot support

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

ac/nir: add ARB_shader_group_vote support

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/nir: add primitive id to inputs scan

Fixes the following piglit tests:

arb_tessellation_shader/fs-primitiveid-instanced
glsl-1.50/primitive-id-no-gs
glsl-1.50/primitive-id-no-gs-first-vertex
glsl-1.50/primitive-id-no-gs-instanced
glsl-1.50/primitive-id-no-gs-strip
glsl-1.50/primitive-id-no-gs-strip-first-vertex

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/nir: add nir_intrinsic_load_sample_mask_in to ir scan

Fixes a bunch of ARB_sample_shading piglit tests.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

u_thread: Use pthread_setname_np on linux only.

pthread_setname_np was added in glibc 2.12 for the Linux port only, other
ports do not necessarily have it.

Signed-off-by: Jose Fonseca <jfonseca@vmware.com>

svga: Prevent use after free.

Courtesy of clang static analyzer.

I was hunting for potential sources of memory corruption using Mesa with
a GL trace, and happened to find this (unrelated) issue.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

i965: Drop render_target_start from binding table struct.

We have to start render targets at binding table index 0 in order to use
headerless FB write messages, and in fact already assume this in a bunch
of places in the code.  Let's finish that off, and not bother storing 0
in a struct to pretend to add it in a few places.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

i965: make brw_context::num_samples unsigned int

It is never a negative number. Variable is compared against unsigned
values and passed into functions that expect unsigned int.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

st/mesa: provide static inline st_init_vdpau_functions

The ifdef spaghetty in st_vdpau.c is rather confusing and misleading.
Simplily it by introducing a static inline helper noop (when
HAVE_ST_VDPAU is not defined) in the header.

Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Acked-by: Christian König <christian.koenig@amd.com>

radv: add an option that allows to dump pre-optimization ir

With RADV_DEBUG=preoptir.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

i965: Accept CONTEXT_ATTRIB_PRIORITY for brwCreateContext

The forward port of commit 6d87500fe12e ("dri: Change
__DriverApiRec::CreateContext to take a struct for attribs") failed to
adapt the set of allowed attributes for the earlier introduction of
context priorities (commit 1617fca6d12e "i965: Pass the EGL/DRI context
priority through to the kernel").

Fixes: 6d87500fe12e ("dri: Change __DriverApiRec::CreateContext to take a struct for attribs")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Adam Jackson <ajax@redhat.com>
Cc: Nicolai Hähnle <nicolai.haehnle@amd.com>
Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org

radv: restore previous stencil reference after depth-stencil clear

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Alex Smith <asmith@feralinteractive.com>

i965: Set tiling on BOs imported with modifiers

We need this to ensure that GTT maps work on buffers we get from Vulkan
on the off chance that someone does a readpixels or something.  Soon, we
will be removing GTT maps from i965 entirely and this can be reverted.
None the less, it's needed for stable.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org

i965/bufmgr: Add a create_from_prime_tiled function

This new function is an import and a set tiling in one go.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org

i965/miptree: Use the tiling from the modifier instead of the BO

This fixes a bug where we were taking the tiling from the BO regardless
of what the modifier said.  When we got images in from Vulkan where it
doesn't set the tiling on the BO, we would treat them as linear even
though the modifier expressly said to treat it as Y-tiled.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org

i965/miptree: Add an explicit tiling parameter to create_for_bo

Otherwise, create_for_bo will just grab the tiling from the BO which is
not what we want when using modifiers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org

radv: Don't allow 3d or 1d depth/stencil textures.

addrlib asserts when that happens, and supporting it is not
required so lets not allow this for now.

It also assert on fmask, but we don't have the number of samples here.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Init variant entry with memset.

This gets memcpy'd and written driectly, and due to alignment, this
resulted in uninitialized gaps. This makes those gaps go away.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Fix bufimage failure deallocation.

The inidividual init parts don't clean up their own stuff on failure.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Fix fragment resolve init memory allocation failure paths.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Fix freeing meta state if the device pipeline cache fails to allocate.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Fix memory allocation failure path in compute resolve init.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Fix ordering issue in meta memory allocation failure path.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airlied@redhat.com>

etnaviv: dirty TS state when framebuffer has changed

When switching between framebuffers with and without TS, the TS state
needs to be flushed to the command stream even if the derived state
isn't changed.

Fixes: 4ee7c2c2843c ("etnaviv: enable TS, but disable autodisable")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>

broadcom/vc5: Fix source file name.

Fixes: c9b2cb78972d ("vc5: add missing files to the tarball")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

broadcom/vc5: Add missing include paths.

Fixes: 954a704da305 ("broadcom/vc5: Port the RCL setup to V3D4.1.")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: Only require independent blending for GLES 3.2.

We've been requiring this since GLES 3.0 was introduced, but the GLES 3.2
spec is the one that has "Supporting blending on a per-draw-buffer basis"
in the new features.  V3D 3.3 would require lowering blending to shader
code to implement independent blending.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

i965: Delete completely bogus comment

This hasn't been true in 6+ years, if it was even true then.  Before
we rewrote the compiler and introduced GLSL IR in 2010-2011, i965 used
to have two compiler backends for WM programs, based on Mesa IR.  One
handled flow control and was SIMD8-only, while the other was SIMD16
only and didn't handle flow control.  Or something like that.

Even then, this certainly didn't handle vertex shaders, so "all ...
code generation" is a bit strong.

autotools: include meson build files in tarball

This adds the meson.build, meson_options.txt, and a few scripts that are
used exclusively by the meson build.

v2: - Remove accidentally included changes needed to test make dist with
      LLVM > 3.9

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

swr/rast: Fix llvm5 behavior

For some reason llvm5 is picky about accepting a void * type in the
case of building an argument list.

Since we don't care about the type (we ignore the argument for now),
pick another pointer type

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Enable early rasterization

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Implement Early Rasterization optimization

Early Rasterization is an optimization for small triangles.

Scientific workloads often contain very small triangles that has non-zero
area and cannot be trivially rejected as falling between pixel centers,
but does not cover any pixel center. Those triangles can be initially
rasterized as early as in binner and rejected if they cover no pixels The
optimization can be disabled in compilation using KNOB_ENABLE_EARLY_RAST
option in knobs.h

The Early Rast is disabled by default.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Enable simd16 vertex shaders

Flip the switch(es) to enable simd16 vertex shaders:

USE_SIMD16_SHADERS and USE_SIMD16_VS

Both have to be enabled at the same time.  Currently, just setting
USE_SIMD16_SHADERS does not work correctly.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: Support simd16 vertex shaders

Supporting simd16 vertex shaders involves packing the output of the
fetch shader appropriately, especially the vertexID buffers that have to
be formatted in one simd16 register, needed by the VS.

As part of this support, we needed to remove the 2nd JitManager, since it
was not accounting for vector width correctly.

USE_SIMD16_SHADERS is also split into two defines.  The additional
one (USE_SIMD16_VS) controls the width of the vertex shader (VS), while
the original one (USE_SIMD16_SHADERS) controls overall front end width.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: changed jit debug magic number

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Added ICLAMP builder function

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Jit debug work

Properly validate DLL matches OBJ for jitted function

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: silence generated file warnings

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: jit shader lib debug work

Create shader_lib during build, link with shaders at DLL generation time

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: AVX-512 changes to enable 16-wide VS

Add a new define (USE_SIMD16_VS), to denote calling a 16-wide vertex shader.
This is needed because the mesa driver can do 16-wide shaders, but rasty
cannot yet, so we need to distinguish.

Create a new VertexID entry (VertexID16) for the USE_SIMD16_VS case, since
we need to format the vertex id in a way that is digestible by the 16-wide VS

Disabled for now.  To be enabled in a future checkin when driver work
is complete.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: x86 autogenerated macro work

Add name argument to x86 autogenerated macros.
Add useful variable names for DCL_inputVec implementation.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Shorten some filenames

in shader and fetch dump files

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: work supporting optimizations in Debug builds.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Add debugging type support for function types.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Shader debugging work

- Move debug .ll files to JIT_CACHE_DIR
- Don't link against jitter SRGBLut table, add global data to shader that needs it.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Debug Symbols work

Added support for Fetch / Sample / LD functions
Added DLL link to JitCache implementation

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Initial work for debugging support.

Adds ability to step into jitted llvm IR in Visual Studio.
- Updated llvm type generation script to also generate corresponding debug types.
- New module pass inserts debug metadata into the IR for each function

Disabled by default.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Add private state parameter in fetcher

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Added missing define for Linux/gcc

+ ZeroMemory() macro definition for non win32-compilation in common/os.h

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Fix one more invalid object format for windows.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

radv: Always re-emit the sample position offset user SGPR.

The user SGPR location can change between pipelines, so we need to
emit it again to the pottentially changed SGPR index.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: emit pa_sc_mode_cntl_0 with multisample state.

We don't have the meta kludge with 0 viewports anymore,
so we can always enable them.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

i965: Avoid problems from referencing orphaned BOs after growing.

Growing the batch/state buffer is a lot more dangerous than I thought.

A number of places emit multiple state buffer sections, and then write
data to the returned pointer, or save a pointer to brw->batch.state.bo
and then use it in relocations.  If each call can grow, this can result
in stale map references or stale BO pointers.  Furthermore, fences refer
to the old batch BO, and that reference needs to continue working.

To avoid these woes, we avoid ever swapping the brw->batch.*.bo pointer,
instead exchanging the brw_bo structures in place.  That way, stale BO
references are fine - the GEM handle changes, but the brw_bo pointer
doesn't.  We also defer the memcpy until a quiescent point, so callers
can write to the returned pointer - which may be in either BO - and
we'll sort it out and combine the two properly in the end.

v2/v3:
- Handle stale pointers in the shadow copy case, where realloc may or
  may not move our shadow copy to a new address.
- Track the partial map explicitly, to avoid problems with buffer reuse
  where multiple map modes exist (caught by Chris Wilson).

v4:
- Don't use realloc in the CPU shadow case, it isn't safe.

Fixes: 2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> [v3]
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

i965: Rename 'aux' to 'prog_data' in program cache.

'aux' is a very generic name, suggesting it can be a bunch of things.
However, it's always the brw_*_prog_data structure.  So, call it that.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

swr: allow a single swr architecture to be builtin

Part 2 of 2 (part 1 is autoconf changes, part 2 is C++ changes)

When only a single SWR architecture is being used, this allows that
architecture to be builtin rather than as a separate libswrARCH.so that
gets loaded via dlopen.  Since there are now several different code
paths for each detected CPU architecture, the log output is also
adjusted to convey where the backend is getting loaded from.

This allows SWR to be used for static mesa builds which are still
important for large HPC environments where shared libraries can impose
unacceptable application startup times as hundreds of thousands of copies
of the libs are loaded from a shared parallel filesystem.

Based on an initial implementation by Tim Rowley.

v2: Refactor repetitive preprocessor checks to reduce code duplication
v3: Formatting changes per Bruce C. Also delay screen creation until end
    to avoid leaks when failure conditions are hit.

Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
CC: Tim Rowley <timothy.o.rowley@intel.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: (autoconf) allow a single swr architecture to be builtin

Part 1 of 2 (part 1 is autoconf changes, part 2 is C++ changes)

When only a single SWR architecture is being used, this allows that
architecture to be builtin rather than as a separate libswrARCH.so that
gets loaded via dlopen.  Since there are now several different code
paths for each detected CPU architecture, the log output is also
adjusted to convey where the backend is getting loaded from.

This allows SWR to be used for static mesa builds which are still
important for large HPC environments where shared libraries can impose
unacceptable application startup times as hundreds of thousands of copies
of the libs are loaded from a shared parallel filesystem.

Based on an initial implementation by Tim Rowley.

v2: Fix comment placement pointed out by Bruce C.

Signed-off-by: Chuck Atkins <chuck.atkins@kitware.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
CC: Tim Rowley <timothy.o.rowley@intel.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr: fix clang 5 null cast warning

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

mesa/program: Fix -Wunused-param warning

v2: Don't annotate, but remove the unused ctx parameter

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa/program/prog_execute.c: Silence -Wunused-param

v2: Don't annotate, but remove the unused ctx parameter

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

mesa: Make numSamples an unsigned int

As a followup to the previous patch propagate the change of numSamples
from int to unsigned to gl_config::samples and consequently fix some
-Wsign-compare warnings.

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

gallium: Make (num_)samples an unsigned int

According to the ARB_multisample num_samples is a non-negative integer.
Consequently define it as such, fail in glx/choose_visual if a negative
number is given.

v2: split patch into gallium and mesa part

Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

docs: correct a typo in releasing instructions

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

docs: move untar line in basic testing instructions for coherence

For scons, windows/mingw dealing with LLVM_CONFIG is done before
untarring. This is also more convenient for copy and paste.

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

docs: add a notice whenever a release is the final in a series

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

docs: add final release note for 17.2.8

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

docs: add final release note for 17.1.10

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

st/vdpau: release held lock in error path

Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: mesa-stable@lists.freedesktop.org

docs: update calendar, add news and link release notes to 17.3.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

docs: add sha256 checksums for 17.3.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit bc1503b13fcf8190262757ea7f86613e14e25981)

docs: add release notes for 17.3.3

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit 80f5f279b3f9fc752ba35b1cb2878a936f8ace90)

anv: avoid segmentation fault due to vk_error()

vk_error() is a macro that calls __vk_errorf() with instance == NULL.

Then, __vk_errorf() passes a pointer to instance->debug_report_callbacks
to vk_debug_error(), which segfaults as this pointer is invalid but not
NULL.

Fixes: e5b1bd6ab8 "vulkan: move anv VK_EXT_debug_report implementation to common code."
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

ac/nir: Fix vector extraction if source vector has >4 elements.

v2: Add forgotten argument and start offset.

Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>

ac/nir: Use correct 32-bit component writemask for 64-bit SSBO stores.

Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri <tarceri@itsqueeze.com>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>

ac/nir: Fix TCS output LDS offsets.

When a channel was not set we also did not increase the LDS address,
while that obviously should happen.

The output loading code was inadvertently fixed which resulted in a
mismatch causing the SaschaWillems tessellation demo to result
in corrupt rendering.

Fixes: 7898eb9a60 "ac: rework load_tcs_{inputs,outputs}"
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Use correct bindings for inputRate in key generation.

The bindings also have an index field.

Fixes: 49d035122e "radv: Add single pipeline cache key."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104677
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Implement VK_ANDROID_native_buffer.

Passes
  dEQP-VK.api.smoke.*
  dEQP-VK.wsi.android.*

with android-cts-7.1_r12 .

Unlike the initial anv implementation this does
use syncobjs instead of waiting on the CPU.

This is missing meson build coverage for now.

One possible todo is that linux 4.15 now has a
sycall that allows us to export amdgpu fence to
a sync_file, which allows us not to force all
fences and semaphores to use syncobjs. However,
I had trouble with my kernel crashing regularly
with NULL pointers, and I'm not sure how beneficial
it is in the first place given that intel uses
syncobjs for all fences if available.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Add create image flag to not use DCC/CMASK.

If we import an image, we might not have space in the
buffer for CMASK, even though it is compatible.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Generate VK_ANDROID_native_buffer.

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: Replace an assert with unreachable.

Otherwise we get uninitialized variable warnings for es_vgpr_comp_cnt.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

radv: Remove DCC check on CS resolve dst image.

Gives a warning when the assert is disabled, and not even
necessarily true.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

gallivm: support avx512 (16x32) in interleave2_half

lp_build_interleave2_half was not doing the right thing for avx512-style
16-wide loads.

This path is hit in the swr driver with a 16-wide vertex shader. It is
called from lp_build_transpose_aos, when doing texel fetches and the
fetched data needs to be transposed to one component per output register.

Special-case the post-load swizzle operations for avx512 16x32 (16-wide
32-bit values) so that we move the xyzw components correctly to the outputs.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

vbo: fix VBO optimization regression

The optimization in change 8e4efdc895ea ("vbo: optimize some display
list drawing") missed the loopback case.  This is used when the
glBegin/End primitive doesn't have a uniform set of vertex attributes.
The new Piglit gl-1.0-dlist-materials test hits this.

So check the aligned_vertex_buffer_offset(list) value and adjust the
buffer offset accordingly.

We also need to remove the 'start == 0' assertion in the loopback
code since it no longer applies.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>

meson: ensure that xmlpool_options.h is generated for targets that need it

Currently a couple of gallium targets race with xmlpool_options.h being
generated, don't do that.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

ac: fix visit_ssa_undef() for doubles

V2: use LLVMIntTypeInContext()

Fixes: f4e499ec7914 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>