synth_xilinx to use shregmap with -minlen 3

Merge remote-tracking branch 'origin/master' into xc7srl

Add "cutpoint" pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #896 from YosysHQ/transp_fixes

memory_bram: Fix multiclock make_transp

Merge pull request #897 from trcwm/libertyfixes

Liberty parser: Accept ranges [A:B], and ignore missing ';'.

spaces -> tabs

EOL is now accepted as ';' replacement on lines that look like: feature_xyz(option)

Updated the liberty parser to accept [A:B] ranges (AST has not been updated). Liberty parser now also accepts key : value pair lines that do not end in ';'.

memory_bram: Fix multiclock make_transp

Signed-off-by: David Shah <dave@ds0.me>

Cope with SHREG not having E port; Revert $pmux fine tune

Add "mutate -none -mode", "mutate -mode none"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "mutate -s <filename>"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #893 from YosysHQ/clifford/btormeminit

Memory init support in write_btor

Add support for memory initialization to write_btor

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix BTOR output tags syntax in writye_btor

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add support for SHREGMAP+$mux, also fine tune $pmux

Leftover printf

Fixes for multibit

Working for 1 bit

Merge remote-tracking branch 'origin/master' into xc7srl

Merge pull request #889 from YosysHQ/clifford/fix888

Fix mem2reg handling of memories with upto data ports

Merge pull request #890 from YosysHQ/clifford/fix887

Trim init attributes when resizing FFs in "wreduce"

Merge pull request #891 from YosysHQ/xilinx_keep

xilinx: Add keep attribute where appropriate

xilinx: Add keep attribute where appropriate

Signed-off-by: David Shah <dave@ds0.me>

Trim init attributes when resizing FFs in "wreduce", fixes #887

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add '-nosrl' option to synth_xilinx

Fix mem2reg handling of memories with upto data ports, fixes #888

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve "read_verilog -dump_vlog[12]" handling of upto ranges

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve read_verilog debug output capabilities

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Opt

Fix spacing

Fine tune cells_map.v

Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length

Add support for variable length Xilinx SRL > 128

Restore original synth_xilinx commands

Fix spacing

shregmap -tech xilinx to delete $shiftx for var length SRL

Fix INIT for variable length SRs that have been bumped up one

Merge remote-tracking branch 'origin/master' into xc7srl

Make output port a non chain user

Merge pull request #885 from YosysHQ/clifford/fix873

Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873

Add Xilinx negedge FFs to synth_xilinx dffinit call, fixes #873

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #808 from eddiehung/read_aiger

Add new read_aiger frontend

Merge https://github.com/YosysHQ/yosys into read_aiger

Add author name

Merge pull request #884 from zachjs/master

fix local name resolution in prefix constructs

fix local name resolution in prefix constructs

Fix shregmap to correctly recognise non chain users; cleanup

shiftx NULL pointer check

Update issue template

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update issue template

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Cleanup

Only accept <128 for variable length, only if $shiftx exclusive

Merge pull request #877 from FelixVi/master

Add note about test requirements in README

Add note about test requirements in README

Cleanup synth_xilinx

Working

Improve mix of src/wire/wirebit coverage in "mutate -list"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #876 from YosysHQ/clifford/fmcombine

Add fmcombine pass

Add "fmcombine -fwd -bwd -nop"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add fmcombine pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #875 from YosysHQ/clifford/mutate

Add "mutate" pass

Disable realmath tests

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improvements in "mutate" list-reduce algorithm

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "mutate -cfg", improve pick_cover behavior

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add a strictly coverage-driven mutation selection strategy

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve "mutate" wire coverage metric

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add more mutation types, improve mutation src cover

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix smtbmc.py handling of zero appended steps

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "mutate" command DB reduce functionality

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add hashlib "<container>::element(int n)" methods

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "mutate -mode inv", various other mutate improvements

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add basic "mutate -list N" framework

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #874 from YosysHQ/clifford/andopt

Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327

Improve handling of and-with-1 and or-with-0 in opt_expr, fixes #327

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #872 from YosysHQ/clifford/pmuxfix

Improve handling of "full_case" attributes

Improve handling of "full_case" attributes

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix a syntax bug in ilang backend related to process case statements

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Reverse bits in INIT parameter for Xilinx, since MSB is shifted first

Misspell

Revert "Add shregmap -init_msb_first and use in synth_xilinx"

This reverts commit 26ecbc1aee1dca1c186ab2b51835d74f67bc3e75.

Merge remote-tracking branch 'origin/master' into xc7srl

Merge pull request #869 from cr1901/win-shell

Install launcher executable when running yosys-smtbmc on Windows.

Add shregmap -init_msb_first and use in synth_xilinx

Fix cells_map for SRL

Move shregmap until after first techmap

Refactor $__SHREG__ in cells_map.v

Install launcher executable when running yosys-smtbmc on Windows.

Signed-off-by: William D. Jones <thor0505@comcast.net>

Merge pull request #868 from YosysHQ/clifford/fixmem

Various mem2reg-related improvements in handling of memories

Fix a bug in handling quotes in multi-cmd lines in Yosys scripts

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #866 from YosysHQ/clifford/idstuff

Improve determinism of IdString DB for similar scripts

Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve handling of memories used in mem index expressions on LHS of an assignment

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Remove outdated "blocking assignment to memory" warning

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve determinism of IdString DB for similar scripts

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #864 from YosysHQ/svalabelfix

Fix handling of cases that look like sva labels, fixes #862

Add ENABLE_GLOB Makefile switch

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix handling of cases that look like sva labels, fixes #862

Signed-off-by: Clifford Wolf <clifford@clifford.at>