whitequark [Fri, 11 Oct 2019 11:37:26 +0000 (11:37 +0000)]
hdl.ast: Operator.{op→operator}
Both "operator" and "operand" were shortened to "op" in different
places in code, which caused confusion.
whitequark [Fri, 11 Oct 2019 11:16:00 +0000 (11:16 +0000)]
hdl.ast: simplify enum handling.
whitequark [Fri, 11 Oct 2019 10:49:34 +0000 (10:49 +0000)]
hdl.ast: Value.{wrap→cast}
Preparation for #225.
whitequark [Thu, 10 Oct 2019 16:35:48 +0000 (16:35 +0000)]
vendor.xilinx_ultrascale: new supported family.
whitequark [Thu, 10 Oct 2019 16:25:10 +0000 (16:25 +0000)]
xilinx_7series: add grade platform property.
For some devices grade has to be omitted, so it is optional.
whitequark [Thu, 10 Oct 2019 15:33:01 +0000 (15:33 +0000)]
vendor.lattice_machxo2: new supported family.
whitequark [Thu, 10 Oct 2019 14:38:09 +0000 (14:38 +0000)]
vendor: yosys is a required tool for all Verilog-based flows.
whitequark [Thu, 10 Oct 2019 00:50:01 +0000 (00:50 +0000)]
README: add device support matrix.
whitequark [Wed, 21 Aug 2019 22:14:33 +0000 (22:14 +0000)]
vendor.intel: add Quartus support.
Co-authored-by: Dan Ravensloft <dan.ravensloft@gmail.com>
whitequark [Wed, 9 Oct 2019 23:19:19 +0000 (23:19 +0000)]
examples: update blinky, add some explanatory text about domains.
whitequark [Wed, 9 Oct 2019 21:16:14 +0000 (21:16 +0000)]
build.plat: elaborate result of create_missing_domain() against platform.
Before this commit, the result was elaborated without platform, which
caused generic implementation of e.g. ResetSynchronizer to be used.
whitequark [Wed, 9 Oct 2019 20:44:07 +0000 (20:44 +0000)]
build.plat: don't create default sync domain as reset-less.
whitequark [Wed, 9 Oct 2019 20:02:33 +0000 (20:02 +0000)]
build.plat,vendor: always synchronize reset in default sync domain.
This change achieves two related goals.
First, default_rst is no longer assumed to be synchronous to
default_clk, which is the safer option, since it can be connected to
e.g. buttons on some evaluation boards.
Second, since the power-on / configuration reset is inherently
asynchronous to any user clock, the default create_missing_domain()
behavior is to use a reset synchronizer with `0` as input. Since,
like all reset synchronizers, it uses Signal(reset=1) for its
synchronization stages, after power-on reset it keeps its subordinate
clock domain in reset, and releases it after fabric flops start
toggling.
The latter change is helpful to architectures that lack an end-of-
configuration signal, i.e. most of them. ECP5 was already using
a similar scheme (and is not changed here). Xilinx devices with EOS
use EOS to drive a BUFGMUX, which is more efficient than using
a global reset when the design does not need one; Xilinx devices
without EOS use the new scheme. iCE40 requires a post-configuration
timer because of BRAM silicon bug, and was changed to add a reset
synchronizer if user clock is provided.
whitequark [Sun, 6 Oct 2019 08:52:49 +0000 (08:52 +0000)]
back.rtlil: don't crash legalizing values with no branches.
Fixes #239.
whitequark [Fri, 4 Oct 2019 07:56:06 +0000 (07:56 +0000)]
back.rtlil: avoid unsoundness for division by zero.
Fixes #238.
whitequark [Fri, 4 Oct 2019 07:49:24 +0000 (07:49 +0000)]
hdl.ast: prohibit signed divisors.
See #238.
whitequark [Thu, 3 Oct 2019 02:44:43 +0000 (02:44 +0000)]
build.dsl: accept Pins(invert=True).
The PinsN() form is still preferred, but Pins(invert=) form is useful
for code generic over pin polarity.
whitequark [Wed, 2 Oct 2019 08:24:37 +0000 (08:24 +0000)]
hdl.ast: don't crash on Mux(<bool>, ...).
Fixes #240.
whitequark [Wed, 2 Oct 2019 07:51:49 +0000 (07:51 +0000)]
back.rtlil: don't cache wires for legalized switch tests.
This causes miscompilation of code such as:
r = Array([self.a, self.b])
m = Module()
with m.If(r[self.s]):
m.d.comb += self.o.eq(1)
return m
whitequark [Wed, 2 Oct 2019 03:50:20 +0000 (03:50 +0000)]
back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow} don't need to match.
whitequark [Wed, 2 Oct 2019 03:38:58 +0000 (03:38 +0000)]
back.rtlil: it is not necessary to match binop operand width.
Jean-François Nguyen [Sun, 29 Sep 2019 22:12:17 +0000 (00:12 +0200)]
rpc: add public Records as module ports.
whitequark [Fri, 27 Sep 2019 02:35:45 +0000 (02:35 +0000)]
rpc: add support for Yosys RPC protocol.
whitequark [Sat, 28 Sep 2019 19:33:24 +0000 (19:33 +0000)]
hdl.ast: actually implement the // operator.
whitequark [Sat, 28 Sep 2019 17:50:24 +0000 (17:50 +0000)]
hdl.dsl: add a diagnostic for `m.d.submodules += ...`.
whitequark [Sat, 28 Sep 2019 01:29:56 +0000 (01:29 +0000)]
hdl.mem: remove WritePort(priority=) argument.
The write port priority in Yosys is derived directly from the order
in which the ports are declared in the Verilog frontend. It is being
removed for several reasons:
1. It is not clear if it works correctly for all cases (FFRAM,
LUTRAM, BRAM).
2. Although it is roundtripped via Verilog with correct simulation
semantics, the resulting code has a high chance of being
interpreted incorrectly by Xilinx tools.
3. It cannot be roundtripped via FIRRTL, which is an alternative
backend that is an interesting future option. (FIRRTL leaves
write collision completely undefined.)
3. It is a niche feature that, if it is needed, can be completely
replaced using an explicit comparator, priority encoder, and
write enable gating circuit. (This is what Xilinx recommends
for handling this case.)
In the future we should extend nMigen's formal verification to assert
that a write collision does not happen.
whitequark [Tue, 24 Sep 2019 18:32:26 +0000 (18:32 +0000)]
back.rtlil: fix handling of certain nested arrays.
This triggers on code like:
c1 = Signal()
c2 = Signal()
c3 = Signal()
v1 = Array([Const(1, 8), Const(2, 8)])[c1]
v2 = Array([Const(3, 8), Const(4, 8)])[c2]
v3 = Array([v1, v2])[c3]
Fixes #226.
whitequark [Tue, 24 Sep 2019 14:54:22 +0000 (14:54 +0000)]
build.plat: strip internal attributes from Verilog output.
Although useful for debugging, most external tools often complain
about such attributes (with notable exception of Vivado). As such,
it is better to emit Verilog with these attributes into a separate
file such as `design.debug.v` and only emit the attributes that were
explicitly placed by the user to `design.v`.
This still leaves the (*init*) attribute. See #220 for details.
whitequark [Tue, 24 Sep 2019 14:14:45 +0000 (14:14 +0000)]
build.plat,lib.cdc,vendor: unify platform related diagnostics. NFC.
whitequark [Tue, 24 Sep 2019 12:30:02 +0000 (12:30 +0000)]
lib.cdc: specify maximum input delay in seconds.
Since we use hertz elsewhere, this provides for easy conversions.
Also, cast the delay to string before applying it in xilinx_7series,
to avoid stripping the fractional digits.
Closes #234.
whitequark [Tue, 24 Sep 2019 12:22:29 +0000 (12:22 +0000)]
vendor.xilinx_spartan_3_6: explain why ASYNC_REG is used. NFC.
Kate Temkin [Tue, 24 Sep 2019 06:55:00 +0000 (00:55 -0600)]
vendor.lattice_ecp5: correct a typo in tristate buffer generation
Darrell Harmon [Tue, 24 Sep 2019 00:47:54 +0000 (18:47 -0600)]
vendor.xilinx_7series: apply false path / max delay constraints.
whitequark [Mon, 23 Sep 2019 20:27:42 +0000 (20:27 +0000)]
vendor.xilinx_7series: simplify. NFC.
whitequark [Mon, 23 Sep 2019 20:15:29 +0000 (20:15 +0000)]
vendor.xilinx_7series: override reset synchronizer.
whitequark [Mon, 23 Sep 2019 19:38:21 +0000 (19:38 +0000)]
lib.cdc: add diagnostic checks for synchronization stage count.
whitequark [Mon, 23 Sep 2019 19:31:23 +0000 (19:31 +0000)]
lib.cdc: expand ResetSynchronizer documentation.
Loosely based on work by @Wren6991.
whitequark [Mon, 23 Sep 2019 16:42:44 +0000 (16:42 +0000)]
lib.cdc: avoid modifying synchronizers in their elaborate() method.
Darrell Harmon [Mon, 23 Sep 2019 16:28:15 +0000 (10:28 -0600)]
vendor.xilinx_spartan_3_6: override reset synchronizer.
whitequark [Mon, 23 Sep 2019 16:01:59 +0000 (16:01 +0000)]
README: add a section on migrating from Migen.
whitequark [Mon, 23 Sep 2019 14:17:44 +0000 (14:17 +0000)]
lib.cdc: MultiReg→FFSynchronizer.
Fixes #229.
whitequark [Mon, 23 Sep 2019 13:39:31 +0000 (13:39 +0000)]
hdl.ast: cast Mux() selector to bool if it is not a 1-bit value.
Fixes #232.
whitequark [Mon, 23 Sep 2019 12:48:02 +0000 (12:48 +0000)]
back.rtlil: give predictable names to anonymous subfragments.
This is required for applying constraints to clocks in anonymous
subfragments in build.plat.
whitequark [Mon, 23 Sep 2019 12:27:59 +0000 (12:27 +0000)]
lib.fifo: handle depth=0, elaborating to a dummy FIFO with no logic.
whitequark [Mon, 23 Sep 2019 11:18:01 +0000 (11:18 +0000)]
hdl.mem,lib.fifo: use keyword-only arguments for memory geometry.
Fixes #230.
whitequark [Mon, 23 Sep 2019 11:16:29 +0000 (11:16 +0000)]
hdl.mem: simplify. NFC.
whitequark [Mon, 23 Sep 2019 11:08:43 +0000 (11:08 +0000)]
hdl.ast: make Signal(name=) a keyword-only argument.
Almost no code would specify Signal(_, name) as a positional argument
on purpose, but forgetting parens and accidentally placing signedness
into the name position is so common that we had a test for it.
whitequark [Mon, 23 Sep 2019 11:03:50 +0000 (11:03 +0000)]
lib.fifo: change FIFOInterface() diagnostics to follow Memory().
whitequark [Mon, 23 Sep 2019 10:57:30 +0000 (10:57 +0000)]
lib.fifo: round up AsyncFIFO{,Buffered} depth to lowest valid value.
Unless exact_depth=True is specified.
The logic introduced in this commit is idempotent: that is, if one
uses the depth of one AsyncFIFOBuffered in the constructor of another
AsyncFIFOBuffered, they will end up with the same depth. More naive
logic would result in an unbounded, quadratic growth with each such
step.
Fixes #219.
whitequark [Mon, 23 Sep 2019 08:45:58 +0000 (08:45 +0000)]
lib.fifo: make simulation read() and write() functions compat-only.
These functions were originally changed in
3ed51938, in an attempt
to make them take one cycle instead of two. However, this does not
actually work because of drawbacks of the simulator interface.
Avoid committing to any specific implementation for now, and instead
make them compat-only extensions.
whitequark [Sun, 22 Sep 2019 17:23:32 +0000 (17:23 +0000)]
hdl.rec: fix using Enum subclass as shape if direction is specified.
Also improves error messages.
Fixes #224.
whitequark [Sun, 22 Sep 2019 15:16:36 +0000 (15:16 +0000)]
hdl.rec: allow using Enum subclass as shape.
Fixes #223.
whitequark [Sun, 22 Sep 2019 11:56:03 +0000 (11:56 +0000)]
lib.fifo: add more compatibility shims.
Some downstream code was broken by renames in
da4b810f.
whitequark [Sun, 22 Sep 2019 07:18:37 +0000 (07:18 +0000)]
vendor.lattice_ice40: fix required tool list for iCECube2. NFC.
whitequark [Sun, 22 Sep 2019 07:17:12 +0000 (07:17 +0000)]
vendor.lattice_ecp5: simplify quoting. NFC.
See commit
ee1ad2da.
whitequark [Sun, 22 Sep 2019 06:57:28 +0000 (06:57 +0000)]
build.plat: restrict design names to alphanumeric to avoid quoting issues.
whitequark [Sat, 21 Sep 2019 14:27:35 +0000 (14:27 +0000)]
vendor.lattice_ice40: add iCECube support.
This also makes some iCE40 and ECP5 overrides more consistent.
whitequark [Sat, 21 Sep 2019 14:12:29 +0000 (14:12 +0000)]
build.res: simplify clock constraints.
Before this commit, it was possible to set and get clock constraints
placed on Pin objects. This was not a very good implementation, since
it relied on matching the identity of the provided Pin object to
a previously requested one. The only reason it worked like that is
deficiencies in nextpnr.
Since then, nextpnr has been fixed to allow setting constraints on
arbitrary nets. Correspondingly, backends that are using Synplify
were changed to use [get_nets] instead of [get_ports] in SDC files.
However, in some situations, Synplify does not allow specifying
ports in [get_nets]. (In fact, nextpnr had a similar problem, but
it has also been fixed.)
The simplest way to address this is to refer to the interior net
(after the input buffer), which always works. The only downside
of this is that requesting a clock as a raw pin using
platform.request("clk", dir="-")
and directly applying a constraint to it could fail in some cases.
This is not a significant issue.
whitequark [Sat, 21 Sep 2019 12:23:53 +0000 (12:23 +0000)]
build.plat: NMIGEN_<toolchain>_env→NMIGEN_ENV_<toolchain>
This is more consistent with other environment variables nMigen uses.
whitequark [Sat, 21 Sep 2019 06:53:39 +0000 (06:53 +0000)]
lib.fifo: update docs. NFC.
whitequark [Sat, 21 Sep 2019 06:53:13 +0000 (06:53 +0000)]
hdl.ast: update docs. NFC.
whitequark [Sat, 21 Sep 2019 06:09:30 +0000 (06:09 +0000)]
lib.fifo: simplify. NFC.
whitequark [Fri, 20 Sep 2019 19:50:43 +0000 (19:50 +0000)]
lib.fifo: fix doc typo. NFC.
whitequark [Fri, 20 Sep 2019 19:38:42 +0000 (19:38 +0000)]
lib.fifo: work around Yosys issue with handling of \TRANSPARENT.
Because of YosysHQ/yosys#1390, using a transparent port in AsyncFIFO,
instead of being a no-op (as the semantics of \TRANSPARENT would
require it to be in this case), results in a failure to infer BRAM.
This can be easily avoided by using a non-transparent port instead,
which produces the desirable result with Yosys. It does not affect
the semantics on Xilinx platforms, since the interaction between
the two ports in case of address collision is undefined in either
transparent (WRITE_FIRST) or non-transparent (READ_FIRST) case, and
the data out of the write port is not used at all.
Fixes #172.
whitequark [Fri, 20 Sep 2019 19:36:19 +0000 (19:36 +0000)]
hdl.mem: use 1 as reset value for ReadPort.en.
This is necessary for consistency, since for transparent read ports,
we currently do not support .en at all (it is fixed at 1) due to
YosysHQ/yosys#760. Before this commit, changing port transparency
would require adding or removing an assignment to .en, which is
confusing and error-prone.
Also, most read ports are always enabled, so this behavior is also
convenient.
whitequark [Fri, 20 Sep 2019 16:11:01 +0000 (16:11 +0000)]
vendor.lattice_{ecp5,ice40}: allow clock constraints on arbitrary signals.
Fixes #88.
whitequark [Fri, 20 Sep 2019 15:35:55 +0000 (15:35 +0000)]
hdl.ast: rename `nbits` to `width`.
Also, replace `bits, sign = x.shape()` with more idiomatic
`width, signed = x.shape()`.
This unifies all properties corresponding to `len(x)` to `x.width`.
(Not all values have a `width` property.)
Fixes #210.
Darrell Harmon [Fri, 20 Sep 2019 15:13:27 +0000 (09:13 -0600)]
vendor.xilinx_{7series,spartan3_6}: specialize MultiReg.
Vivado/ISE would otherwise infer an SRL16 from a MultiReg in some cases.
Emily [Fri, 20 Sep 2019 13:48:08 +0000 (14:48 +0100)]
setup: improve repository detection.
Emily [Fri, 20 Sep 2019 13:48:03 +0000 (14:48 +0100)]
setup: add setuptools dependency.
whitequark [Fri, 20 Sep 2019 11:53:05 +0000 (11:53 +0000)]
test.test_lib_fifo: fix typo.
whitequark [Fri, 20 Sep 2019 10:12:59 +0000 (10:12 +0000)]
back.pysim: fix simulation of Value.xor().
whitequark [Mon, 16 Sep 2019 18:59:28 +0000 (18:59 +0000)]
hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value; accept Enum patterns.
Fixes #207.
whitequark [Sat, 14 Sep 2019 21:06:12 +0000 (21:06 +0000)]
hdl.ast: add Value.matches(), accepting same language as Case().
Fixes #202.
whitequark [Sat, 14 Sep 2019 20:46:10 +0000 (20:46 +0000)]
hdl.dsl: improve error messages for Case().
whitequark [Fri, 13 Sep 2019 14:28:43 +0000 (14:28 +0000)]
hdl.ast: add Value.xor, mapping to $reduce_xor.
Fixes #147.
whitequark [Fri, 13 Sep 2019 13:14:52 +0000 (13:14 +0000)]
hdl.ast: add Value.{any,all}, mapping to $reduce_{or,and}.
Refs #147.
whitequark [Thu, 12 Sep 2019 20:01:28 +0000 (20:01 +0000)]
lib.fifo: adjust for new CDC primitive conventions.
Fixes #97.
whitequark [Thu, 12 Sep 2019 19:51:01 +0000 (19:51 +0000)]
lib.fifo: adjust properties to have consistent naming.
whitequark [Thu, 12 Sep 2019 21:56:48 +0000 (21:56 +0000)]
build.plat: bypass tool detection if NMIGEN_*_env is set.
It's not practical to detect tools within the toolchain environment
for various reasons, so just assume the tools are there if the user
says they are.
Before this commit, the tools would be searched outside the toolchain
environment, which of course would always fail for Vivado, ISE, etc.
whitequark [Thu, 12 Sep 2019 21:49:08 +0000 (21:49 +0000)]
vendor.xilinx_7series: Vivado requires bash on *nix as well.
whitequark [Thu, 12 Sep 2019 20:03:48 +0000 (20:03 +0000)]
hdl.mem: use keyword-only arguments as appropriate.
whitequark [Thu, 12 Sep 2019 19:36:45 +0000 (19:36 +0000)]
lib.fifo: make fwft a keyword-only argument.
Because it accepts a boolean.
whitequark [Thu, 12 Sep 2019 19:14:56 +0000 (19:14 +0000)]
lib.fifo: remove SyncFIFO.replace.
This obscure functionality was likely only ever used in old MiSoC
code, and doesn't justify the added complexity. It was also not
provided (and could not be reasonably provided) in SyncFIFOBuffered,
which made its utility extremely marginal.
whitequark [Thu, 12 Sep 2019 14:33:38 +0000 (14:33 +0000)]
README: update Yosys version requirement.
whitequark [Thu, 12 Sep 2019 13:54:48 +0000 (13:54 +0000)]
lib.cdc: make domain properties private.
It is not correct to access domain properties from user code, because
it will not match the reality if DomainRenamer has been applied to
the module.
whitequark [Thu, 12 Sep 2019 13:51:18 +0000 (13:51 +0000)]
lib.io: style. NFC.
whitequark [Thu, 12 Sep 2019 13:48:45 +0000 (13:48 +0000)]
lib.cdc: adjust ResetSynchronizer for new CDC primitive conventions.
Refs #97.
whitequark [Thu, 12 Sep 2019 13:48:24 +0000 (13:48 +0000)]
lib.cdc: adjust MultiReg for new CDC primitive conventions.
Refs #97.
whitequark [Wed, 11 Sep 2019 23:35:43 +0000 (23:35 +0000)]
build.plat,vendor: allow clock constraints on arbitrary signals.
Currently only done for Synopsys based toolchains (i.e. not nextpnr).
Refs #88.
whitequark [Wed, 11 Sep 2019 23:14:00 +0000 (23:14 +0000)]
back: return name map from convert_fragment().
whitequark [Tue, 10 Sep 2019 07:25:28 +0000 (07:25 +0000)]
hdl.ast: warn if reset value is truncated.
Fixes #183.
Darrell Harmon [Tue, 10 Sep 2019 03:32:36 +0000 (21:32 -0600)]
vendor.lattice_ecp5: pass ecppack_opts to ecppack.
whitequark [Sun, 8 Sep 2019 23:55:05 +0000 (23:55 +0000)]
hdl.ast: check type of Sample(domain=...).
Fixes #199.
whitequark [Sun, 8 Sep 2019 12:24:18 +0000 (12:24 +0000)]
hdl.dsl: add Default(), an alias for Case() with no arguments.
Fixes #197.
whitequark [Sun, 8 Sep 2019 12:19:13 +0000 (12:19 +0000)]
hdl.mem,lib,examples: use Signal.range().
whitequark [Sun, 8 Sep 2019 12:10:31 +0000 (12:10 +0000)]
hdl.ast: add Signal.range(...), to replace Signal(min=..., max=...).
Fixes #196.
whitequark [Fri, 6 Sep 2019 06:47:27 +0000 (06:47 +0000)]
Remove nmigen.lib from prelude.
Currently it's just MultiReg, and there's no particularly good reason
to privilege this specific CDC primitive so much.
whitequark [Fri, 6 Sep 2019 05:30:22 +0000 (05:30 +0000)]
Fix .gitignore.
whitequark [Fri, 6 Sep 2019 05:11:41 +0000 (05:11 +0000)]
setup: replace versioneer with setuptools_scm.
Has the same problems with git-archive but is much less invasive.