i915: Use C99 initializers for primitive arrays

Using C99 initializers for the primitive arrays makes things more
readable.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

tgsi: add const qualifier to silence warning

Trivial.

glsl: whitespace/formatting/typo fixes in link_uniforms.cpp

main: array stride for unsized arrays of arrays are calculated like records

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>

glsl: add std430 layout support for AoA

Signed-off-by: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>

docs: Mark GL_ARB_enhanced_layouts as in progress

i965: add EXT_polygon_offset_clamp support to gen4/gen5

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>

meta: Update comment about unsupported texture types.

Ken added support for 2DArray (commit ec23d5197e) and 1DArray (commit
14ca61125) last year.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

glx: Drop CRAY support.

It couldn't have worked anyway. There were calls to undefined functions.

Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>

glsl: Remove CSE pass.

With NIR, it actually hurts things.

total instructions in shared programs: 6529329 -> 6528888 (-0.01%)
instructions in affected programs:     14833 -> 14392 (-2.97%)
helped:                                299
HURT:                                  1

In all affected programs I inspected (including the single hurt one) the
pass CSE'd some multiplies and caused some reassociation (e.g., caused
(A * B) * C to be A * (B * C)) when the original intermediate result was
reused elsewhere.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Generalize predicated break pass for use in vec4 backend.

instructions in affected programs:     44204 -> 43762 (-1.00%)
helped:                                221

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/fs: Use backend_instruction in predicated break peephole.

We're not using any fs_inst fields, and the next commit will make the
peephole used by the vec4 backend.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

i965/fs: Remove SNB embedded-comparison support from optimizations.

We never emit IF instructions with an embedded comparison (lost in the
switch to NIR), so this code is not used. If we want to readd support,
we should have a pass that merges a CMP instruction with an IF or a
WHILE instruction after other optimizations have run.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

mesa: Add missing _mm_mfence() before streaming loads.

According to the Intel Software Development Manual (Volume 1: Basic
Architecture, 12.10.3 Streaming Load Hint Instruction):

   Streaming loads may be weakly ordered and may appear to software to
   execute out of order with respect to other memory operations.
   Software must explicitly use fences (e.g. MFENCE) if it needs to
   preserve order among streaming loads or between streaming loads and
   other memory operations.

That is, a memory fence is needed to preserve the order between the GPU
writing the buffer and the streaming loads reading it back.

Reported-by: Joseph Nuzman <joseph.nuzman@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

i965: Fix intel_miptree_is_fast_clear_capable()

There are three types of fast clears:
  a. fast depth clears
  b. fast singlesample color clears
  c. fast multisample color clears
Function intel_miptree_is_fast_clear_capable() checks if a miptree
supports fast clears of type (b).

Rename the function to disambiguate what it does:
  old: intel_miptree_is_fast_clear_capable
  new: intel_miptree_supports_non_msrt_fast_clear

The functionally accidentally rejected multisampled color surfaces
because it thought they were singlesample array surfaces. Fix that by
explicitly rejecting surfaces with samples > 1.

This fix would have been needed before we enabled layered fast
singlesample color clears (introduced in gen8), which we want to do
eventually. For now, though, this patch changes no behavior; it just
fixes how the driver chooses its behavior.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

i965/mt: Declare some functions as static

intel_tiling_supports_non_msrt_mcs() and
intel_miptree_is_fast_clear_capable() are not used outside of
intel_mipmap_tree.c.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>

i965: Make vec4_visitor's destructor virtual

We need a virtual destructor when at least one of the class' methods is virtual.
Failure to do so might lead to undefined behavior when destructing derived classes.
Fixes the following warning:

brw_vec4_gs_visitor.cpp: In function 'const unsigned int* brw::brw_gs_emit(brw_context*, gl_shader_program*, brw_gs_compile*, void*, unsigned int*)':
brw_vec4_gs_visitor.cpp:703:11: warning: deleting object of polymorphic class type 'brw::vec4_gs_visitor' which has non-virtual destructor might cause undefined behaviour [-Wdelete-non-virtual-dtor]
    delete gs;

Curro: This shouldn't be causing any actual bugs at the moment because
gen6_gs_visitor is the only subclass of vec4_visitor destroyed through
a pointer of a base class (vec4_gs_visitor *) and its destructor is
basically the same as its parent's. Anyway it seems sensible to change
this so it doesn't bite us in the future.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>

glsl: set glsl error if binding qualifier used on global scope

Fixes following Piglit test:
global-scope-binding-qualifier.frag

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

i965: Assert on the number of combined UBO and SSBO binding table entries

In theory we can't break this assertion since the compiler frontend checks
that we don't exceed any of the individual limits, but it does not hurt to
be extra safe.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Reserve binding table space for SSBO surfaces

These share the space with UBO surfaces but we need to make sure we
allocate enough space for both sets (12 of each)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Define BRW_MAX_SSBO

Instead of using hard-coded values.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Define BRW_MAX_UBO

Instead of using hard-coded values.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Remove more dead visitor/vertex program code.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Don't print line numbers with INTEL_DEBUG=optimizer.

The thing you want to do with the output files is diff them, which is
made more difficult by line numbers changing.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

nv30: always go through translate module on big-endian

It seems like things are either coming in slighly wrong, or perhaps
uploaded incorrectly, but either way passing them through the translate
module seems to fix everything. Eventually we should figure out what's
going wrong and fix it "for real", but this should do for now.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

nv30: pretend to have packed texture/surface formats

This puts us in line with what the DDX/DRI2 st are expecting. It also
happens to work... no idea why, but seems better to have it work than to
ask lots of questions.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org

st/dri: Use packed RGB formats

Fixes Gallium based DRI drivers failing to load on big endian hosts
because they can't find any matching fbconfigs.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71789
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Ilia Mirkin <imirkin@alum.mit.edu>

glsl: reduce memory footprint of uniform_storage struct

The uniform will only be of a single type so store the data for
opaque types in a single array.

Cc: Francisco Jerez <currojerez@riseup.net>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>

i965: Remove shader_prog from vec4_gs_visitor.

Unfortunately it has to stay in gen6_gs_visitor.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Use nir->has_transform_feedback_varyings to avoid shader_prog.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

nir: Add a nir_shader_info::has_transform_feedback_varyings flag.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>

nir: Introduce new nir_intrinsic_load_per_vertex_input intrinsics.

Geometry and tessellation shaders process multiple vertices; their
inputs are arrays indexed by the vertex number.  While GLSL makes
this look like a normal array, it can be very different behind the
scenes.

On Intel hardware, all inputs for a particular vertex are stored
together - as if they were grouped into a single struct.  This means
that consecutive elements of these top-level arrays are not contiguous.
In fact, they may sometimes be in completely disjoint memory segments.

NIR's existing load_input intrinsics are awkward for this case, as they
distill everything down to a single offset.  We'd much rather keep the
vertex ID separate, but build up an offset as normal beyond that.

This patch introduces new nir_intrinsic_load_per_vertex_input
intrinsics to handle this case.  They work like ordinary load_input
intrinsics, but have an extra source (src[0]) which represents the
outermost array index.

v2: Rebase on earlier refactors.
v3: Use ssa defs instead of nir_srcs, rebase on earlier refactors.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

nir/lower_io: Make get_io_offset() return a nir_ssa_def * for indirects.

get_io_offset() already walks the dereference chain and discovers
whether or not we have an indirect; we can just return that rather than
computing it a second time via deref_has_indirect().  This means moving
the call a bit earlier.

By returning a nir_ssa_def *, we can pass back both an existence flag
(via NULL checking the pointer) and the value in one parameter.  It
also simplifies the code somewhat.  nir_lower_samplers works in a
similar fashion.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>

glsl: fix whitespace

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>

radeonsi: enable PIPE_CAP_FORCE_PERSAMPLE_INTERP

Now st/mesa won't generate 2 variants for this state.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: do force_persample_interp in shaders for non-trivial cases

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: implement the simple case of force_persample_interp

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: move SPI_PS_INPUT_ENA/ADDR registers to a separate state

This will be a derived state used for changing center->sample and
centroid->sample at runtime.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

tgsi/scan: add interpolation info into tgsi_shader_info

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

st/mesa: automatically set per-sample interpolation if using SampleID/Pos

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

st/mesa: set force_persample_interp if ARB_sample_shading is used

This is only a half of the work. The next patch will handle
gl_SampleID/SamplePos, which is the other half of ARB_sample_shading.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

gallium: add per-sample interpolation control into rasterizer statOAe

Required by ARB_sample_shading for drivers that don't want a shader variant
in st/mesa.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Roland Scheidegger <sroland@vmware.com>

st/mesa: add ST_DEBUG=precompile support for tessellation shaders

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>

mesa: remove Driver.BindImageTexture

Nothing sets it.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove Driver.DeleteSamplerObject

Nothing overrides it.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove Driver.EndCallList

Nothing overrides it.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: remove Driver.BeginCallList

Nothing overrides it.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: remove Driver.EndList

Nothing overrides it.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: remove Driver.NewList

Nothing overrides it.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: remove Driver.NotifySaveBegin

Nothing overrides it.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: remove Driver.SaveFlushVertices

Nothing overrides it.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: remove Driver.FlushVertices

Nothing overrides it.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: remove Driver.BeginVertices

Nothing overrides it.

Reviewed-by: Brian Paul <brianp@vmware.com>

mesa: remove Driver.BindArrayObject

Nothing sets it.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove Driver.DeleteArrayObject

Nothing reimplements it.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove Driver.NewArrayObject

Nothing reimplements it.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove Driver.Hint

Nothing sets it.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove Driver.ColorMaskIndexed

Nothing sets it.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove some Driver.Blend* hooks

Nothing sets them.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove Driver.Accum

Nothing calls it.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove Driver.ResizeBuffers

Nothing overrides it.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove Driver.DeleteShaderProgram

Nothing overrides it.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove Driver.NewShaderProgram

Nothing overrides it.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

mesa: remove Driver.DeleteShader

Nothing overrides it.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

egl/dri2: don't require a context for ClientWaitSync (v2)

The spec doesn't require it. This fixes a crash on Android.

v2: don't set any flags if ctx == NULL
v3: add the spec note

Cc: 10.6 11.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Albert Freeman <albertwdfreeman@gmail.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>

st/dri: don't use _ctx in client_wait_sync

Not needed and it can be NULL.

v2: fix dri2_get_fence_from_cl_event - thanks Albert

Cc: 10.6 11.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Albert Freeman <albertwdfreeman@gmail.com>

r600g: only do depth-only or stencil-only in-place decompression

instead of always doing both.
Usually, only depth is needed, so stencil decompression is useless.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: only do depth-only or stencil-only in-place decompression

instead of always doing both.
Usually, only depth is needed, so stencil decompression is useless.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium/radeon: add separate stencil level dirty flags

We will only do depth-only or stencil-only decompress blits, whichever is
needed by textures, instead of always doing both.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: dump buffer lists while debugging

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

winsys/radeon: implement cs_get_buffer_list

This is more complicated, because tracking priority_usage needed changing
the relocs_bo type.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

winsys/amdgpu: add winsys function cs_get_buffer_list

For debugging.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium/radeon: stop using "reloc" in a few places

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

gallium/radeon: tell the winsys the exact resource binding types

Use the priority flags and expand them.
This information will be used for debugging.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: add an option for debugging VM faults

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

radeonsi: move dumping the last IB into its own function

v2: indentation fix

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

ddebug: separate creation of debug files

This will be used by radeonsi for logging.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

docs: add news item and link release notes for 10.6.9

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

docs: add sha256 checksums for 10.6.9

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 8957b696f9cc8a92b2c160c551c34545447ec28a)

docs: add release notes for 10.6.9

Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit ab9aacce2d26a802bac81fc25748320428996692)

egl: rework handling EGL_CONTEXT_FLAGS

As of version 15 of the EGL_KHR_create_context spec, debug contexts
are allowed for ES contexts.  We should allow creation instead of
erroring.

While we're here provide a more comprehensive checking for the other two
flags - ROBUST_ACCESS_BIT_KHR and FORWARD_COMPATIBLE_BIT_KHR

v2 [Emil Velikov] Rebase. Minor tweak in commit message.

Cc: Boyan Ding <boyan.j.ding@gmail.com>
Cc: Chad Versace <chad.versace@intel.com>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91044
Signed-off-by: Matthew Waters <ystreet00@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

i965/wm: Make compute_barycentric_interp_modes take a nir_shader and a devinfo

Now that everything comes in through NIR, we can pick this directly out of
the shader source and don't need to reference the gl_fragment_program.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Use nir_foreach_variable

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir: Add a nir_foreach_variable macro

This is a common enough operation that it's nice to not have to think about
the arguments to foreach_list_typed every time.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/nir: Remove the prog parameter from brw_nir_lower_inputs

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

radeon/llvm: Initialize gallivm targets when initializing the AMDGPU target v2

This fixes a race condition in the glx-multithreaded-shader-compile
test.

v2:
  - Replace gallivm_init_llvm_{begin,end}() with gallivm_init_llvm_targets().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
CC: "10.6 11.0" <mesa-stable@lists.freedesktop.org>

gallivm: Allow drivers and state trackers to initialize gallivm LLVM targets v2

Drivers and state trackers that use LLVM for generating code, must
register the targets they use with LLVM's global TargetRegistry.
The TargetRegistry is not thread-safe, so all targets must be added
to the registry before it can be queried for target information.

When drivers and state trackers initialize their own targets, they need
a way to force gallivm to initialize its targets at the same time.
Otherwise, there can be a race condition in some multi-threaded
applications (e.g. glx-multihreaded-shader-compile in piglit),
when one thread creates a context for a driver that uses LLVM (e.g.
radeonsi) and another thread creates a gallivm context (glxContextCreate
does this).

The race happens when the driver thread initializes its LLVM targets and
then starts using the registry before the gallivm thread has a chance to
register its targets.

This patch allows users to force gallivm to register its targets by
calling the gallivm_init_llvm_targets() function.

v2:
  - Use call_once and remove mutexes and static initializations.
  - Replace gallivm_init_llvm_{begin,end}() with
    gallivm_init_llvm_targets().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
CC: "10.6 11.0" <mesa-stable@lists.freedesktop.org>

gallium/radeon: Use call_once() when initailizing LLVM targets

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
CC: "10.6 11.0" <mesa-stable@lists.freedesktop.org>

i965/shader: Get rid of the shader, prog, and shader_prog fields

Unfortunately, we can't get rid of them entirely.  The FS backend still
needs gl_program for handling TEXTURE_RECTANGLE.  The GS vec4 backend still
needs gl_shader_program for handling transfom feedback.  However, the VS
needs neither and we can substantially reduce the amount they are used.
One day we will be free from their tyranny.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs,vec4: Get rid of the sanity_param_count

It doesn't exist for anything other than an assert that, as far as I can
tell, isn't possible to trip.  Soon, we will remove prog from the visitor
entirely and this will become even more impossible to hit.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/vec4: Use nir info instead of pulling things out of [shader_]prog

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Use the nir info instead of pulling things out of [shader_]prog

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/fs: Move sampler unit lookup into rescale_texcoord

The texunit variable we create and assign in nir_emit_texture gets passed
through two more layers of function calls before it gets to its sole use in
rescale_texcoord.  The best part is that we already pass the sampler into
rescale_texcoord so we can just look it up there.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/cs: Remove the prog argument from local_id_payload_dwords

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965/backend_shader: Add a field to store the NIR shader

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir: Move GS data to nir_shader_info

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir: Add a a nir_shader_info struct

This commit also adds code to glsl_to_nir and prog_to_nir to fill it out.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

nir/glsl: Take a gl_shader_program and a stage rather than a gl_shader

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Move prog_data uniform setup to the codegen level

As of now, uniform setup is more-or-less unified between vec4 and fs and no
longer requires the fs_visitor.  This makes uniform setup more of a
language/API thing than a backend compiler thing.  This commit moves
setting up the stage_prog_data.params arrays to the same place as we set up
the rest of stage_prog_data.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

i965: Move binding table setup to codegen time.

Setting up binding tables really has little to do with the actual process
of turning shaders into instructions; it's more part of setting up
prog_data.  This commit moves it out of the visitors and with the rest of
the prog_data setup stuff.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>