gem5.git
5 years agosystemc: Remove redundant tlm_ prefixes from file names.
Gabe Black [Tue, 11 Dec 2018 07:02:13 +0000 (23:02 -0800)]
systemc: Remove redundant tlm_ prefixes from file names.

We already know those files belong to tlm because of the directory
they're in. Removing the prefix makes the paths of the headers less
enormously long.

Change-Id: I869e58fae904162f353bb31f4c0919fba08dffa6
Reviewed-on: https://gem5-review.googlesource.com/c/15059
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

5 years agosystemc: Replace some calls to some Accellera specific functions in TLM.
Gabe Black [Thu, 13 Dec 2018 00:07:58 +0000 (16:07 -0800)]
systemc: Replace some calls to some Accellera specific functions in TLM.

The TLM event finder class was calling implementation specific
functions from the Accellera version of systemc. This change replaces those
calls with equivalent calls which match the gem5 implementation.

Change-Id: I0ecdb0a4bf09aeb1aad823a01105fbd88edb4601
Reviewed-on: https://gem5-review.googlesource.com/c/15075
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

5 years agosystemc: Rename tlm .cpp files to .cc and add SConscripts.
Gabe Black [Thu, 3 Jan 2019 05:16:38 +0000 (21:16 -0800)]
systemc: Rename tlm .cpp files to .cc and add SConscripts.

Change-Id: Ia30192b441dd34bc7165c6335386c88c0015fdf6
Reviewed-on: https://gem5-review.googlesource.com/c/15295
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

5 years agosystemc: Fix style issues in the TLM header files.
Gabe Black [Sat, 8 Dec 2018 10:05:34 +0000 (02:05 -0800)]
systemc: Fix style issues in the TLM header files.

Change-Id: Id12ffb9b56b3887afcf30120f81ce5eb75a5987b
Reviewed-on: https://gem5-review.googlesource.com/c/15057
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

5 years agosystemc: Also look for tests in the tlm test directory.
Gabe Black [Sat, 8 Dec 2018 09:59:34 +0000 (01:59 -0800)]
systemc: Also look for tests in the tlm test directory.

Both basic systemc and tlm tests were present, but scons only looked
in the systemc directory when populating the test json. This change
makes it also look in the tlm directory so that those tests can be run.

Change-Id: Id65b744664350f6105fb3a4f28cbc7ab91d8c82e
Reviewed-on: https://gem5-review.googlesource.com/c/15056
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

5 years agosystemc: Initial import of TLM headers from Accellera.
Gabe Black [Sat, 8 Dec 2018 09:58:26 +0000 (01:58 -0800)]
systemc: Initial import of TLM headers from Accellera.

These headers will need to be cleaned up and have some Accellera
specific quirks ironed out of them, but I'll do that in a later change
to make it clear what those changes are.

Change-Id: Ia4e08633ab552b4c616c66c9b7e2bbd78ebfe7b9
Reviewed-on: https://gem5-review.googlesource.com/c/15055
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>

5 years agosystem-arm: Add device tree for new VExpress GEM5_V2 platform
Jairo Balart [Tue, 13 Nov 2018 10:02:46 +0000 (11:02 +0100)]
system-arm: Add device tree for new VExpress GEM5_V2 platform

Change-Id: Ifc2b91afe5b88a656b4ed1c64ab6cca97f082034
Reviewed-on: https://gem5-review.googlesource.com/c/14275
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agosystem-arm: Add aarch64 bootloader support for GICv3
Jairo Balart [Thu, 11 Oct 2018 14:03:24 +0000 (16:03 +0200)]
system-arm: Add aarch64 bootloader support for GICv3

Change-Id: If75262709868cc59d320f60273a32397339f1dd5
Signed-off-by: Jairo Balart <jairo.balart@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13435
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agoscons: Disable partial linking on Mac OS
Nikos Nikoleris [Sun, 23 Dec 2018 11:16:27 +0000 (11:16 +0000)]
scons: Disable partial linking on Mac OS

Up until Apple LLVM version 10.0.0 (clang-1000.11.45.5), partial
linked objects do not expose symbols that are marked with the hidden
visibility and consequently building gem5 on Mac OS fails. As a
workaround, we disable partial linking, however, we may want to
revisit in the future.

Change-Id: I0a26dae082bf723c2bd49d90e4497e44ecab9c41
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15235
Reviewed-by: Andrea Mondelli <andrea.mondelli@ucf.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

5 years agodev, arm: Warn on PL011 DMA disable
Jan-Peter Larsson [Thu, 20 Dec 2018 15:55:56 +0000 (15:55 +0000)]
dev, arm: Warn on PL011 DMA disable

The PL011 spec specifies a DMACR register at offset 0x48, which isn't
implemented in the model. Currently any attempt to access the register
results in a panic.

This change swaps the panic for a warning only when software writes into
DMACR to disable DMA, keeping the panic otherwise.

Change-Id: I04586b52df8d5d174536276fd7ae19e77ff4681a
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15279
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agodev-arm: Added VGIC GICV_IIDR response
Anouk Van Laer [Wed, 7 Nov 2018 14:04:47 +0000 (14:04 +0000)]
dev-arm: Added VGIC GICV_IIDR response

Change-Id: I60e8eadbbbf07c0f8b726213fd580aeb0dd0e00b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15278
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agodev-arm: Implement GIC-400 model from GicV2
Giacomo Travaglini [Fri, 21 Dec 2018 10:26:55 +0000 (10:26 +0000)]
dev-arm: Implement GIC-400 model from GicV2

Implementation registers for the GICv2 model currently hold values
referring to a GIC-400 implementation. This patch is making them
parametrizable so that it is possible to instantiate a GIC-400 model.
The patch is also modifying Realview platform to use new GIC-400 model
in lieau of GICv2.

Change-Id: I446db8c796ee3c2708af91e9139f0a6e7947321b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15277
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agodev-arm: Move VGic from Realview.py to Gic.py
Giacomo Travaglini [Thu, 20 Dec 2018 17:31:42 +0000 (17:31 +0000)]
dev-arm: Move VGic from Realview.py to Gic.py

Change-Id: I17f2fb6be2435d4601263e7f68a0582e0cc70838
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15276
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agodev-arm: Added unimplemented GICv2 GICC_DIR
Anouk Van Laer [Thu, 27 Sep 2018 15:49:30 +0000 (16:49 +0100)]
dev-arm: Added unimplemented GICv2 GICC_DIR

This GICC CPU register is not implemented but just gives a warning.

Change-Id: I7630aa1df78dde5cf84a87e26cd580b00b283673
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15275
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

5 years agoarm: properly handle RES0/1 for SCTLRs
Curtis Dunham [Mon, 7 May 2018 23:06:08 +0000 (18:06 -0500)]
arm: properly handle RES0/1 for SCTLRs

They were being treated as RAZ/RAO, which is incorrect.
Put the access masks in the register metadatabase now that we have one.

Also fix this for HVBAR.

Change-Id: I097c847e35be2d59fb8235fc621bb061ef514cfb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/10401
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agocpu: Stop using unions to store FP registers.
Gabe Black [Tue, 20 Nov 2018 01:30:06 +0000 (17:30 -0800)]
cpu: Stop using unions to store FP registers.

These are now accessed only as integer values.

Change-Id: I21ae6537ebbcbaa02890384194ee1ce001c092bb
Reviewed-on: https://gem5-review.googlesource.com/c/14458
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarch, cpu: Remove float type accessors.
Gabe Black [Tue, 20 Nov 2018 01:20:31 +0000 (17:20 -0800)]
arch, cpu: Remove float type accessors.

Use the binary accessors instead.

Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2
Reviewed-on: https://gem5-review.googlesource.com/c/14457
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarch-arm: Add Crypto in SE mode
Giacomo Travaglini [Thu, 20 Sep 2018 13:13:11 +0000 (14:13 +0100)]
arch-arm: Add Crypto in SE mode

This patch is also enabling AArch32 crypto instructions by setting the
ID_ISAR5 register accordingly.

Change-Id: Id412585b39b78570a65bd3047199c84e9db76cda
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15155
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agosystemc: Allow specific functions to shadow the base class method
Nikos Nikoleris [Mon, 17 Dec 2018 15:50:04 +0000 (15:50 +0000)]
systemc: Allow specific functions to shadow the base class method

sc_in::bind and sc_core::sc_object::print shadow their respective base
class method. This change adds the necessary declarations to inform
the compiler that this is intentional.

Change-Id: I8c6bc0f05aa568630783db63d52be90f4ea4748c
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15135
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoscons: Disable systemc on Mac OS
Nikos Nikoleris [Sun, 2 Dec 2018 18:39:32 +0000 (18:39 +0000)]
scons: Disable systemc on Mac OS

LLVM on Mac OS up until version 10.0.0 doesn't seem to support the
attribute for weak linking and fails to compile. Additionally, even
the basic example tests fail. Therefore, this change disables systemc
by default on Mac OS until we address these issues.

Change-Id: Iaa6360ec61317e01f4e645af8b509961b3144282
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14818
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarch: Make the ISA parser always use binary floating point accessors.
Gabe Black [Tue, 20 Nov 2018 00:50:41 +0000 (16:50 -0800)]
arch: Make the ISA parser always use binary floating point accessors.

Any operands which use read_code or write_code would need to start
using the floatToBits and bitsToFloat, but only ARM is using that
mechanism, and not on float operands.

Also I notice that the "predicate" mechanism for operands ignores the
read_code and write_code mechanism, and using both will not work
correctly. This change makes no attempt to fix that problem, but
shouldn't contribute to it either.

Change-Id: I0e3a7f78ed28f40cb66958ef12c32e862950fde0
Reviewed-on: https://gem5-review.googlesource.com/c/14456
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Ensure resets and edges are notified when signaling a change.
Gabe Black [Wed, 5 Dec 2018 00:17:30 +0000 (16:17 -0800)]
systemc: Ensure resets and edges are notified when signaling a change.

Boolean sc_buffers (either pure bool or sc_dt::sc_logic) should signal
positive and negative edges and resets even when their value doesn't
change, unlike sc_signals. The spec doesn't actually say that and just
mentions the value changed event, but it may have been implied that the
other types of events also happen, they just made special mention of
the value change event.

This change moves some code around a bit so that when _signalChange()
is called, if the underlying type is a boolean signal, it will
automatically notify the appropriate edge event and signal any reset.
Putting the functionality in _signalChange instead of delegating it to
the sc_buffer lets us have a single template for sc_buffer and makes
the base class template specialization handle whether the edge events
exist, and if so which should be notified.

Change-Id: Ic4ca86afc3fde6a9df5c15a0a7386e24ac89a9e2
Reviewed-on: https://gem5-review.googlesource.com/c/14916
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agocpu: Fixed typos in parameter/stats descriptions
Pau Cabre [Sat, 1 Dec 2018 23:20:13 +0000 (00:20 +0100)]
cpu: Fixed typos in parameter/stats descriptions

Change-Id: I7b3274a3e37128da35f497da150af08343e97ee6
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14795
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agocpu: Added parameters to enable/disable features in LTAGE
Pau Cabre [Fri, 23 Nov 2018 22:29:35 +0000 (23:29 +0100)]
cpu: Added parameters to enable/disable features in LTAGE

They are for the following features in the LTAGE loop predictor:
 - Hashing for calculating the loop table entry
 - Add direction information
 - Add speculative iteration number information

Change-Id: I395f4526163ee0d0229d1e87cde2bb046f1dd43a
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14597
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Louis Delhez <ldelhez@ucla.edu>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agocpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctor
Tony Gutierrez [Tue, 11 Dec 2018 00:20:06 +0000 (19:20 -0500)]
cpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctor

Change 9af1214 added a new ctor to the LSQUnit, however
there is a typo/bug because it sizes the SQEntries
member variable to lqEntries + 1, as opposed to
sqEntries + 1. This change corrects the issue by
using sqEntries.

Change-Id: I19dfaa5c0e335bd7b84343a92034147d7c5d914e
Reviewed-on: https://gem5-review.googlesource.com/c/15015
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agosystemc: Update test output for longer lived processes.
Gabe Black [Thu, 6 Dec 2018 02:02:14 +0000 (18:02 -0800)]
systemc: Update test output for longer lived processes.

In the systemc spec, process handles can be invalidated if they have no
children and are terminated. The implementation is not required to do
so however, and for the sake of simplicity gem5 currently does not. To
quote:

"When the underlying process instance terminates, if the process
instance has no surviving children, an implementation may choose to
invalidate any associated process handles, but it is not obliged to do
so."

Two tests have reference output which is affected by this (legal)
difference in behavior. In one case, the test creates new processes
which reuse the names of processes that have been terminated. Since
gem5 doesn't invalidate the old processes, a standard mechanism is
activated which renames the processes to something which is unique.

The other test has this same problem, and also prints the hierarchy
of processes several times during the test. In that hierarchy, the
terminated tests with no live children are still present, where in the
old reference output they've been removed.

This change updates the reference output to match gem5's behavior.

Change-Id: I363448de10080bdce01a4df92f991c67b31a2401
Reviewed-on: https://gem5-review.googlesource.com/c/14919
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Update the ordering in the reference output for some tests.
Gabe Black [Wed, 5 Dec 2018 00:30:45 +0000 (16:30 -0800)]
systemc: Update the ordering in the reference output for some tests.

There are a number of cases where systemc leaves the decision of what
order things happen up to the kernel, and any ordering is legal and
conformant with the spec as long as it's repeatable. The reference
outputs reflect a particular choice of ordering which is implementation
specific, and while considerable effort has been made to make the gem5
ordering match the Accellera ordering, at a certain point that's no
longer practical or desirable.

This change manually updates the reference output for the tests that
haven't been excluded for other reasons which have this sort of ordering
problem. They have been individually examined, and as best as I can
tell changing the output this way does not mask any underlying error.

One or two real problems were discovered in addition to the ordering
issues, and those were fixed in earlier changes.

Change-Id: I915269998de3f33d5ab5d1fd754a830fd620184d
Reviewed-on: https://gem5-review.googlesource.com/c/14918
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Ignore process control functions on terminated processes.
Gabe Black [Thu, 6 Dec 2018 01:45:31 +0000 (17:45 -0800)]
systemc: Ignore process control functions on terminated processes.

These functions can descend to the children of a terminated process,
but should have no effect on that process itself.

Change-Id: I6e4bdec8c492dd03d05bc1397aa080e8a51397c1
Reviewed-on: https://gem5-review.googlesource.com/c/14917
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Update signals before initing processes.
Gabe Black [Sat, 1 Dec 2018 00:57:02 +0000 (16:57 -0800)]
systemc: Update signals before initing processes.

We were supposed to do one update phase before adding all processes
which didn't have dont_initialize() called to the run queue. We were
doing that in the opposite order.

Change-Id: I6dd4108040d455dc78029da029a2eb5e7af819cb
Reviewed-on: https://gem5-review.googlesource.com/c/14915
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase, systemc: Fix clang compilation
Giacomo Travaglini [Fri, 7 Dec 2018 11:21:24 +0000 (11:21 +0000)]
base, systemc: Fix clang compilation

This patch is fixing the following issues:

- base: typename should be used only for types
- systemc: 'GCC_VERSION' is not defined for clang

Change-Id: I27c94445d65691a08a0a14a0ffe6b6942f6c455f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14976
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agomem: Compile tracePacket only when TRACING_ON is defined
Giacomo Travaglini [Fri, 7 Dec 2018 11:05:55 +0000 (11:05 +0000)]
mem: Compile tracePacket only when TRACING_ON is defined

If TRACING_ON is not defined (e.g. when building gem5.fast), clang
compilations will fail reporting an unused function.

Change-Id: I959dba6e9fcf74b951e16365077939ae4d4ef924
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14975
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agomem-cache: Workaround for setWhenReady assertion
Daniel R. Carvalho [Fri, 7 Dec 2018 09:50:31 +0000 (10:50 +0100)]
mem-cache: Workaround for setWhenReady assertion

Change 174da8e2da6a896d2e97bc264f9c827a0f4c35ac added an assert that
is not satisfiable with current implementation, breaking some
regression tests.

Change-Id: Ibafaf0c51906384364f0b2a4b931f8ec6126d858
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14955
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agoext: Remove unused bankwiseMode variable
Matteo Andreozzi [Tue, 2 Oct 2018 14:33:28 +0000 (15:33 +0100)]
ext: Remove unused bankwiseMode variable

Apple LLVM version 10.0.0 (clang-1000.11.45.2) complains about
unused members variables

Change-Id: If1f2210c09e80b632cb3688aaa7df0594f9e49c9
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13228
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agobase: Ported circlebuf to CircularQueue
Rekai Gonzalez-Alberquilla [Thu, 6 Apr 2017 11:27:20 +0000 (12:27 +0100)]
base: Ported circlebuf to CircularQueue

Ported the existing circlebuf on top of the CircularQueue to condense
shared functionality and minimise code/functionality replication.

Additional contributors: Gabor Dozsa.

Change-Id: Ib4e67c638f0fb66b54cef77007a03439218bda7f
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13128
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
6 years agobase: Iterable CircularQueue implementation
Rekai Gonzalez-Alberquilla [Wed, 26 Apr 2017 16:44:33 +0000 (17:44 +0100)]
base: Iterable CircularQueue implementation

The former implementation of CircleBuf is functional but a bit too
tailored to match a use-case. This patches introduces a new iterable
circular queue, which adds some more functionality so it can also be
used for the newer LSQ implementation, where iteration and iterators
are a very desirable feature.

Additional contributors: Gabor Dozsa.

Change-Id: I5cfb95c8abc1f5e566a114acdbf23fc52a38ce5e
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13127
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
6 years agoext: Build googlemock with googletest
Giacomo Travaglini [Mon, 3 Dec 2018 11:37:51 +0000 (11:37 +0000)]
ext: Build googlemock with googletest

googlemock needs to be built together with googletest. This patch
is enabling it by doing the following things

* Moving googletest and googlemock under the same top level directory,
  so that we have a single SConscript for building them.
  This also matches googletest directory structure:
  googletest
      |_googletest
      |_googlemock

* Adding a shared SConscript which is building gmock and gtest as libgtest
* Removing googletest/SConscript

Change-Id: I88accbdd2e80fb47efaa17819233371fbad6acaa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14696
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoext: Import googlemock, release version 1.8.0
Giacomo Travaglini [Wed, 14 Nov 2018 18:41:19 +0000 (18:41 +0000)]
ext: Import googlemock, release version 1.8.0

gtest 1.8.0 is already part of gem5; this patch adds a matching gmock
so that it is possible to create Mocks in gem5 unit tests.

Please note: the commit is just importing the source code as it is
without adding any SConscript; it is hence unbuildable at the moment.
Next commits will integrate the mocking framework into the gem5
build system

Change-Id: Iaf05ad91b1964aac7ea37085f839027a8d34ba3e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14695
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarch-x86: Add sys/syscall.h to x86 process.cc/syscall_emul.cc
Tony Gutierrez [Fri, 30 Nov 2018 17:19:21 +0000 (12:19 -0500)]
arch-x86: Add sys/syscall.h to x86 process.cc/syscall_emul.cc

Change a66d12c guards the selection of getdents()
in x86's process.cc file with SYS_getdents, however
process.cc does not include the right header for
SYS_getdents, which leads to x86 choosing the
unimplemented call. This change adds sys/syscall.h to
address the problem.

This change also adds sys/syscall.hh to syscall_emu.cc,
which only includes syscall.hh and may not be supported on
all systems.

Change-Id: If1adcf41e9e455de5f2827ba98c542fdcacdc22e
Reviewed-on: https://gem5-review.googlesource.com/c/14775
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

6 years agomem-cache: Remove writebacks parameter from serviceMSHRTargets
Daniel R. Carvalho [Wed, 5 Dec 2018 14:06:56 +0000 (15:06 +0100)]
mem-cache: Remove writebacks parameter from serviceMSHRTargets

Change 8ba77ae8fc98a355082da2bd9fdc6ecf4928f725 introduced the
writebacks parameter, but it was never used.

Change-Id: I225e5b399de42d77c72fc0012d3dc93ef39b8853
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14896
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agomem-cache: Add getter and setter to CacheBlk::whenReady
Daniel R. Carvalho [Wed, 28 Nov 2018 12:54:42 +0000 (13:54 +0100)]
mem-cache: Add getter and setter to CacheBlk::whenReady

Add a getter and a setter function to access CacheBlk::whenReady
to encapsulate the variable and allow error checking. This error
checking consists on verifying that writes to a block after it
has been inserted follow a chronological order.

As a side effect, tickInserted retain its value until updated,
that is, it is not reset in invalidate().

Change-Id: Idc3c5a99c3f002ee9acc2424f00e554877fd3a69
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14715
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agobase: Fix fiber compilation issue for Mac OS
Nikos Nikoleris [Sat, 1 Dec 2018 14:52:23 +0000 (14:52 +0000)]
base: Fix fiber compilation issue for Mac OS

Mac OS has deprecated the use of ucontext and at the moment we are
using a workaround to enable it. A side-effect is that the code is
marked as _POSIX_C_SOURCE and consequently <sys/mman.h> requires the
code to be also marked as _DARWIN_C_SOURCE to include the definition
of MAP_ANONYMOUS.

Change-Id: I65550d11a0a21cd36d832a7de6320e7e3f332a9d
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14817
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase, sim: Add missing destructors
Nikos Nikoleris [Wed, 28 Nov 2018 08:16:33 +0000 (08:16 +0000)]
base, sim: Add missing destructors

Derived classes with virtual functions need to define a virtual
destructor or a protected destructor otherwise calling the base class
destructor has undefined behavior. This change adds a virtual
distructor in the base class.

Change-Id: I1c855aa56dff6585ff99b9147bdb4eb9729a0a53
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14815
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agobase: Add type alias for raw pointer in RefCountingPtr
Giacomo Gabrielli [Mon, 22 Oct 2018 16:21:45 +0000 (17:21 +0100)]
base: Add type alias for raw pointer in RefCountingPtr

Change-Id: Ied2204566a8fc5c34fb4702301051b8e5ab84ffe
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13717
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agomem-cache: Optimize sector valid and secure check
Daniel R. Carvalho [Thu, 25 Oct 2018 15:52:26 +0000 (17:52 +0200)]
mem-cache: Optimize sector valid and secure check

Previously a loop was being done to check whether the
block was valid/secure or not. Variables have been
added to skip this loop and save and update sector
block state when sub-blocks are validated, invalidated
and secured.

Change-Id: Ie1734f7dfda9698c7bf22a1fcbfc47ffb9239cea
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14363
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agocpu: Change raw pointers to STL Containers
Rekai Gonzalez-Alberquilla [Wed, 1 Mar 2017 13:49:08 +0000 (13:49 +0000)]
cpu: Change raw pointers to STL Containers

This patch changes two members from being raw pointers to being STL
containers. The reason behind, other than cleanlyness and arguable OO
best practices is that containers have more intronspections capabilities
than naked pointers do, as the size is known.

Using STL containers adds little overhead and eases the automation of
process during debugging (gdb).

Change-Id: I4d9d3eedafa8b5e50ac512ea93b458a4200229f2
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13126
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agoarch-arm: correctly set floats from GDB on aarch64
Ciro Santilli [Thu, 15 Nov 2018 00:00:00 +0000 (00:00 +0000)]
arch-arm: correctly set floats from GDB on aarch64

aarch64 floating point registers are now stored as vector type, but this
was not updated in the stub.

Change-Id: I4a2bc1cea0eec9beeb5bbd49e2a868b9d5ed0a42
Reviewed-on: https://gem5-review.googlesource.com/c/14498
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

6 years agobase: increase the GDB buffer size dynamically
Ciro Santilli [Wed, 14 Nov 2018 00:00:01 +0000 (00:00 +0000)]
base: increase the GDB buffer size dynamically

The size was not large enough for the 'G' packet on aarch64, which the
client sends to set registers.

This would lead to the stub not to be able to find the end of the input
packet and keep waiting forever.

Change-Id: Icb149f15a6c769371ebcb6ec5fbebc6170c31fc6
Reviewed-on: https://gem5-review.googlesource.com/c/14497
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarch-arm: only change the pc address when GDB registers are set
Ciro Santilli [Wed, 14 Nov 2018 00:00:00 +0000 (00:00 +0000)]
arch-arm: only change the pc address when GDB registers are set

The entire pcState was being reset, which made the simulation incorrectly
switch to aarch32 from aarch64.

Change-Id: I9ba7dd0ed95bc6120d94393bba272e0cb8c081c5
Reviewed-on: https://gem5-review.googlesource.com/c/14496
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

6 years agoarch-arm: fix the aarch64 GDB stub
Ciro Santilli [Wed, 18 Jul 2018 17:00:51 +0000 (18:00 +0100)]
arch-arm: fix the aarch64 GDB stub

The main change is to remove vector registers from the GDB stub.

Those registers were intended for SVE, which is a new architecture feature
and not yet treated by default on the GDB present in Ubuntu 18.04, and
possibly not even on GDB master.

As a result, aarch64 GDB stub connections would fail with:

Remote 'g' packet reply is too long

The correct way to support those registers is to send XML GDB target
description files to the client. This feature is not yet available for
any architecture, and should be implemented in future patches.

Other smaller fixes are:

* cpsr is uint32_t in aarch64 as well as arm
* use M5_ATTR_PACKED on the register structs since they are being cast and
  sent as byte arrays

Change-Id: I77cd8a98e322ecc60799e5b11fe5cd414d893cc7
Reviewed-on: https://gem5-review.googlesource.com/c/14495
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

6 years agosystemc: Disable systemc when using gcc versions older than 5.0.
Gabe Black [Fri, 30 Nov 2018 01:33:46 +0000 (17:33 -0800)]
systemc: Disable systemc when using gcc versions older than 5.0.

These versions don't support the std::put_time function. Since versions
of gcc older than 5.0 aren't going to be supported at all in the fairly
near future, this should only be temporary. The number of people using
both systemc and older versions of gcc should be very small, or even
zero.

Change-Id: Ie9572fdf83ba9569df6bc0457c98d86565dcdcd8
Reviewed-on: https://gem5-review.googlesource.com/c/14755
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase: Change the unit test binary names to use .test, and to be consistent.
Gabe Black [Thu, 29 Nov 2018 01:40:17 +0000 (17:40 -0800)]
base: Change the unit test binary names to use .test, and to be consistent.

Most tests were named *test where * was the base name of the file being
tested, but some were named differently based on, for instance, the
name of the class that file implemented.

This change makes all the test names consistently based off of the file
name they test, and also brings in the new .test convention to make
them easier to read.

Now, if you have a file like fiber.cc you want to test, you'd have a
unit test in a file called fiber.test.cc, and a test called fiber.test
which would generate a binary called fiber.test.opt, fiber.test.debug,
etc.

Change-Id: I61d59016090371a9bae72066e7473a34aecea21f
Reviewed-on: https://gem5-review.googlesource.com/c/14677
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase: Rename unit test cc files to be *.test.cc.
Gabe Black [Thu, 29 Nov 2018 01:36:28 +0000 (17:36 -0800)]
base: Rename unit test cc files to be *.test.cc.

This makes the name easier to read, looks ok if the file is named with
underscores between words or not, is easy to grep for, and shouldn't
introduce any ambiguities in the file names.

Change-Id: I34b7bcccea2d87c10c0de417dd5e3ef27c4b5666
Reviewed-on: https://gem5-review.googlesource.com/c/14676
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoutil: Add the scons configuration cache to .gitignore for util/tlm.
Gabe Black [Tue, 27 Nov 2018 03:18:26 +0000 (19:18 -0800)]
util: Add the scons configuration cache to .gitignore for util/tlm.

Change-Id: Ife31e1bbf862d10bbe8e2c0fa36c8c168cfafa84
Reviewed-on: https://gem5-review.googlesource.com/c/14656
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Update the gem5-within-systemc README to mention USE_SYSTEMC.
Gabe Black [Thu, 22 Nov 2018 01:59:16 +0000 (17:59 -0800)]
systemc: Update the gem5-within-systemc README to mention USE_SYSTEMC.

When linking with an external systemc host, the native gem5 systemc API
should be disabled to avoid linking conflicts.

Change-Id: If7f9b3718fcdbdab5ebc9ef52e746f6bf9f2fb9c
Reviewed-on: https://gem5-review.googlesource.com/c/14520
Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase: Fix include order in the inifile unit test.
Gabe Black [Thu, 29 Nov 2018 01:34:33 +0000 (17:34 -0800)]
base: Fix include order in the inifile unit test.

Even though gtest.h is a C++ header, it looks like a C header which
makes the style check hook upset. Lets move it up so the hook doesn't
complain when the file is changed.

Change-Id: Ibcc2d0b7bf3b254c70e55b30379ebd4b70933c26
Reviewed-on: https://gem5-review.googlesource.com/c/14675
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agosystemc: Run the systemc tests directly from their build directories.
Gabe Black [Thu, 22 Nov 2018 01:51:46 +0000 (17:51 -0800)]
systemc: Run the systemc tests directly from their build directories.

We were previously running them from the current directory to start
with, and then having the config script switch to the build directory.
That worked, except when output streams might be opened as part of the
global constructors which would run before the config script.

This change makes us start from the build directory directly, making
the switch in the config script unnecessary and ensuring that no files
leak outside of the build when running tests.

Change-Id: I484168793bfc5abc4e5631fb3468733fb9d829af
Reviewed-on: https://gem5-review.googlesource.com/c/14519
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Run the systemc tests with the CWD in the build directory.
Gabe Black [Thu, 22 Nov 2018 01:35:28 +0000 (17:35 -0800)]
systemc: Run the systemc tests with the CWD in the build directory.

This will prevent some (but not all) output files the tests generate
from ending up outside the build directory. Because some output file
streams are constructed as global objects, their paths are resolved
relative to the CWD when gem5 starts, before the config script has a
chance to change it.

Subsequent changes will make verify.py should make gem5 start with the
correct working directory, cleaning up the remaining leaking files.

Change-Id: I75a1256719dab4c98ab868c209d09b9dcdabb458
Reviewed-on: https://gem5-review.googlesource.com/c/14518
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Add DEPS files for some tests with non-source file dependencies.
Gabe Black [Thu, 22 Nov 2018 01:34:36 +0000 (17:34 -0800)]
systemc: Add DEPS files for some tests with non-source file dependencies.

This ensures that those files will be available when running the test
relative to its build directory.

Change-Id: If775ca328b3e1165baa968e4b39c36db0172837c
Reviewed-on: https://gem5-review.googlesource.com/c/14517
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Make verify.py recognize a DEPS file in test dirs.
Gabe Black [Thu, 22 Nov 2018 00:59:32 +0000 (16:59 -0800)]
systemc: Make verify.py recognize a DEPS file in test dirs.

This file lists additional files beyond the sources that the test
relies on, like files it uses when running.

Change-Id: Ifc4958b26eed08689e0e72bd87f84388dbcf1898
Reviewed-on: https://gem5-review.googlesource.com/c/14516
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase: Add missing overrides in statistics header
Nikos Nikoleris [Wed, 28 Nov 2018 08:00:57 +0000 (08:00 +0000)]
base: Add missing overrides in statistics header

Change-Id: Id5ee2a970a3dceee1b7e24ce3b452b7fece87875
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14619
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agoarch-arm: Add missing template declaration
Nikos Nikoleris [Wed, 28 Nov 2018 07:58:32 +0000 (07:58 +0000)]
arch-arm: Add missing template declaration

The lack of a template declaration for IllegalInstSetStateFault was
causing errors when compiling with clang.

Change-Id: If7f19d7e879330226c80df2baca73d88d818f673
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14618
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

6 years agocpu: Added new stats to TAGE and LTAGE branch predictors
Pau Cabre [Thu, 22 Nov 2018 13:48:30 +0000 (14:48 +0100)]
cpu: Added new stats to TAGE and LTAGE branch predictors

They are basically used to tell wich component of the predictor is
providing the prediction and whether it is correct or wrong

Change-Id: I7b3db66535f159091f1b37d70c2d942d50b20fb2
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14535
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agocpu: split LTAGE implementation into a base TAGE and a derived LTAGE
Pau Cabre [Tue, 20 Nov 2018 00:04:56 +0000 (01:04 +0100)]
cpu: split LTAGE implementation into a base TAGE and a derived LTAGE

The new derived LTAGE is equivalent to the original LTAGE implementation
The default values of the TAGE branch predictor match the settings of the
8C-TAGE configuration described in https://www.jilp.org/vol8/v8paper1.pdf

Change-Id: I8323adbfd5c9a45db23cfff234218280e639f9ed
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14435
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agocpu,arch-arm: Initialise data members
Rekai Gonzalez-Alberquilla [Fri, 10 Feb 2017 17:30:22 +0000 (17:30 +0000)]
cpu,arch-arm: Initialise data members

The value that is not initialized has a bogus value that manifests when
using some debug-flags what makes the usage of tracediff a bit more
challenging.

In addition, while debugging with other techniques, it introduces the
problem of understanding if the value of a field is 'intended' or just
an effect of the lack of initialisation.

Change-Id: Ied88caa77479c6f1d5166d80d1a1a057503cb106
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13125
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
6 years agoarch-arm: clang compilation fixes
Matteo Andreozzi [Mon, 26 Feb 2018 16:40:12 +0000 (10:40 -0600)]
arch-arm: clang compilation fixes

Fix 1: std::pair constructor is not a constexpr in clang implementation
Fix 2: static const templates need to be defined in their
       translation unit

Change-Id: I3d9b9b47e1d148e44555f40e2e2aeff06707ff8f
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14617
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

6 years agotests: Convert IniFile unit test to a GTest
Giacomo Travaglini [Thu, 22 Nov 2018 15:09:04 +0000 (15:09 +0000)]
tests: Convert IniFile unit test to a GTest

Change-Id: I47d6c9cbae21877420a15ffcf8489e3c26959139
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14615
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agohsail: Fix a warning/build failure for HSAIL_X86.
Gabe Black [Tue, 27 Nov 2018 03:12:52 +0000 (19:12 -0800)]
hsail: Fix a warning/build failure for HSAIL_X86.

The Bitselect operation definition used ~ to invert the bits of a mask
value, but if that mask value is of type bool, that generates a
warning. This change casts that value to a uint64_t so that it can
always have ~ applied to it.

Change-Id: I7fbfc6ff264bc32a265f2724c772b8fae08590f7
Reviewed-on: https://gem5-review.googlesource.com/c/14655
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agoarch, base, cpu, gpu, mem: Replace assert(0 or false with panic.
Gabe Black [Tue, 27 Nov 2018 01:51:16 +0000 (17:51 -0800)]
arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.

Neither assert(0) nor assert(false) give any hint as to why control
getting to them is bad, and their more descriptive versions,
assert(0 && "description") and assert(false && "description"), jury
rig assert to add an error message when the utility function panic()
already does that directly with better formatting options.

This change replaces that flavor of call to assert with panic, except
in the actual code which processes the formatting that panic uses (to
avoid infinitely recurring error handling), and in some *.sm files
since I don't know what rules those have to follow and don't want to
accidentaly break them.

Change-Id: I8addfbfaf77eaed94ec8191f2ae4efb477cefdd0
Reviewed-on: https://gem5-review.googlesource.com/c/14636
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agosim-se: only implement getdentsFunc on supported hosts
Ciro Santilli [Tue, 20 Nov 2018 16:45:07 +0000 (16:45 +0000)]
sim-se: only implement getdentsFunc on supported hosts

The implementation of the getdents syscall relies on SYS_getdents, which
is not available on all archs, because the getdents syscall has been
superseded by getdents64, and does not exist on newer archs such as
aarch64.

This leads the build to break on aarch64 hosts with error:

error: 'SYS_getdents' was not declared in this scope

Change-Id: I8701fb5b61c0418b14a9463ef135a391a7f7a9ba
Reviewed-on: https://gem5-review.googlesource.com/c/14596
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>

6 years agosystemc: set endianess to fix build for ARM host
Ciro Santilli [Wed, 21 Nov 2018 16:27:28 +0000 (16:27 +0000)]
systemc: set endianess to fix build for ARM host

ARM architectures were not covered in the endianess #if cases, which
lead the build to fail on an arm host with message:

error The file boost/detail/endian.hpp needs to be set up for your CPU
type.

Change-Id: Id012cf37810da113174a51746e290e25138739cb
Reviewed-on: https://gem5-review.googlesource.com/c/14595
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase: Add some functions to convert floats to bits and vice versa.
Gabe Black [Tue, 20 Nov 2018 00:06:03 +0000 (16:06 -0800)]
base: Add some functions to convert floats to bits and vice versa.

These make it easier to extract the binary representation of floats and
doubles, and given a binary representation convert it back again.

The versions with a size prefix are safer to use since they make it
clear what size inputs/outputs are expected. The versions without are
to make writing generic code easier in case the same code snippet,
templated function, etc., needs to be applied in both circumstances.

Change-Id: Ib1f35a7e88e00806a7c639c211c5699b4af5a472
Reviewed-on: https://gem5-review.googlesource.com/c/14455
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agomem-cache: Add setters to validate and secure block
Daniel R. Carvalho [Thu, 25 Oct 2018 15:26:02 +0000 (17:26 +0200)]
mem-cache: Add setters to validate and secure block

In order to allow polymorphism of the block these two
functions have been added, and all direct status
assignments to these bits have been substituted.

We also assert that the block has been invalidated
before insertion. Then the block is validated in
the insertion.

Change-Id: Ie7be42408721ad4c2c9dc880f82a62cb594f8668
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14362
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agocpu: Made LTAGE parameters configurable
Pau Cabre [Sun, 18 Nov 2018 01:40:13 +0000 (02:40 +0100)]
cpu: Made LTAGE parameters configurable

This includes TAGE tag sizes, TAGE table sizes, U counters reset period,
loop predictor associativity, path history size, the USE_ALT_ON_NA size
and the WITHLOOP size

Change-Id: I935823f0a5794f5d55b744263798897a813dc1bd
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14417
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agocpu: Fixed useful counter handling in LTAGE
Pau Cabre [Sat, 17 Nov 2018 22:21:15 +0000 (23:21 +0100)]
cpu: Fixed useful counter handling in LTAGE

Increased to 2 bits of useful counter per TAGE entry as described in the
LTAGE paper (and made the size configurable)

Changed how the useful counters are incremented/decremented as described
in the LTAGE paper

Change-Id: I8c692cc7c180d29897cb77781681ff498a1d16c8
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14215
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agocpu: Fixes on the loop predictor part of LTAGE
Pau Cabre [Sun, 11 Nov 2018 22:43:33 +0000 (23:43 +0100)]
cpu: Fixes on the loop predictor part of LTAGE

Fixed the following fields of the loop predictor entries as described on
the LTAGE paper:
 - Age counter (it was 3 bits and it should be 8 bits)
 - Tag (it was 16 bits and it should be 14 bits). Also some times it used
   int variables and some times uint16_t, leading to wrong behaviour
 - Confidence counter (it was 2 bits ins some parts of the code and 3 bits
   in some other parts. It should be 2 bits)
 - Iteration counters (they were 16 bits and they should be 14 bits)
All the new sizes are now configurable

Change-Id: I8884c7454c1e510b65160eb4d5749d3259d34096
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14216
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agox86: Get rid of a problematic DPRINTF in PremFp.
Gabe Black [Wed, 21 Nov 2018 00:22:26 +0000 (16:22 -0800)]
x86: Get rid of a problematic DPRINTF in PremFp.

This DPRINTF shouldn't be necessary since it shows the operands and
results of the instruction which the trace should already make
available. Also by passing the destination register to DPRINTF, the ISA
parser will assume that it's also a source when tracking dependencies.

Change-Id: I820387c82578bdbb8d2e3d91652a6c0185077f54
Reviewed-on: https://gem5-review.googlesource.com/c/14475
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosim: Deschedule existing events when destructing an event queue.
Gabe Black [Sat, 17 Nov 2018 00:27:58 +0000 (16:27 -0800)]
sim: Deschedule existing events when destructing an event queue.

Other objects in the simulation may try to deschedule their events when
destructed, and if they're cleaned up after the event queue is then
they might try to deschedule events on an event queue that no longer
exists.

Change-Id: I9452ce52fba78297ce3dc4b3884289b5e2f2574d
Reviewed-on: https://gem5-review.googlesource.com/c/14400
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase: Don't let exceptions leak from the to_number utility function.
Gabe Black [Sat, 17 Nov 2018 01:57:41 +0000 (17:57 -0800)]
base: Don't let exceptions leak from the to_number utility function.

This function catches a couple types of exceptions the functions it
calls might throw, but if one that it doesn't catch is thrown, then
it will propogate that exception to its own callers, and not initialize
the value it was asked to convert.

This might be considered desirable behavior since it lets errors
propogate and avoids handling them in code that might not know the
context of when it's called. On the other hand, it upsets g++ since it
thinks that there might be an uninitialized value used elsewhere, even
though that value will only be uninitialized if an exception is
propogating, and the code that would use it is after a point where that
exception would have been caught and execution would have resumed.

To satisfy g++ and to also avoid silently hiding errors, this change
adds a catch all which will panic if an unexpected exception is raised.

Change-Id: Ie94dcef3a50f7902566328a3fa2eac59b3cf9aad
Reviewed-on: https://gem5-review.googlesource.com/c/14399
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agosystemc: Stop explicitly adding the systemc ext dir to CPPPATH.
Gabe Black [Fri, 9 Nov 2018 00:16:10 +0000 (16:16 -0800)]
systemc: Stop explicitly adding the systemc ext dir to CPPPATH.

That's now handled automatically when the native systemc API is
enabled.

Change-Id: If1f88929af335a40554a9fd8df6f68aa1a4c0ba4
Reviewed-on: https://gem5-review.googlesource.com/c/14398
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Put systemc headers in the include path when supported.
Gabe Black [Thu, 8 Nov 2018 23:49:03 +0000 (15:49 -0800)]
systemc: Put systemc headers in the include path when supported.

When the native systemc API support is built in, put the systemc and
systemc.h header files in the include path so they can be used as
normal. We don't want any external systemc headers being included and
getting mixed in with our local ones.

Change-Id: I5fc01ff5f069cfadb7c19a9dead13e7ce7272976
Reviewed-on: https://gem5-review.googlesource.com/c/14397
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agosystemc: Increase the stack size for the sc_main fiber to 8MB.
Gabe Black [Sat, 17 Nov 2018 02:01:30 +0000 (18:01 -0800)]
systemc: Increase the stack size for the sc_main fiber to 8MB.

This is a reasonable size for a stack, and the default size for a stack
on Linux as determined by some quick Googling. The sc_main fiber would
normally use the primary program stack if run under the standard
systemc implementation, and so might expect to have more room to play
with.

Change-Id: Ie12344939e7b249da203630ebc7dc773a387d716
Reviewed-on: https://gem5-review.googlesource.com/c/14396
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agobase: Set up a guard page for fiber stacks.
Gabe Black [Sat, 17 Nov 2018 01:07:42 +0000 (17:07 -0800)]
base: Set up a guard page for fiber stacks.

This will help detect stack overflow for fibers.

Change-Id: Iff2b102120ec351709e495291d6bead597f8d10c
Reviewed-on: https://gem5-review.googlesource.com/c/14395
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agomem-cache: a missing cast was truncating addresses
Javier Bueno [Sat, 17 Nov 2018 23:59:09 +0000 (00:59 +0100)]
mem-cache: a missing cast was truncating addresses

High bits were truncated when computing the block address

Change-Id: Iab2a4c6063ece2d1d4c24ce5686045a6d6d35434
Reviewed-on: https://gem5-review.googlesource.com/c/14415
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agocpu: Fix LTAGE max number of allocations on update
Pau Cabre [Fri, 9 Nov 2018 23:12:30 +0000 (00:12 +0100)]
cpu: Fix LTAGE max number of allocations on update

The LTAGE paper states that only one TAGE entry can be
allocated when updating

Change-Id: I6cfb4d80ce835e93d4bf5099ef88a7d425abaddd
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14195
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agoconfigs: Added an option for choosing branch predictor type
Pau Cabre [Wed, 7 Nov 2018 22:22:05 +0000 (23:22 +0100)]
configs: Added an option for choosing branch predictor type

Added the parameter "--bp-type" to set the branch predictor type
Added the parameter "--list-bp-types" to list all the available branch
predictor types

Change-Id: Ia6aae90c784aef359b6d8233c8383cd7a871aca1
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14015
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agosim: Fix data type of ticks per second before passing it to C++
Srikant Bharadwaj [Fri, 16 Nov 2018 19:24:43 +0000 (14:24 -0500)]
sim: Fix data type of ticks per second before passing it to C++

Casts ticks per second value to int before passing it to C++. Python
throws an error because of incompatible type because of the recent
change.

Change-Id: Ibcaf8c327f1be0dba38763975d389584addd8373
Reviewed-on: https://gem5-review.googlesource.com/c/14375
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agomem: avoid calling regStat twice on a QoSPolicy
Matteo Andreozzi [Wed, 7 Sep 2016 13:04:45 +0000 (14:04 +0100)]
mem: avoid calling regStat twice on a QoSPolicy

Change-Id: I216c57073fabe29c3f898a5d89cee41efd4277d5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13696
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agocpu: Fix the usage of const DynInstPtr
Rekai Gonzalez-Alberquilla [Mon, 6 Feb 2017 11:10:06 +0000 (11:10 +0000)]
cpu: Fix the usage of const DynInstPtr

Summary: Usage of const DynInstPtr& when possible and introduction of
move operators to RefCountingPtr.

In many places, scoped references to dynamic instructions do a copy of
the DynInstPtr when a reference would do. This is detrimental to
performance. On top of that, in case there is a need for reference
tracking for debugging, the redundant copies make the process much more
painful than it already is.

Also, from the theoretical point of view, a function/method that
defines a convenience name to access an instruction should not be
considered an owner of the data, i.e., doing a copy and not a reference
is not justified.

On a related topic, C++11 introduces move semantics, and those are
useful when, for example, there is a class modelling a HW structure that
contains a list, and has a getHeadOfList function, to prevent doing a
copy to an internal variable -> update pointer, remove from the list ->
update pointer, return value making a copy to the assined variable ->
update pointer, destroy the returned value -> update pointer.

Change-Id: I3bb46c20ef23b6873b469fd22befb251ac44d2f6
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13105
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

6 years agomem-cache: fix invalid iterator access
Javier Bueno [Thu, 15 Nov 2018 15:19:45 +0000 (16:19 +0100)]
mem-cache: fix invalid iterator access

An iterator was assigned end() and then it was used to access
its corresponding element.

Change-Id: I87246cf56cbc694dd6b4e2cabbe84a08429d2ac3
Reviewed-on: https://gem5-review.googlesource.com/c/14361
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agomem-cache: Make StridePrefetcher use Replacement Policies
Daniel [Sun, 11 Nov 2018 14:52:08 +0000 (15:52 +0100)]
mem-cache: Make StridePrefetcher use Replacement Policies

Previously StridePrefetcher was only able to use random
replacement policy. This change allows all replacement
policies to be applied to the pc table.

Change-Id: I8714e71a6a4c9c31fbca49a07a456dcacd3e402c
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14360
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agomem-cache: Add invalidation function to StrideEntry
Daniel [Sun, 11 Nov 2018 16:56:08 +0000 (17:56 +0100)]
mem-cache: Add invalidation function to StrideEntry

Add invalidation function to StrideEntry so that every
entry can be invalidated appropriately.

Change-Id: I38c42b7d7c93d839f797d116f1d2c88572123c0e
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14359
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agomem-cache: Make PCTable context independent
Daniel [Sun, 11 Nov 2018 15:11:40 +0000 (16:11 +0100)]
mem-cache: Make PCTable context independent

Move the unordered_map outside of the PCTable, as it
belongs to the StridePrefetcher. By doing so we are
moving towards a table that ressembles the ones of
the Tags classes.

Some functions have been moved from the prefetcher to
the PCTable, as they didn't belong there. As such, they
have been renamed to remove the unnecessary prefix.

Change-Id: I3e54bc7dee65e1f78d96b0d548ac8345b7bd4364
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14358
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agomem-cache: Vectorize StridePrefetcher's entries.
Daniel [Tue, 13 Nov 2018 19:47:51 +0000 (20:47 +0100)]
mem-cache: Vectorize StridePrefetcher's entries.

Turn StridePrefetcher::PCTable::entries into a vector of vectors.

Change-Id: I2a4589a76eb205910c43723638b7989eddd5ca24
Reviewed-on: https://gem5-review.googlesource.com/c/14357
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agomem-cache: Return entry in StridePrefetcher::pcTableHit()
Daniel [Tue, 13 Nov 2018 19:59:50 +0000 (20:59 +0100)]
mem-cache: Return entry in StridePrefetcher::pcTableHit()

Return a pointer to the entry instead of returning a
boolean and passing a pointer reference. As a side
effect, change the name of the function to be more
descriptive of the functionality.

Change-Id: Iad44979e98031754c1d0857b1790c0eaf77e9765
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14356
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agomem-cache: Cleanup prefetchers
Daniel [Sun, 11 Nov 2018 10:55:37 +0000 (11:55 +0100)]
mem-cache: Cleanup prefetchers

Prefetcher code had extra variables, dependencies
that could be removed, code duplication, and missing
overrides.

Change-Id: I6e9fbf67a0bdab7eb591893039e088261f52d31a
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14355
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agoscons: add --gold-linker to link with the gold linker
Ciro Santilli [Wed, 7 Nov 2018 00:00:00 +0000 (00:00 +0000)]
scons: add --gold-linker to link with the gold linker

This option can significantly speedup link time on Linux systems, which is
the main bottleneck to rebuild after small changes.

Change-Id: I3b0bdd61f7dcef0d73629c8ee2ee98091953fec3
Reviewed-on: https://gem5-review.googlesource.com/c/14075
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>

6 years agocpu: Fixed ratio of pred to hyst bits for LTAGE Bimodal
Pau Cabre [Thu, 8 Nov 2018 23:30:15 +0000 (00:30 +0100)]
cpu: Fixed ratio of pred to hyst bits for LTAGE Bimodal

The LTAGE paper states 1 hyst bit shared for 4 pred bits.
Made this ratio configurable use 4 by default.
Also changed the Bimodal structure to use two std::vector<bool> (one for
pred and one for hyst bits)

Change-Id: I6793e8e358be01b75b8fd181ddad50f259862d79
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14120
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

6 years agomem-cache: Remove Cache dependency from Tags
Daniel R. Carvalho [Wed, 14 Nov 2018 11:04:38 +0000 (12:04 +0100)]
mem-cache: Remove Cache dependency from Tags

Tags do not need to be aware of caches.

Change-Id: Ib6a082b74dcd9b2f10852651634b59512732fb2a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14296
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agomem-cache: Move access latency calculation to Cache
Daniel R. Carvalho [Thu, 18 Oct 2018 13:31:51 +0000 (15:31 +0200)]
mem-cache: Move access latency calculation to Cache

Access latency was not being calculated properly, as it was
always assuming that for hits reads take as long as writes,
and that parallel accesses would produce the same latency
for read and write misses.

By moving the calculation to the Cache we can use the write/
read information, reduce latency variables duplication and
remove Cache dependency from Tags.

The tag lookup latency is still calculated by the Tags.

Change-Id: I71bc68fb5c3515b372c3bf002d61b6f048a45540
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/13697
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

6 years agoarch-arm: Print register name when warning on AT instructions
Giacomo Travaglini [Mon, 12 Nov 2018 16:46:52 +0000 (16:46 +0000)]
arch-arm: Print register name when warning on AT instructions

With this patch we don't print anymore the enum value when warning
on any AT instruction usage, but we print the sys reg name instead

Change-Id: Ic6831b98ad6b0582be69883dc9519a9d3324da30
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/14316
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>