Gabe Black [Sat, 12 Aug 2006 00:29:15 +0000 (20:29 -0400)]
Started to add support for O3 for sparc.
--HG--
extra : convert_revision :
3f94bda14024a09b9fbd7a5d13284d4987349ddf
Gabe Black [Sat, 12 Aug 2006 00:28:35 +0000 (20:28 -0400)]
Changed the compiler guards to say SPARC
--HG--
extra : convert_revision :
e79964148c7fb7075627f46add6687f6cd0ee241
Gabe Black [Sat, 12 Aug 2006 00:27:22 +0000 (20:27 -0400)]
Added code to support setting up all of the auxillieary vectors configured by the sparc linux elf loader.
src/arch/sparc/process.cc:
All of the auxilliary vectors are now set like they are in the linux elf loader. This code should probably be moved to arch/sparc/linux/process.cc somehow.
--HG--
extra : convert_revision :
4a90cacf70b1032cad3f18b0f833a6df8237e0de
Gabe Black [Sat, 12 Aug 2006 00:23:31 +0000 (20:23 -0400)]
#include of iostream needed.
--HG--
extra : convert_revision :
d31bb943ab25103cf715159054df318a5b88abc9
Gabe Black [Sat, 12 Aug 2006 00:22:36 +0000 (20:22 -0400)]
Adjusted the decoder a little.
--HG--
extra : convert_revision :
5bdbe00342837ae4caacb3ad86c7becca36ba6ce
Gabe Black [Sat, 12 Aug 2006 00:21:35 +0000 (20:21 -0400)]
Started adding a system to output data after every instruction.
src/arch/alpha/regfile.hh:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/cpu/exetrace.hh:
Added functions to start to support dumping register values once per cycle.
src/cpu/exetrace.cc:
Added some code to support printing the value of registers after each cycle.
src/python/m5/main.py:
Options to turn on output after every instruction. They are commented out.
--HG--
extra : convert_revision :
168a48a6b98ab6be412a96bdee831c71906958b0
Gabe Black [Fri, 11 Aug 2006 23:43:10 +0000 (19:43 -0400)]
Pushed most of constants.hh back into isa_traits.hh and regfile.hh and created a seperate file for the syscallreturn class.
--HG--
extra : convert_revision :
9507ea1c09fda959f00aec9ec8ffb887ec8dd0f9
Korey Sewell [Fri, 11 Aug 2006 22:42:43 +0000 (18:42 -0400)]
make test3.py usable again ... I guess I should fix up test4 and test5 too???
Also, What happened to the "lets make real names for these tests" thing we
were talking about? Is test1 - test(n) OK now?
--HG--
extra : convert_revision :
60716e41ecc79a78241be383ab3cae4b9e382335
Korey Sewell [Fri, 11 Aug 2006 00:51:43 +0000 (20:51 -0400)]
really confused about this license but OK...
--HG--
extra : convert_revision :
85e40593e344b9eff325061630db27d178937258
Kevin Lim [Thu, 27 Jul 2006 21:49:00 +0000 (17:49 -0400)]
Clean up some more config stuff.
configs/common/FSConfig.py:
Clean up some code to make functions look less like classes. Also put makeList function (formerly listWrapper) into m5 itself.
configs/test/fs.py:
Update for changed code.
src/python/m5/__init__.py:
Put makeList into m5.
--HG--
extra : convert_revision :
731806a7486f9abf986f52926126df666b024b1d
Kevin Lim [Thu, 27 Jul 2006 21:47:43 +0000 (17:47 -0400)]
Update ref stats.
tests/test1/ref/alpha/atomic/stdout:
tests/test1/ref/alpha/detailed/stderr:
tests/test1/ref/alpha/detailed/stdout:
tests/test1/ref/alpha/timing/stdout:
Updated output.
--HG--
extra : convert_revision :
3189564725ac4d2b3d63e6a71151a52326f8d416
Kevin Lim [Thu, 27 Jul 2006 21:37:28 +0000 (17:37 -0400)]
Output the command line.
src/python/m5/main.py:
Output the command line being used.
--HG--
extra : convert_revision :
51dadb0ef79ca1e8bbb5a3bd64110071c30ade0d
Kevin Lim [Thu, 27 Jul 2006 20:43:29 +0000 (16:43 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
70221af596bddbfcc40646d03f175ef5e4b75909
Kevin Lim [Thu, 27 Jul 2006 20:43:02 +0000 (16:43 -0400)]
Need config read/write latency.
--HG--
extra : convert_revision :
2d978635db89e727f228890738b24fcad9b6ced6
Korey Sewell [Wed, 26 Jul 2006 22:47:06 +0000 (18:47 -0400)]
MIPS ISA runs 'hello world' in O3CPU ...
src/arch/mips/isa/base.isa:
special case syscall disasembly... maybe give own instruction class?
src/arch/mips/isa/decoder.isa:
add 'IsSerializeAfter' flag for syscall
src/cpu/o3/commit.hh:
Add skidBuffer to commit
src/cpu/o3/commit_impl.hh:
Use skidbuffer in MIPS ISA
src/cpu/o3/fetch_impl.hh:
Print name out when there is a fault
src/cpu/o3/mips/cpu_impl.hh:
change comment
--HG--
extra : convert_revision :
d032549e07102bdd50aa09f044fce8de6f0239b5
Gabe Black [Wed, 26 Jul 2006 07:48:48 +0000 (03:48 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision :
3bb2cdd9b286e7f0235fb5fd5099b89775e05a10
Gabe Black [Wed, 26 Jul 2006 07:42:16 +0000 (03:42 -0400)]
Added alot of fp instructions, and some impdep instructions.
--HG--
extra : convert_revision :
cc703919b59e674044ae370a65dc03deece6d69e
Gabe Black [Wed, 26 Jul 2006 07:40:56 +0000 (03:40 -0400)]
Now ignore sigaction
src/arch/sparc/isa/operands.isa:
Added the GSR register as a control register
--HG--
extra : convert_revision :
11ff4016d5c72468dd2daeba3a6105d4e84220ce
Korey Sewell [Sun, 23 Jul 2006 17:41:53 +0000 (13:41 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision :
be1e5dcb1c5025db8526e628c2060b1790d38227
Korey Sewell [Sun, 23 Jul 2006 17:39:42 +0000 (13:39 -0400)]
This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds, runs, and gets very very close to completing the hello world
succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh!
Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS
ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... )
src/arch/alpha/isa/mem.isa:
spacing
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
Gabe really authored this
src/arch/mips/isa/decoder.isa:
add StoreConditional Flag to instruction
src/arch/mips/isa/formats/basic.isa:
Steven really did this file
src/arch/mips/isa/formats/branch.isa:
fix bug for uncond/cond control
src/arch/mips/isa/formats/mem.isa:
Adjust O3CPU memory access to use new memory model interface.
src/arch/mips/isa/formats/util.isa:
update LoadStoreBase template
src/arch/mips/isa_traits.cc:
update SERIALIZE partially
src/arch/mips/process.cc:
src/arch/mips/process.hh:
no need for this for NOW. ASID/Virtual addressing handles it
src/arch/mips/regfile/misc_regfile.hh:
add in clear() function and comments for future usage of special misc. regs
src/cpu/base_dyn_inst.hh:
add in nextNPC variable and supporting functions.
add isCondDelaySlot function
Update predTaken and mispredicted functions
src/cpu/base_dyn_inst_impl.hh:
init nextNPC
src/cpu/o3/SConscript:
add MIPS files to compile
src/cpu/o3/alpha/thread_context.hh:
no need for my name on this file
src/cpu/o3/bpred_unit_impl.hh:
Update RAS appropriately for MIPS
src/cpu/o3/comm.hh:
add some extra communication variables to aid in handling the
delay slots
src/cpu/o3/commit.hh:
minor name fix for nextNPC functions.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
Fix necessary variables and functions for squashes with delay slots
src/cpu/o3/cpu.cc:
Update function interface ...
adjust removeInstsNotInROB function to recognize delay slots insts
src/cpu/o3/cpu.hh:
update removeInstsNotInROB
src/cpu/o3/decode.hh:
declare necessary variables for handling delay slot
src/cpu/o3/dyn_inst.hh:
Add in MipsDynInst
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/rename.hh:
declare necessary variables and adjust functions for handling delay slot
src/cpu/o3/inst_queue.hh:
src/cpu/simple/base.cc:
no need for my name here
src/cpu/o3/isa_specific.hh:
add in MIPS files
src/cpu/o3/scoreboard.hh:
dont include alpha specific isa traits!
src/cpu/o3/thread_context.hh:
no need for my name here, i just rearranged where the file goes
src/cpu/static_inst.hh:
add isCondDelaySlot function
src/cpu/o3/mips/cpu.cc:
src/cpu/o3/mips/cpu.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/mips/dyn_inst.cc:
src/cpu/o3/mips/dyn_inst.hh:
src/cpu/o3/mips/dyn_inst_impl.hh:
src/cpu/o3/mips/impl.hh:
src/cpu/o3/mips/params.hh:
src/cpu/o3/mips/thread_context.cc:
src/cpu/o3/mips/thread_context.hh:
MIPS file for O3CPU...mirrors ALPHA definition
--HG--
extra : convert_revision :
9bb199b4085903e49ffd5a4c8ac44d11460d988c
Gabe Black [Sun, 23 Jul 2006 07:06:12 +0000 (03:06 -0400)]
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision :
f6a68bbf8aad9be54ff24310b3e51eaed9abb8b5
Gabe Black [Sun, 23 Jul 2006 07:04:46 +0000 (03:04 -0400)]
Added myself to the authors list.
--HG--
extra : convert_revision :
d90154159473ed93c5b50cf3221e132eda242852
Kevin Lim [Sun, 23 Jul 2006 04:10:52 +0000 (00:10 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
45650c90385b4e13e79ccf271a30bb55552b380f
Kevin Lim [Sun, 23 Jul 2006 04:10:11 +0000 (00:10 -0400)]
Fix up test.py
configs/test/test.py:
Fix up this config.
--HG--
extra : convert_revision :
e15071ee27b860cc3ad79277aa61f3e6bb7405d3
Gabe Black [Sat, 22 Jul 2006 21:30:50 +0000 (17:30 -0400)]
Reorganized SPARC binaries
--HG--
rename : configs/test/hello_sparc => configs/test/sparc_tests/hello_sparc
extra : convert_revision :
d8f36fc9b346f0e89dc8406403576e88bb2dc139
Gabe Black [Sat, 22 Jul 2006 19:50:40 +0000 (15:50 -0400)]
Fixed subtract with carry, and started some work with floating point.
src/arch/sparc/isa/decoder.isa:
fixed subc, subccc, added decoding for impdep1 to fit with ua2005, and started work on floating point.
src/arch/sparc/isa/operands.isa:
Added in floating point operands, and changed the numbering of operands.
src/arch/sparc/regfile.hh:
Fixed some memory errors related to floating point.
--HG--
extra : convert_revision :
fa0aef2021a5cf99f175fceeb533fe63eb5f805c
Kevin Lim [Sat, 22 Jul 2006 19:50:39 +0000 (15:50 -0400)]
Last minute check in. Very few functional changes other than some minor config updates. Also include some recently generated stats.
SConstruct:
Make test CPUs option non-sticky.
configs/common/FSConfig.py:
Be sure to set the memory mode.
configs/test/fs.py:
Wrong string.
tests/SConscript:
Only test valid CPUs that have been compiled in.
tests/test1/ref/alpha/atomic/config.ini:
tests/test1/ref/alpha/atomic/config.out:
tests/test1/ref/alpha/atomic/m5stats.txt:
tests/test1/ref/alpha/atomic/stdout:
tests/test1/ref/alpha/detailed/config.ini:
tests/test1/ref/alpha/detailed/config.out:
tests/test1/ref/alpha/detailed/m5stats.txt:
tests/test1/ref/alpha/detailed/stdout:
tests/test1/ref/alpha/timing/config.ini:
tests/test1/ref/alpha/timing/config.out:
tests/test1/ref/alpha/timing/m5stats.txt:
tests/test1/ref/alpha/timing/stdout:
Update output.
--HG--
extra : convert_revision :
6eee2a5eae0291b5121b41bcd7021179cdd520a3
Kevin Lim [Fri, 21 Jul 2006 20:08:17 +0000 (16:08 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
configs/test/fs.py:
Hand merge.
--HG--
extra : convert_revision :
78f7c46084f66d52ddfe0386fd7c08de8017331e
Kevin Lim [Fri, 21 Jul 2006 19:56:35 +0000 (15:56 -0400)]
Rearrange the FS configs to be more shared. Also check in the full-system tests. Reference stats coming soon.
configs/test/fs.py:
Pull out a lot of common code and put it into configs/common/FSConfig.py.
--HG--
extra : convert_revision :
175b18d75f82ddecbcc9a6418fe40df314db55d5
Kevin Lim [Fri, 21 Jul 2006 19:53:07 +0000 (15:53 -0400)]
Missed some files in a previous check-in. Also check-in the SMT tests. Reference stats will be coming soon.
--HG--
extra : convert_revision :
c2f7ea613f350e62395f2b50e4c8cc21c6960a22
Kevin Lim [Fri, 21 Jul 2006 19:46:12 +0000 (15:46 -0400)]
Minor functionality updates.
SConstruct:
Include an option to specify the CPUs being tested.
src/cpu/SConscript:
Checker isn't SMT right now, so don't do SMT tests with the O3CPU if we're using the checker.
src/python/m5/objects/O3CPU.py:
Include default options. Unfortunately FullO3Config.py is still needed because it specifies which FUPool is being used.
tests/SConscript:
Several minor updates (sorry for one commit). Updated the copyright and fixed some m5 style issues. Also added the ability to specify which CPUs to run the tests on.
--HG--
extra : convert_revision :
b0b801115705544ea02e572e31314f7bb8b5f0f2
Kevin Lim [Fri, 21 Jul 2006 19:42:44 +0000 (15:42 -0400)]
Some reorganization. Options are all handled at the user level script. Move createCpus function (now called connectCpu) to Util.py, where it can be used by other configs.
--HG--
rename : configs/test/SysPaths.py => configs/common/SysPaths.py
extra : convert_revision :
2b1b95c5f29e7ade08b1abd6f24c129d600fe2e8
Gabe Black [Fri, 21 Jul 2006 01:01:57 +0000 (21:01 -0400)]
Fixed a glitch in the disassembly output.
--HG--
extra : convert_revision :
833aa358b12ac987e0ab467708425c17e5a8fdb7
Gabe Black [Thu, 20 Jul 2006 23:04:09 +0000 (19:04 -0400)]
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision :
0c696374b19b27c0bd50ffa7f75117b1e211e4bc
Ali Saidi [Thu, 20 Jul 2006 23:04:08 +0000 (19:04 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
c7fedc68996f2f6cbfb70baebf7c87e0736da883
Ali Saidi [Thu, 20 Jul 2006 23:03:47 +0000 (19:03 -0400)]
Move PioPort timing code into Simple Timing Port object
Make PioPort use it
Make Physical memory use it as well
src/SConscript:
Add timing port to sconscript
src/dev/io_device.cc:
src/dev/io_device.hh:
Move simple timing pio port stuff into a simple timing port class so it can be used by the physical memory
src/mem/physical.cc:
src/mem/physical.hh:
use a simple timing port stuff instead of rolling our own here
--HG--
extra : convert_revision :
e5befbd295a572568cfdca533efb5ed1984c59d1
Ali Saidi [Thu, 20 Jul 2006 23:00:40 +0000 (19:00 -0400)]
Enforce the timing cpu ticking at it's clock rate
Add a max time option in seconds and a single system root clock be 1THz
configs/test/fs.py:
Add a max time option in seconds and a single system root clock be 1THz
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Enforce the timing cpu ticking at it's clock rate
--HG--
extra : convert_revision :
a1b0de27abde867f9c3da5bec11639e3d82a95f5
Ali Saidi [Wed, 19 Jul 2006 21:59:04 +0000 (17:59 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem.head
--HG--
extra : convert_revision :
8c747208d72ffbb0160a2ad4a75383420debdf83
Ali Saidi [Wed, 19 Jul 2006 21:24:45 +0000 (17:24 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
--HG--
extra : convert_revision :
c5dbee4ba46fae1edba732f4bd05ef984a46d088
Ali Saidi [Wed, 19 Jul 2006 21:24:20 +0000 (17:24 -0400)]
Change the device latency here to a latency rather than a Tick
src/python/m5/objects/Device.py:
src/python/m5/objects/Pci.py:
Change the default here to a latency rather than a Tick
--HG--
extra : convert_revision :
b9366dd89646cea27a836baf249ac2da38c1809f
Kevin Lim [Wed, 19 Jul 2006 20:09:34 +0000 (16:09 -0400)]
Minor changes to reflect state used for regression stats.
src/cpu/checker/cpu.hh:
Don't count checker's instructions towards total instructions committed.
src/python/m5/objects/Root.py:
Set default clock to 1 THz.
--HG--
extra : convert_revision :
0b5eaa197c860c361a3b00087e45ddc249ff1918
Kevin Lim [Wed, 19 Jul 2006 20:07:25 +0000 (16:07 -0400)]
Put regression tests back into m5. They are located in the "tests" directory. The directory output and reference outputs have changed slightly. Now the directory is ALPHA_SE/test/<test>/<cpu_model>/, and for the reference stats <test>/ref/<arch>/<cpu_model>
Right now only non-SMT SE regression tests have been added back in. The rest are pending getting SMT working, and consolidating the FS configuration files.
Eventually support for different OSs can be added so you can specify which versions of the binary you want to run from one config file.
Note: mp-test1 doesn't have any reference stats because MP mode doesn't currently work. The test itself should probably work once the code is fixed.
SConstruct:
Updates to allow for regression tests to work via the command line "scons build/ALPHA_SE/test/debug/quick" and such once again.
src/cpu/SConscript:
Keep a list of SMT supporting CPUs so that the regression tests can easily specify which CPUs to use if they are SMT only.
--HG--
extra : convert_revision :
34e6286150aae8f316ae694f6c00be8f510522f2
Kevin Lim [Wed, 19 Jul 2006 19:28:53 +0000 (15:28 -0400)]
Get the path to load the ini file from. I'm not sure if this fix is needed in other places as well.
src/sim/main.cc:
Get the path to load the ini file from.
--HG--
extra : convert_revision :
aa38fc9b1bc99cd74d095cbfc67253e4549f91d3
Kevin Lim [Wed, 19 Jul 2006 19:28:02 +0000 (15:28 -0400)]
O3CPU fixes.
src/cpu/o3/lsq_unit.hh:
LSQ needs to decrement the WB counter if the load is going to be replayed.
src/cpu/o3/lsq_unit_impl.hh:
LSQ needs to decrement the WB counter if the load is squashed.
--HG--
extra : convert_revision :
20a10baf0d6ab46065e561ddba231251865ebdbd
Kevin Lim [Wed, 19 Jul 2006 19:26:48 +0000 (15:26 -0400)]
Some minor compiling fixes.
src/cpu/o3/iew.hh:
Non-debug compile fixes.
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
Merge fix.
--HG--
extra : convert_revision :
38081925d2b74d8f64acdb65dba94b2bf465b16a
Kevin Lim [Wed, 19 Jul 2006 19:24:22 +0000 (15:24 -0400)]
Update configs.
configs/test/test.py:
Update for changes to SEConfig.
--HG--
extra : convert_revision :
a089a7db4035889db01d543d9a18ea6526f832ca
Kevin Lim [Wed, 19 Jul 2006 18:46:05 +0000 (14:46 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
06cb509fbbce882793997db275ff7c54058ae619
Gabe Black [Wed, 19 Jul 2006 06:07:00 +0000 (02:07 -0400)]
Cleaned things up a little.
--HG--
extra : convert_revision :
7091b0d02e5b7c80be43b5ab1ac003dc89c4c136
Gabe Black [Tue, 18 Jul 2006 22:23:23 +0000 (18:23 -0400)]
Merge m5.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmem
--HG--
extra : convert_revision :
516c357f98c7a571c70362babd3fa162fbc2ed5a
Korey Sewell [Mon, 17 Jul 2006 20:50:20 +0000 (16:50 -0400)]
update test3
--HG--
extra : convert_revision :
e41feeee87d1da348604a37f7349900dcbd3a4d9
Kevin Lim [Fri, 14 Jul 2006 21:54:43 +0000 (17:54 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
configs/test/fs.py:
configs/test/test.py:
SCCS merged
--HG--
extra : convert_revision :
7b2dbcd5881fac01dec38001c4131e73b5be52b5
Kevin Lim [Fri, 14 Jul 2006 21:53:16 +0000 (17:53 -0400)]
Minor updates.
src/python/m5/config.py:
Formatting.
src/python/m5/main.py:
Slightly more useful output when you don't enter in a valid script file.
--HG--
extra : convert_revision :
5a71a6c94dbedeb000f83f57b0b575c2df924509
Kevin Lim [Fri, 14 Jul 2006 21:51:29 +0000 (17:51 -0400)]
Fix the CheckerCPU being included via python.
src/arch/SConscript:
Fixes for including the CheckerCPU if it's specified via command line. Previously the env variable was actually being modified.
src/cpu/SConscript:
Copy the CPU_MODELS from the env, don't create a proxy to it.
--HG--
extra : convert_revision :
7d069bd93a6834ccaa1c378b2bc76dce76745c19
Korey Sewell [Fri, 14 Jul 2006 17:22:35 +0000 (13:22 -0400)]
forgot tid
--HG--
extra : convert_revision :
272ef8f9cd0802770edc4dcef2c26dc44de71e47
Korey Sewell [Fri, 14 Jul 2006 17:06:37 +0000 (13:06 -0400)]
For now, halt context is the same as deallocating.
suspend context will now take the thread off the activeThread list.
src/arch/mips/isa_traits.cc:
add in copy MiscRegs unimplemented function
--HG--
extra : convert_revision :
3ed5320b3786f84d4bb242e3a32b6f415339c3ba
Korey Sewell [Fri, 14 Jul 2006 08:52:08 +0000 (04:52 -0400)]
MIPS specific fixes ... the main thing is that SMT threads get their own stack space instead of all stacks start to space
src/arch/mips/isa_traits.hh:
MaxAddr is defined in config.py now
src/arch/mips/process.cc:
adjust process so SMT threads get their own stack space
src/arch/mips/process.hh:
add stack_start static variable
--HG--
extra : convert_revision :
73fdf3da9831d86536651835d209806c7f0d59da
Ali Saidi [Thu, 13 Jul 2006 19:50:09 +0000 (15:50 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
src/python/m5/main.py:
merge two help fixes
--HG--
extra : convert_revision :
b5c4a88bb84b726bebd3e357a4ef29acc0d95600
Ali Saidi [Thu, 13 Jul 2006 19:48:41 +0000 (15:48 -0400)]
fix help when no arguments are passed to m5
--HG--
extra : convert_revision :
ee6614166fd5814654309298abe5a706ff02c4c2
Ali Saidi [Thu, 13 Jul 2006 19:48:17 +0000 (15:48 -0400)]
add system.mem_mode = ['timing', 'atomic']
update scripts acordingly
configs/test/SysPaths.py:
new syspaths from nate, this one allows you to set script, binary, and disk paths like
system.dir = 'aouaou' in your script
configs/test/fs.py:
update for system mem_mode
Put small checkpoint example
Make clock 1THz
configs/test/test.py:
src/arch/alpha/freebsd/system.cc:
src/arch/alpha/linux/system.cc:
src/arch/alpha/system.cc:
src/arch/alpha/tru64/system.cc:
src/arch/sparc/system.cc:
src/python/m5/objects/System.py:
src/sim/system.cc:
src/sim/system.hh:
update for system mem_mode
src/dev/io_device.cc:
Use time returned from sendAtomic to delay
--HG--
extra : convert_revision :
67eedb3c84ab2584613faf88a534e793926fc92f
Kevin Lim [Thu, 13 Jul 2006 17:12:51 +0000 (13:12 -0400)]
Move Dcache port creation from LSQUnit to LSQ in order to support Ron's recent changes, and using the O3CPU in SMT mode.
src/cpu/o3/lsq.hh:
Update to have LSQ work with only one dcache port for all LSQ Units. LSQ has the dcache port, and the LSQ Units must tell the LSQ if the cache has become blocked.
src/cpu/o3/lsq_impl.hh:
Updates to have the LSQ work with only one dcache port for all LSQUnits.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
Update for LSQ to create dcache port instead of LSQUnits. Now LSQUnits are given the dcache port from the LSQ, and also must check the LSQ if the cache is blocked prior to accessing the cache.
--HG--
extra : convert_revision :
2708adbf323f4e7647dc0c1e31ef5bb4596b89f8
Kevin Lim [Thu, 13 Jul 2006 17:09:29 +0000 (13:09 -0400)]
Fix for bug when squashing and the fetching. Now fetch checks if the cache data is valid.
--HG--
extra : convert_revision :
07b8eda3e90bbbb3ed470c8cc3cf1b63371ab529
Kevin Lim [Thu, 13 Jul 2006 17:08:58 +0000 (13:08 -0400)]
Update for changes to draining.
--HG--
extra : convert_revision :
5038dd8be72827f40cf89318db0b2bb4f9bbd864
Kevin Lim [Thu, 13 Jul 2006 16:21:21 +0000 (12:21 -0400)]
Fix help message printing. Might need to clean up the handling of the sys.exit() call, as right now it prints out "None" at the end (not sure why).
src/python/m5/main.py:
Fix help message printing.
--HG--
extra : convert_revision :
6906234101eb7ff7df7933e9aede0362b5a991bd
Ali Saidi [Thu, 13 Jul 2006 00:22:07 +0000 (20:22 -0400)]
memory mode information now contained in system object
States are now running, draining, or drained. memory state information moved into system object
system parameter is not fs only for cpus
Implement drain() support in devices
Update for drain() call that returns number of times drain_event->process() will be called
Break O3 CPU! No sense in putting in a hack change that kevin is going to remove in a few minutes i imagine
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
Since se mode has a system, allow access to it
Verify that the atomic cpu is connected to an atomic system on resume
src/cpu/simple/base.cc:
Since se mode has a system, allow access to it
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
Update for new drain() call that returns number of times drain_event->process() will be called and memory state being moved into the system
Since se mode has a system, allow access to it
Verify that the timing cpu is connected to an timing system on resume
src/dev/ide_disk.cc:
src/dev/io_device.cc:
src/dev/io_device.hh:
src/dev/ns_gige.cc:
src/dev/ns_gige.hh:
src/dev/pcidev.cc:
src/dev/pcidev.hh:
src/dev/sinic.cc:
src/dev/sinic.hh:
Implement drain() support in devices
src/python/m5/config.py:
Allow drain to return number of times drain_event->process() will be called. Normally 0 or 1 but things like O3 cpu or devices with multiple ports may want to call it many times
src/python/m5/objects/BaseCPU.py:
move system parameter out of fs to everyone
src/sim/sim_object.cc:
src/sim/sim_object.hh:
States are now running, draining, or drained. memory state information moved into system object
src/sim/system.cc:
src/sim/system.hh:
memory mode information now contained in system object
--HG--
extra : convert_revision :
1389c77e66ee6d9710bf77b4306fb47e107b21cf
Kevin Lim [Wed, 12 Jul 2006 21:21:25 +0000 (17:21 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
configs/test/test.py:
Hand merge.
--HG--
extra : convert_revision :
e3fce9cf50a65a9400cd3ec887b13e4765274ec2
Kevin Lim [Wed, 12 Jul 2006 21:20:01 +0000 (17:20 -0400)]
Be sure to include the EIO sources as well so we can run regression tests.
src/SConscript:
It's no longer "ALPHA_ISA". I don't think we meant to leave out the EIO sources.
--HG--
extra : convert_revision :
1ca63ffb571d9021f1ced0bf0df1816b0b798edc
Kevin Lim [Wed, 12 Jul 2006 21:18:34 +0000 (17:18 -0400)]
Serialization changes to make O3CPU consistent with the other models.
src/cpu/o3/commit_impl.hh:
Always set instruction. This is necessary for serialization as the instruction is also serialized.
src/cpu/o3/cpu.cc:
Change serialization so it matches other CPU's output. Also fix up some indexing.
--HG--
extra : convert_revision :
52f6e183132d177bed6e29dd7cf0c10aed6d8534
Kevin Lim [Wed, 12 Jul 2006 21:17:17 +0000 (17:17 -0400)]
Initial try of consolidating configuration files so they can be shared more easily, especially across regression tests and simple examples.
configs/test/fs.py:
Pull a lot of the default options out of the config file now that they are in the Python objects themselves. Also merge this file with the single_fs.py, allowing one file to be used for both. Previously they differed only by the system they instantiated.
configs/test/test.py:
Initial stab at consolidating configuration files so they aren't redundant between the regression tests and the simple examples.
--HG--
extra : convert_revision :
e8ae3de5a6d8864831f21089d4fdb8ec690e4731
Kevin Lim [Wed, 12 Jul 2006 21:16:00 +0000 (17:16 -0400)]
Push more default options to the Python object level as they are rarely changed. These are the changes that Steve was working on.
src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/Tsunami.py:
Push more default options to the Python object level as they are rarely changed.
--HG--
extra : convert_revision :
963eb7a34cd04529b3c5f24b92904ab725c93efb
Kevin Lim [Wed, 12 Jul 2006 21:11:57 +0000 (17:11 -0400)]
Updates for serialization. As long as the tickEvent doesn't need to be serialized (I don't believe it does because we drain all CPUs prior to checkpointing), it should be feasible to start up from other CPU's checkpoints.
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.cc:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
Updates for serialization.
--HG--
extra : convert_revision :
0f150de75d4bc833e4c9b83568e7fd22688d5727
Kevin Lim [Wed, 12 Jul 2006 19:25:34 +0000 (15:25 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
src/cpu/o3/fetch_impl.hh:
Hand merge.
--HG--
extra : convert_revision :
820dab2bc921cbadecaca51cd069327f984f5c74
Kevin Lim [Wed, 12 Jul 2006 19:24:27 +0000 (15:24 -0400)]
Track the PC of the cache data stored in fetch so it doesn't access memory multiple times if information is already in fetch.
--HG--
extra : convert_revision :
00b160b255e998cf99286bcc21894110c7642624
Nathan Binkert [Wed, 12 Jul 2006 19:21:23 +0000 (15:21 -0400)]
Add --pdb
src/python/m5/main.py:
Add a command line option to invoke pdb on your script
--HG--
extra : convert_revision :
ef5a2860bd3f6e479fa80eccaae0cb5541a20b50
Nathan Binkert [Wed, 12 Jul 2006 19:19:08 +0000 (15:19 -0400)]
Merge m5.eecs.umich.edu:/bk/newmem
into iceaxe.:/Volumes/work/research/m5/current
--HG--
extra : convert_revision :
842a23da034c40c75364b76ca75de076da776ac6
Nathan Binkert [Wed, 12 Jul 2006 19:18:49 +0000 (15:18 -0400)]
Fix __file__ for scripts
src/python/m5/main.py:
set __file__ to the script, not the m5 binary.
--HG--
extra : convert_revision :
a0bbd059d2fd321ae8ff68225abc8a7bb5c410ed
Ron Dreslinski [Tue, 11 Jul 2006 20:03:42 +0000 (16:03 -0400)]
Add a cache version of FS (should really make this an option in original)
Now to work on caches in FS, first steps:
1) LL/SC support (Top Level Cache Hooks)
2) Snooping in the bus (CSHR's for DMA Invalidates)
--HG--
extra : convert_revision :
b4e7984712f7dcd42649070c5ca538c87461e179
Ron Dreslinski [Tue, 11 Jul 2006 19:42:49 +0000 (15:42 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem
--HG--
extra : convert_revision :
3be1aa4892aa8bbd458bdc5538bbcbd6c1ebe299
Ron Dreslinski [Tue, 11 Jul 2006 19:42:31 +0000 (15:42 -0400)]
Fix ordering issue with squashed Icache Fetches and Static data in packet.
Now hello world works with 2 levels of cache with O3 CPU(multiple outstanding requests).
src/cpu/o3/fetch_impl.hh:
Fix ordering issue with squashed Icache Fetches and Static data in packet.
--HG--
extra : convert_revision :
a6adb87540b007ead0b4982cb3f31da8199fb5ca
Kevin Lim [Tue, 11 Jul 2006 17:43:30 +0000 (13:43 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
--HG--
extra : convert_revision :
c565fd7cebaa4058ba510b3db50a9c76bf301228
Nathan Binkert [Tue, 11 Jul 2006 15:28:59 +0000 (11:28 -0400)]
Fix option parsing.
src/python/m5/main.py:
Don't allow interspersed arguments, it messes things up
--HG--
extra : convert_revision :
8f1bcf4391f570741d92bf5420879862a48f6016
Nathan Binkert [Tue, 11 Jul 2006 03:00:13 +0000 (23:00 -0400)]
Migrate most of main() and and all option parsing to python
configs/test/fs.py:
configs/test/test.py:
update for the new way that m5 deals with options
src/python/SConscript:
Compile AUTHORS, LICENSE, README, and RELEASE_NOTES into the
python stuff.
src/python/m5/__init__.py:
redo the way options work.
Move them all to main.py
src/sim/main.cc:
Migrate more functionality for main() into python.
Namely option parsing
src/python/m5/attrdict.py:
A dictionary object that overrides attribute access to
do item access.
src/python/m5/main.py:
The new location for M5's option parsing, and the main()
routine to set up the simulation.
--HG--
extra : convert_revision :
c86b87a9f508bde1994088e23fd470c7753ee4c1
Ron Dreslinski [Mon, 10 Jul 2006 21:19:54 +0000 (17:19 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem
--HG--
extra : convert_revision :
c811eb9eacc480b14862f8074af80c56ec1e07f1
Ron Dreslinski [Mon, 10 Jul 2006 21:16:15 +0000 (17:16 -0400)]
Some fixes so that MSHR's are matched and we don't issue overlapping requests with detailed cpu
src/mem/cache/base_cache.cc:
If we still have outstanding requests, need to schedule event again
src/mem/cache/miss/miss_queue.cc:
Need to use block size so overlapping requests match in the MSHR's
src/mem/cache/miss/mshr.cc:
Actually save the address, otherwise we can't match MSHR's
--HG--
extra : convert_revision :
f0f018b89c2fb99f3ce8d6eafc0712ee8edeeda8
Kevin Lim [Mon, 10 Jul 2006 20:31:42 +0000 (16:31 -0400)]
Minor fixes.
src/cpu/checker/thread_context.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
Change functions to match Korey's changes.
src/cpu/ozone/lw_back_end.hh:
Fix compile error.
--HG--
extra : convert_revision :
fb11ac2d6db3a75c1cdbad2c1c02f921ad7344a6
Kevin Lim [Mon, 10 Jul 2006 19:41:35 +0000 (15:41 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
0e4c7684879b8552908e0b64a00b4824de807244
Kevin Lim [Mon, 10 Jul 2006 19:41:28 +0000 (15:41 -0400)]
Some minor cleanups.
src/cpu/SConscript:
Change the error message to be slightly nicer.
src/cpu/o3/commit.hh:
Remove old code.
src/cpu/o3/commit_impl.hh:
Remove old unused code.
--HG--
extra : convert_revision :
48aa430e1f3554007dd5e4f3d9e89b5e4f124390
Kevin Lim [Mon, 10 Jul 2006 19:40:28 +0000 (15:40 -0400)]
Add parameters for backwards and forwards sizes for time buffers.
src/base/timebuf.hh:
Add a function to return the size of the time buffer.
--HG--
extra : convert_revision :
8ffacd8b9013eb76264df065244e00dc1460efd4
Ron Dreslinski [Mon, 10 Jul 2006 16:42:35 +0000 (12:42 -0400)]
Update config for a system with an L2
--HG--
extra : convert_revision :
c73a532ad6ad8d5115bda81fa778a4b97fbab713
Ron Dreslinski [Mon, 10 Jul 2006 16:35:18 +0000 (12:35 -0400)]
Fix offset calculation. Now L2's work with timing&atomic.
src/mem/packet.hh:
Offset is based on packet, not request.
--HG--
extra : convert_revision :
d85af5838370541328ca35072c612d8198020625
Ron Dreslinski [Mon, 10 Jul 2006 16:07:21 +0000 (12:07 -0400)]
Update FS configs to use cpu connectors for ports
--HG--
extra : convert_revision :
1e2e503401f92c1f30e2e487d7aeed1c7c5b7ee4
Ron Dreslinski [Mon, 10 Jul 2006 16:03:13 +0000 (12:03 -0400)]
Fix cpu in full system to match SE.
--HG--
extra : convert_revision :
95e422221ff5bab6104925d50a8882d31729b0f5
Korey Sewell [Fri, 7 Jul 2006 23:02:12 +0000 (19:02 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision :
9098d989832e2a5818b80771e3c02170c5c8cd5b
Kevin Lim [Fri, 7 Jul 2006 22:24:13 +0000 (18:24 -0400)]
Support for recent port changes.
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_back_end.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/python/m5/objects/OzoneCPU.py:
Support Ron's recent port changes.
src/cpu/ozone/lw_back_end_impl.hh:
Support Ron's recent port changes. Also support handling faults in SE.
--HG--
extra : convert_revision :
aa1ba5111b70199c052da3e13bae605525a69891
Kevin Lim [Fri, 7 Jul 2006 21:33:24 +0000 (17:33 -0400)]
Support Ron's changes for hooking up ports.
src/cpu/checker/cpu.hh:
Now that BaseCPU is a MemObject, the checker must define this function.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/lsq.hh:
src/cpu/o3/lsq_unit.hh:
Implement getPort function so the connector can connect the ports properly.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_unit_impl.hh:
The connector handles connecting the ports now.
src/python/m5/objects/O3CPU.py:
Add ports to the parameters.
--HG--
extra : convert_revision :
0b1a216b9a5d0574e62165d7c6c242498104d918
Kevin Lim [Fri, 7 Jul 2006 20:48:44 +0000 (16:48 -0400)]
Fix for bug when draining and a memory access is outstanding.
--HG--
extra : convert_revision :
1af782cf023ae74c2a3ff9f7aefcea880bc87936
Kevin Lim [Fri, 7 Jul 2006 20:47:28 +0000 (16:47 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-merge
--HG--
extra : convert_revision :
e8933f852352164f4e50444f94cc6ee260e06766
Kevin Lim [Fri, 7 Jul 2006 20:46:08 +0000 (16:46 -0400)]
Take the name of the checkpoint directory in when calling checkpoint() or restoreCheckpoint().
src/sim/main.cc:
src/sim/serialize.cc:
src/sim/serialize.hh:
Take in the directory name when checkpointing.
--HG--
extra : convert_revision :
040e828622480f1051e2156f4439e24864c38d45
Korey Sewell [Fri, 7 Jul 2006 20:19:13 +0000 (16:19 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision :
be8b295ebf54a7c6bf720a20ab6aa9f02aee8060
Ron Dreslinski [Fri, 7 Jul 2006 20:02:22 +0000 (16:02 -0400)]
Fix address range calculation. Still need bus to handle snoop ranges.
On the way towards multi-level caches (L2)
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
Fix address range calculation. Still need bus to handle snoop ranges.
--HG--
extra : convert_revision :
800078d88aab5e563f4a9bb599f91cd44f36e625
Korey Sewell [Fri, 7 Jul 2006 19:58:22 +0000 (15:58 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-o3
--HG--
extra : convert_revision :
f97469b7d19c82deb3d068f80546d729757c25e3