Gabe Black [Thu, 25 Apr 2019 00:19:23 +0000 (17:19 -0700)]
mem: Remove the ISA specialized versions of port proxy's read/write.
These selected their behavior based on ifdefs and had to be disabled
when on the NULL ISA. The versions which take an explicit endianness
have been renamed to just read/write instead of readGtoH and writeHtoG
since the direction of the translation is obvious from context.
Change-Id: I6cfbfda6c4481962d442d3370534e50532d41814
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18372
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Tue, 23 Apr 2019 02:45:10 +0000 (19:45 -0700)]
mem: Minimize the use of MemObject.
MemObject doesn't provide anything beyond its base ClockedObject any
more, so this change removes it from most inheritance hierarchies.
Occasionally MemObject is replaced with SimObject when I was fairly
confident that the extra functionality of ClockedObject wasn't needed.
Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 16 Apr 2019 06:29:57 +0000 (23:29 -0700)]
python: Get rid of the VectorPort constructor.
The only thing it was doing beyond calling the parent Port __init__ was
to set isVec, and nobody actually looks at that value later.
Change-Id: I567cb583e6f02a6c18504b9bb20dd13b3c934822
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18175
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Tue, 16 Apr 2019 03:47:48 +0000 (20:47 -0700)]
python: Replace the Master/Slave Ports with Request/Response ports.
These are a little more descriptive and a little less potentially
offensive.
Change-Id: I84c30f783f0a4c242cb4f54ab272b6fdf1e9eec7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18174
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Giacomo Travaglini [Mon, 1 Apr 2019 13:38:14 +0000 (14:38 +0100)]
arch-arm: updateMiscReg not setting isHyp in aarch64
The isHyp flag should be set for a TLB::NormalTran when in EL2. This
was happening in aarch32 only, where the CPSR mode is checked, while
aarch64 was only using it for explicit EL2 translations, like for AT
instructions.
Change-Id: I54605811e9dde75b5cf8868190b0f4c2a8d46570
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18394
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Thu, 25 Apr 2019 00:13:37 +0000 (17:13 -0700)]
arm: Factor some repetition out of the ProcessInfo constructor.
Change-Id: I34f952d1097886704d37304478de125a915b2615
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18371
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Thu, 25 Apr 2019 00:08:18 +0000 (17:08 -0700)]
arm: Fix some style issues in stacktrace.cc.
De-indent the ArmISA namespace, and wrap some overly long lines.
Change-Id: Idc02b025bdfda483ddbd27d662e2314a5cbcb23c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18370
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Thu, 25 Apr 2019 00:04:16 +0000 (17:04 -0700)]
x86: Refactor the ProcessInfo constructor.
That function had a lot of repetition which is easily factored out
into its own function.
Change-Id: I3b7a522de2ba808856bb59df75b80efde6780e3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18369
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
David Hashe [Wed, 18 Apr 2018 20:40:28 +0000 (16:40 -0400)]
configs: faux-filesystem fix w/ ruby in se mode
These changes are needed so that the config scripts
can report cache hierarchy information to the faux
filesystem.
This is useful for the ROCm runtime when it reads
psuedofiles from the host filesytem from "/proc".
Change-Id: Iad3e6c088d47c9b93979f584de748367eae8259b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12121
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Wed, 24 Apr 2019 23:55:57 +0000 (16:55 -0700)]
x86: Fix some style issues in stacktrace.cc.
De-indent the X86ISA namespace, and wrap some overly long lines.
Change-Id: I01a6b66a1cf721e16e4ed4dd1c3469ee112e9177
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18368
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
David Hashe [Wed, 18 Apr 2018 20:36:55 +0000 (16:36 -0400)]
sim-se: add a faux-filesystem
This change introduces the concept of a faux-filesystem.
The faux-filesystem creates a directory structure in m5out
(or whatever output dir the user specifies) where system calls
may be redirected.
This is useful to avoid non-determinism when reading files
with varying path names (e.g., variations from run-to-run if
the simulation is scheduled on a cluster where paths may change).
Also, this changeset allows circumventing host pseudofiles which
have information specific to the host processor (such as cache
hierarchy or processor information). Bypassing host pseudofiles
can be useful when executing runtimes in the absence of an
operating system kernel since runtimes may try to query standard
files (i.e. /proc or /sys) which are not relevant to an
application executing in syscall emulation mode.
Change-Id: I90821b3b403168b904a662fa98b85def1628621c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12119
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Wed, 10 Apr 2019 14:45:30 +0000 (15:45 +0100)]
arch-arm: Remove un-needed hyp flag in TLBI operations
The hyp flag was probably a legacy pre-v8 flag distinguishing
invalidation targeting PL2 translation regime (hyp mode).
Since the introduction of target_el parameter, hyp boolean is not needed
anymore. The patch works by setting the hyp flag in the flush* methods
in the TLB automatically by checking if target_el == EL2.
Change-Id: I798009e09ff24a383dea871e348188bae2685e8e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18389
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Wed, 10 Apr 2019 13:26:47 +0000 (14:26 +0100)]
arch-arm: Correct target EL field in TLBI operations
Some TLB Invalidation operations affecting the EL2 translation regime
were marked as targeting EL1 instead of EL2
Change-Id: I77821eec7a409e9df6a6814855f9a375832ffe74
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jan-Peter Larsson <jan-peter.larsson@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18388
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Tue, 16 Apr 2019 13:48:10 +0000 (14:48 +0100)]
dev-arm: Move GICv3 (Re)Ditributor address in Realview.py
Base addresses for GICv3's Distributor and Redistributors are
implementation defined: they depend on the platform rather than the
model. This patch is then moving dist_addr and redist_addr
initialization in Realview.py
Change-Id: I1246df500262f4d3d5a38e62d0240945f90941ee
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18393
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Fri, 5 Apr 2019 12:39:05 +0000 (13:39 +0100)]
dev-arm: Limit number of max PE in GICv3 to 128
This is needed since there is a problem in the memory layout of
VExpress_GEM5_V2 as it is: having 256KB pages is creating overlapping
regions when reserving space for 256 PEs.
GICv3 redistributors: 0x2c010000 - 0x30010000
PCI regions: 0x30000000 - 0x40000000
We fix this by cutting down the number of supported PEs to 128
Change-Id: I6e87f66a6150a441ccba298662b4548a4972dc40
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18392
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Fri, 5 Apr 2019 12:12:08 +0000 (13:12 +0100)]
dev-arm: Add GICv4 extension switch in GICv3
This is currently used only for determining which is the correct
size of redistributors in memory (256KB in GICv4 and 128KB in GICv3)
Change-Id: I2c07005e97167fde03548313c9927176788f31dd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18391
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Giacomo Travaglini [Fri, 5 Apr 2019 12:33:01 +0000 (13:33 +0100)]
dev-arm: Check for maximum number of supported PE in GICv3
This is currently set to 256
Change-Id: If7bb2847c22f29bfa0cb4ebf4a7984ee43ab4e29
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18390
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Javier Bueno [Wed, 27 Mar 2019 13:19:52 +0000 (14:19 +0100)]
config: Add flag options to set the hardware prefetchers to use
This patch adds three flag options to set the prefetcher class of the
L1i cache, L1d cache and L2 cache.
Change-Id: I310fcd9c49f9554d98cd565a32bdb96a3e165486
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17709
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Andrea Mondelli [Tue, 23 Apr 2019 17:36:19 +0000 (13:36 -0400)]
cpu,mem: missing override specifier
Change-Id: I731d3ef021596450ac307461f215760a148bb28a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18348
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Tue, 16 Apr 2019 02:58:16 +0000 (19:58 -0700)]
systemc: Use the new TLM socket types in the TLM bridge SimObjects.
These are in the definition of the python version of the SimObjects.
Change-Id: Iadb143158815df68cf32cc254ad19f755ab4e78a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18173
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 16 Apr 2019 02:56:40 +0000 (19:56 -0700)]
systemc: Add Port types for initiator and target sockets.
These make it clear that a port represents a TLM socket, what direction
it faces, and what its width is.
Change-Id: Idcbea2b9b053f1e0685e011bc2c7de2468fb25b2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18172
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 16 Apr 2019 02:47:28 +0000 (19:47 -0700)]
dev: Use the new Port role mechanism to make an EtherInt Port type.
This type always uses the same "ETHERNET" role, and all connections are
symmetric and self compatible.
Change-Id: I1d060f8c098d52ae9f65c052f816bc813590ff9c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18171
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Tue, 16 Apr 2019 04:05:55 +0000 (21:05 -0700)]
python: Generalize the Port.splice function.
Now that the MASTER and SLAVE roles aren't special, the splice function
needs to be able to handle arbitrarily role-d peers.
Change-Id: I22a28b7cdcb93f7f370730b7e38b0e6d3500a6a0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18170
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Tue, 16 Apr 2019 05:10:37 +0000 (22:10 -0700)]
python: Generalize the dot_writer to handle non Master/Slave roles.
Change-Id: I6d93c28e754c0cacacdd5e8885c45bc861135e94
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18169
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Tue, 16 Apr 2019 02:39:14 +0000 (19:39 -0700)]
python: Make Port roles a more generic concept.
A recent change got rid of the strict Master => Slave port relationship
which used to be checked in python and instead left the checking up to
C++. One major downside to this approach is that it was no longer
obvious in the configuration what was supposed to be connected to what,
and it still left the arbitrary and misleading MasterPort and SlavePort
types in the Ethernet devices which could now connect with each other
symmetrically but couldn't actually connect to an arbitrary
MasterPort/SlavePort.
This change exposes the base Port and VectorPort types, and makes them
accept a "role" parameter in __init__ which used to be set directly by
their subclasses. This role can be any string, and will be used later
to check for compatiblity and to give a hint as to what can be
connected to what in the SimObject definitions.
To make the checks work with arbitrary compatible pairs, the base Port
type now has a class method called compat() which accepts a pair of
roles which will become mutually compatible, ie any port with the first
role will be allowed to connect to any port with the second role, and
vice versa. To be self compatible, the same role should be passed in
for both parameters.
To maintain compatibility, the MasterPort and SlavePort types are
retained, but now they're nothing special and could have been set up
in any arbitrary SimObject .py file. The same is true for
MasterVectorPort and SlaveVectorPort.
Also, since we can no longer assume that all edges in the dot graph of
the config should start with a port with the MASTER role and end with
a port with the SLAVE role, Ports now track an is_source property which
says whether the arrow head should be surpressed at that end of the
edge representing the connection.
Change-Id: Ifcc6faab05e437ad87cd21f0ba613b09cf21c321
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18168
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Ciro Santilli [Mon, 15 Apr 2019 13:08:49 +0000 (14:08 +0100)]
python: fix tracing after Python 3 refactor
gem5.opt --debug-flags ExecAll
was failing with:
ImportError: No module named defines
on Python 2.
Change-Id: I06959d6e0ccb7c661c7c749af3392632dac779f3
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18108
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Alexandru Dutu [Tue, 16 Apr 2019 03:36:36 +0000 (23:36 -0400)]
sim-se: Enhance clone for X86KvmCPU
This changeset enables clone to work with X86KvmCPU model, which
will allow running multi-threaded applications at near hardware
speeds. Even though the application is multi-threaded, the KvmCPU
model uses one event queue, therefore, only one hardware thread
will be used, through KVM, to simulate multiple application threads.
Change-Id: I2b2a7b1edb1c56eeb9c4fa0553cd236029cd53f8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18268
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel [Mon, 22 Apr 2019 09:32:22 +0000 (11:32 +0200)]
mem-cache: Fix fix of replacement count
Commit
7976b561de61b7523ca9a860154ad7ba701d12a7 tried fixing
replacement update when a single location can be associated to
multiple blocks.
Although the comment of the correct action was added, the proper
validation check was forgotten. This change adds that check and
moves doing the eviction to when there is a valid block.
Change-Id: I31d8bb914ccfd1849e9d97464d70a58a62f59533
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18210
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Gabe Black [Sun, 14 Apr 2019 03:49:20 +0000 (20:49 -0700)]
cpu: Eliminate the ProxyThreadContext class.
Replace it with direct inheritance from the ThreadContext class in the
SimpleThread class which was the only place it was used.
Also take the opportunity to use some specialized types instead of
ints, etc., add some consts, and fix some style issues.
Change-Id: I5d2cfa87b20dc43615e33e6755c9d016564e9c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18048
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Po-Hao Su [Mon, 22 Apr 2019 08:23:18 +0000 (16:23 +0800)]
configs: Use param to get number of processors
Although the parameter np is the same as options.num_cpus. But we should
get the number of processors from the parameters of the function.
Change-Id: I3eb02d7c75ab35410b773b06001d1b145cdccd49
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18248
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Daniel R. Carvalho [Thu, 18 Apr 2019 12:54:18 +0000 (14:54 +0200)]
mem-cache: Fix increasing replacement count
Replacements should be increased when there is any evicted
block, which does not necessarily have to be the victim.
For example, assume a superblock contains 4 blocks, and both
A and C are stored compressed (belonging to SB_1). Then F,
from SB2 needs to make room by replacing SB1. If F map to
location 2, the number of replacements should be increased,
even though 2 had no valid blocks:
Tag Data Tag Data
|SB_1|--|A|X|C|X| --> |SB_2| |X|F|X|X|
1 2 3 4 1 2 3 4
Change-Id: I7b3735d28a35faa8d8fa613a1555bb258da65859
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18208
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Daniel R. Carvalho [Mon, 11 Feb 2019 14:41:34 +0000 (15:41 +0100)]
mem-cache: Remove blk_addr from Queue::trySatisfyFunctional
The blk_addr is pkt->getBlockAddr(), and therefore can be
acquired internally, when needed, as long as the pkt is
provided.
Change-Id: I2780445d2a0cb9e27257961efc4f438cc19550e5
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17537
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Thu, 24 Jan 2019 14:00:18 +0000 (15:00 +0100)]
mem-cache: Add match functions to QueueEntry
Having the caller decide the matching logic is error-prone, and
frequently ends up with the secure bit being forgotten. This
change adds matching functions to the QueueEntry to avoid this
problem.
As a side effect the signature of findPending has been changed.
Change-Id: I6e494a821c1e6e841ab103ec69632c0e1b269a08
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17530
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Mon, 11 Feb 2019 13:19:57 +0000 (14:19 +0100)]
mem: Add packet matching functions
Add both block and non-block-aligned packet matching functions,
so that both address and secure bits are checked when checking
whether a packet matches a request.
Change-Id: Id0069befb925d112e06f250741cb47d9dfa249cc
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17533
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Wed, 30 Jan 2019 13:46:22 +0000 (14:46 +0100)]
mem-cache: Move Target to QueueEntry
WriteQueueEntry's target has 100% functionality overlap with MSHR's,
therefore make it base to MSHR::Target.
Change-Id: I48614e78179d708bd91bbe75a752e5a05146e8eb
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17534
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Thu, 24 Jan 2019 14:13:07 +0000 (15:13 +0100)]
mem-cache: Assert Entry inherits from QueueEntry in Queue
Queue has several assumptions regarding its template parameter,
so make sure they are fulfilled by forcing Entry to be derived
from QueueEntry.
Change-Id: I0203a62aec00c04ac89e9674d86a44a07f9f13ab
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17529
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Tue, 12 Feb 2019 13:20:42 +0000 (14:20 +0100)]
mem: Make DRAMCtrl::decodeAddr const
DRAMCtrl's decodeAddr does not need to modify the packet it
receives, nor should it modify the contents of the class,
and therefore both the packet and the function are made const.
Change-Id: I577f48d9a43611ba54878a9a793cb7b4fbb326f4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17540
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Daniel R. Carvalho [Fri, 8 Feb 2019 14:31:43 +0000 (15:31 +0100)]
mem: Allow packet to provide its own addr range
Add a getter to Packet to allow it to provide its own addr
range.
Change-Id: I2128ea3b71906502d10d9376b050a62407defd23
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17536
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andrea Mondelli [Tue, 16 Apr 2019 13:35:32 +0000 (09:35 -0400)]
mem: missing override specifier
Change-Id: Ied4817bcda317826303a1bb688b41823b18b489b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18128
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Gabe Black [Tue, 26 Mar 2019 01:08:27 +0000 (18:08 -0700)]
mem: Teach SimpleMem to return a MemBackdoor when appropriate.
If the back door SimpleMem inherits from AbstractMem has a pointer and
is hence valid, SimpleMem will return that pointer when asked.
Change-Id: I734daba48e4ae5b4ad8ac9a108e7b12b5e82803f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17669
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Gabe Black [Tue, 26 Mar 2019 01:04:50 +0000 (18:04 -0700)]
mem: Maintain a back door into the AbstractMem's backing store.
The backing store pointer is added to the back door when it's set,
assuming that the range isn't interleaved. If it is interleaved, then
there isn't a way to get a flat pointer to the backing store.
Depending on how the backing store is set up, it may be possible to
return a larger backdoor which applies to all interleaved memories at
the same time and to avoid problems with interleaving. I'm leaving this
as a todo.
Change-Id: I0e531c22835ec10954ab39f761b3d87666b59220
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17668
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Rutuja Oza [Mon, 11 Mar 2019 22:26:52 +0000 (15:26 -0700)]
tests: Add tests for learning_gem5 configs
Change-Id: Ia9cbb77115c741051c871526517bb7d8124a8051
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17873
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Jason Lowe-Power [Fri, 5 Apr 2019 02:02:16 +0000 (19:02 -0700)]
tests: Add protocol as an option to SconsFixture
Change-Id: I16e9a6169e7ad50601e460e221d6a05db1208783
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17872
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Hoa Nguyen [Fri, 1 Mar 2019 02:26:07 +0000 (18:26 -0800)]
tests: add riscv to cpu tests
Change-Id: Id8e767afbb74f79b980d8160eefc13e7f529f1c3
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16889
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Anis Peysieux [Tue, 9 Apr 2019 14:26:53 +0000 (16:26 +0200)]
mem-cache: Fix RRPV for RRIP
The RRPV values for RRIP and NRU replacment policies.
Long re-rereference interval was used instead of
distant re-rereference interval and vice-versa.
The btp value permit to choose beetwen distant and
long insertion ratio. A btp value of 0 force the
policy to always insert at a distant re-reference
interval and a btp value of 100 force the policy to
always insert at a long (intermediate) re-rereference
interval.
Change-Id: I516098f73942b769dcc31fe0edfe07c3e9c3effd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17851
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Giacomo Travaglini [Tue, 9 Apr 2019 08:30:43 +0000 (09:30 +0100)]
arch-arm: Enable PMSELR_EL0 read in PMU
Change-Id: Ic1ec1d03464a7ce42295cee8a9f4ebcd3e90def1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17948
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Fri, 22 Mar 2019 22:46:57 +0000 (15:46 -0700)]
mem: Plumb backdoor requests through the xbar classes.
Change-Id: Ic8f49339ab95c31d2f00edfdf23a46f1271ec3aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17593
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 22 Mar 2019 00:28:26 +0000 (17:28 -0700)]
systemc: Teach the TLM bridges how to use gem5's new backdoor mechanism.
This change teaches the TLM bridges to translate between TLM's DMI
mechanism and gem5's backdoor mechanism.
Change-Id: I942a6cce4fb87f10e8173f4ee49b6c7b0ffa7e4a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17591
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 22 Mar 2019 00:23:03 +0000 (17:23 -0700)]
mem: Add sendAtomicBackdoor/recvAtomicBackdoor port methods.
These both perform atomic accesses like their non-backdoor equivalents,
and also request a backdoor corresponding to the access.
The default implementation for recvAtomicBackdoor prints a warning
(once per port instance), calls recvAtomic to do the actual access,
and leaves the backdoor pointer as nullptr. That way if an object
doesn't know how to handle or transfer requests for a back door, it
automatically replies in a safe way that ignores the back door request.
Change-Id: Ia9fbbe9996eb4b71ea62214d203aa039a05f1618
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17590
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Nikos Nikoleris [Tue, 12 Feb 2019 08:26:14 +0000 (08:26 +0000)]
mem-cache: Fix MSHR handling of cache clean requests
Previously satisfied clean requests would not snoop in-service
MSHRs. This is a problem when a clean request is also invalidating, in
which case we have to post-invalidate or post-downgrade outstanding
requests. This changes fixes this bug.
Change-Id: I31e42aa94dd3637b2818e00fbaae68c810145eaf
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17728
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Giacomo Travaglini [Fri, 29 Mar 2019 13:02:05 +0000 (13:02 +0000)]
cpu: O3 switchFreeList checking VecElems instead of FloatRegs
Vector elements should be checked instead of floats since those are the
ones mapped to the vector registers.
Change-Id: I36088ab90e63720d846fcf5b43360da105b6c736
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17850
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Jason Lowe-Power [Fri, 5 Apr 2019 17:43:59 +0000 (10:43 -0700)]
learning_gem5,configs: Update ruby_test
Use SimpleMemory instead of DDR3 so we can use the timing results in
tests. By using SimpleMemory, even if the DRAM timing changes the timing
of this test won't change. I expect the timing of SimpleMemory to never
change.
Change-Id: I4c75981d7b8bfc4dcca59e628e89f5a6ea4c0e36
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17871
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Jason Lowe-Power [Fri, 5 Apr 2019 17:29:54 +0000 (10:29 -0700)]
learning_gem5: Fix vector port panic in SimpleCache
Change-Id: I0f3b71fdbed77690c533d9d14e774ab2cc08c053
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17870
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Jason Lowe-Power [Fri, 5 Apr 2019 01:36:42 +0000 (18:36 -0700)]
configs: Fix import path error in learning_gem5 part3
Change-Id: I2c5cd22bded998bae8e7aa77e42e1b042ce1c5f5
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17869
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Jason Lowe-Power [Fri, 5 Apr 2019 01:36:23 +0000 (18:36 -0700)]
configs: Add full path for learning_gem5 binaries
Change-Id: Ie48429d65e322136109a223ed404937989aae494
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17868
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Ryan Gambord [Sun, 7 Apr 2019 06:37:24 +0000 (23:37 -0700)]
configs: Removed redudant exec-style import
garnet_synth_traffic.py imports common.Options on line 40, so exec'ing
the Options.py file again seems redundant.
It also runs Options.py as a script rather than a module, which throws
ValueError: Attempted relative import in non-package due to the recent
change to python3 imports.
Change-Id: Id729a8dfa776af0d14312e765168aff6900eb727
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17888
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Fri, 22 Mar 2019 00:12:08 +0000 (17:12 -0700)]
mem: Add a MemBackdoor type to track memory backdoors.
These are similar to the structures TLM's DMI mechanism uses. Instead
of having an invalidation broadcast which propogates backwards up the
port hierarchy, this mechanism tracks a set of callbacks which are
triggered when a back door is invalidated to let other holders clean
up their bookkeeping.
Change-Id: If24489258dcaee14d7b6e5b996dfb1c2636f26ab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17589
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Nikos Nikoleris [Thu, 28 Feb 2019 17:55:41 +0000 (17:55 +0000)]
cpu: Correctly account for executed instructions in simple cpus
Change-Id: I53f34b2d9db6e4d2e03dde42a970764bb2a5e701
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17730
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Ryan Gambord [Thu, 4 Apr 2019 16:25:07 +0000 (12:25 -0400)]
mem-cache: ambiguous use of abs function
std::abs doesn't accept unsigned long long, generating the error:
error: call to 'abs' is ambiguous
Use instead a compare-and-subtract idiom.
Also, Changed return type of distanceFromTrigger from unsigned int to Addr to
prevent overflow problems.
Change-Id: Ia7752c1c7a838f98e8c7ed6ade9f586f31bbcf7d
Signed-off-by: Ryan Gambord <gambordr@oregonstate.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17788
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Jason Lowe-Power [Thu, 4 Apr 2019 21:10:16 +0000 (14:10 -0700)]
mem: Reverse order of write/read mem queue check
For atomic RMW instructions that go directly to memory, we want to put
them on the write queue instead of the read queue. Swap the if/else
condition to accomplish this.
Note: This is ignoring the read latency of the RMW, but these
instructions should usually be handled in caches anyway.
Change-Id: I62dbfff3a16ac470f1ebdb489abe878962b20bb6
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17828
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Jason Lowe-Power [Mon, 3 Dec 2018 19:19:37 +0000 (11:19 -0800)]
tests: Add Jenkins presubmit and continuous test scripts
Note that continuous currently isn't used.
Change-Id: Ifcff88c8c4c75a9f630b97eaca22edd1681529c3
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17456
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Javier Bueno [Tue, 2 Apr 2019 21:34:20 +0000 (23:34 +0200)]
mem-cache: AMPM Prefetcher fails when restoring from a checkpoint
The preriodic event triggers an assertion due to an incorrect tick value to
schedule when restoring from a checkpoint.
Change-Id: I9454dd0c97d5a098f8a409886e63f7a7e990947c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17732
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andrea Mondelli [Wed, 6 Mar 2019 15:50:48 +0000 (10:50 -0500)]
misc: Removed inconsistency in O3* debug msgs
Added consistency in the DEBUG message form, to allow a better parsing.
Fixed sn/tid type parameter.
Removed some annoying newlines
Change-Id: I4761c49fc12b874a7d8b46779475b606865cad4b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17248
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Andrea Mondelli [Mon, 25 Mar 2019 16:41:54 +0000 (12:41 -0400)]
arch-mips: added missing override specifier (o3)
Change-Id: Ic538825a2964fd62def672b933a83067a15bd12a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Javier Bueno [Tue, 2 Apr 2019 21:29:42 +0000 (23:29 +0200)]
mem-cache: Fix PIF prefetcher compilation error with NULL ISA
Referencing BaseCPU is causing a compilation error when using the NULL ISA.
This patch changes the reference to a SimObject, which fixes the problem.
Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17731
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Javier Bueno [Tue, 2 Apr 2019 21:43:28 +0000 (23:43 +0200)]
mem-cache: ISB prefetcher was triggering an assertion
An assertion ignored the case when an entry of the SP table had been invalidated.
Change-Id: I5bf04e7a0979300b0f41f680c371f6397d4cbf3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17734
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Javier Bueno [Tue, 2 Apr 2019 21:39:06 +0000 (23:39 +0200)]
mem-cache: Fix panic in Indirect Memory prefetcher
Memory requests with a size non-power-of-two and less than 8 values were causing
a panic, but there these should be allowed and ignored by the prefetcher.
Change-Id: I86baa60058cc8a7f232d6ba5748d4c24a463c840
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17733
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Giacomo Travaglini [Mon, 18 Feb 2019 14:33:36 +0000 (14:33 +0000)]
dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt
Change-Id: I88e2b72849cdf3f69026c62517303837e7d3d551
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17629
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Ivan Pizarro [Mon, 25 Feb 2019 13:30:55 +0000 (14:30 +0100)]
mem-cache: Proactive Instruction Fetch Implementation
Ferdman, M., Kaynak, C., & Falsafi, B. (2011, December).
Proactive instruction fetch. In Proceedings of the 44th Annual IEEE/ACM
International Symposium on Microarchitecture (pp. 152-162). ACM.
Change-Id: I38c3ab30a94ab279f03e3d5936ce8ed118310c0e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16968
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Andrea Mondelli [Thu, 14 Mar 2019 22:20:54 +0000 (18:20 -0400)]
dev-arm: Correct cast of template parameter
Clang with -Wconstant-conversion is _very_ restrictive on casting.
The shift operator results in an incorrect promotion.
This patch add a compile-time static cast that remove the error
when clang is used.
Change-Id: I3aa1e77da2565799feadc32317d5faa111b2de86
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17308
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Thu, 14 Mar 2019 12:33:51 +0000 (05:33 -0700)]
systemc: Templatize the gem5/TLM bridge SimObjects.
The C++ side is templated, and there are python versions for each
(currently two) width of bridge supported.
Change-Id: I4baa9f22d4c87629d45e9e1292eb66c65d25a655
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17234
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 12 Mar 2019 04:27:17 +0000 (21:27 -0700)]
systemc: Delete extra code from src/systemc/tlm_bridge.
Much of the code in src/systemc/tlm_bridge has been absorbed into the
TLM/gem5 bridge SimObjects and is no longer needed and redundant with
the original version in util/.
Change-Id: I0fa7af67649987cf9f6fc5cd4783002dde2242ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17233
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Mon, 11 Mar 2019 23:02:26 +0000 (16:02 -0700)]
systemc: Create unified gem5/TLM bridge SimObjects.
These objects expose a standard TLM initiator or target socket with
width 64, and a gem5 slave or master port. What goes in one type of
port comes out the other with the appropriate conversion applied.
Change-Id: I65e07f746d46d3db0197968b78fffc5ddaede9bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17232
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Tue, 26 Feb 2019 04:27:06 +0000 (20:27 -0800)]
tlm: Initial import of tlm/gem5 bridge code.
This is a slightly mangled version of the existing bridge code in
util/tlm/src/. The changes fix some small style issues, change to gem5
specific include paths, and removes the Gem5SimControl code. That code
coordinates gem5 with the external systemc kernel, and in this usage
there's no external kernel.
The code imported here compiles, but it isn't yet expected to work.
Change-Id: I9c593a52e2554534720d21cd31a03e543ad897ad
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17231
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Wed, 13 Mar 2019 00:16:23 +0000 (17:16 -0700)]
systemc: Provide a utility Port TLM socket wrapper class.
This class should make it easy to attach TLM sockets into the gem5
python Port config mechanism.
Change-Id: I3548c654d56bfc852f3fc98fe6433163b14f7fe3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17230
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Javier Bueno [Tue, 26 Mar 2019 22:12:00 +0000 (23:12 +0100)]
cpu: Added a probe to notify the address of retired instructions
A probe is added to notify the address of each retired instruction.
Change-Id: Iefc1b09d74b3aa0aa5773b17ba637bf51f5a59c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17632
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Daniel R. Carvalho [Wed, 27 Mar 2019 15:38:07 +0000 (16:38 +0100)]
mem-cache: Remove extra cache header from AMAP
The cache header was being included in the AMAP, although not
used, which resulted in slightly longer compilation time.
Change-Id: I3654bc719c6b5f558af116addae159301602a3cf
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17711
Reviewed-by: Javier Bueno Hedo <javier.bueno@metempsy.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Javier Setoain [Thu, 14 Mar 2019 17:42:44 +0000 (17:42 +0000)]
arch-arm: Fix use of bitwise operators on booleans
Change-Id: I3762b2921f1d00a9104d8dc11a19dc0a219581e5
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17288
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Tue, 26 Mar 2019 18:02:11 +0000 (18:02 +0000)]
arch-arm: Fix index generation for VecElem operands
Current operand generation is not providing VecElems with the right
vector index and element index.
The bug was covered when registers were 128 bit wide, but with SVE we
have augmented the vector register size and the bug has been exposed.
E.g. With dest = 2,
FpDestP2 = (vec_index = 0, elem_index = 4)
whereas it should be
FpDestP2 = (vec_index = 1, elem_index = 0)
Change-Id: Iad02fb477afd0d3dd3d437bf2ca4338fbd142107
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17710
Giacomo Travaglini [Mon, 18 Feb 2019 14:15:41 +0000 (14:15 +0000)]
dev-arm: Rename GIC maintenance interrupt from ppint to maint_int
ppint is a generic name which only reflects Arm recommendation of
assigning the maintanance interrupt to a PPI (numbered 25)
Change-Id: Ic5abb6ed50817ad2d165b5df46dd989eb195a9db
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17628
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Fri, 8 Mar 2019 11:06:21 +0000 (11:06 +0000)]
dev-arm: Fix GICv3 overflow for INTID > 256
SPIs can get to a maximum number of 1023, so that an uint8_t is not capable
of representing all of them.
Change-Id: I7a2c43b41ac93eabdfcf8311681240416b954177
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17631
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Fri, 8 Mar 2019 10:47:02 +0000 (10:47 +0000)]
dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)
For SGIs and PPIs:
* When ARE is 1 (only value supported in gem5) for the Security state of
an interrupt, the field for that interrupt is RES0 and an implementation
is permitted to make the field RAZ/WI in this case.
Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Javier Bueno [Wed, 27 Mar 2019 11:35:54 +0000 (12:35 +0100)]
config: Use the corresponding HPI Caches when using the HPI cpu
The HPI cpu comes with specific cache definitions, but they
are ignored when using this cpu. This patch solves this in the same
way it is done for the O3_ARM_v7a cpu.
Change-Id: Iabf763291099d9508e3c5eac00b1e233cb38ce6b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17708
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Pau Cabre [Fri, 1 Mar 2019 16:32:16 +0000 (17:32 +0100)]
cpu: Fixed the indirect branch predictor GHR handling
The internal indirect predictor global history was not being updated
properly, resulting in higher than expected miss rates
Also added a parameter to set the size of the indirect predictor GHR
Change-Id: Ibc797816974cba6719da65122801e8919559a003
Signed-off-by: Pau Cabre <pau.cabre@metempsy.com>
Reported-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16928
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu>
Reviewed-by: Sudhanshu Jha <sudhanshu.jha@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Gabe Black [Tue, 26 Mar 2019 18:29:28 +0000 (11:29 -0700)]
mem: Deleting this init() method was accidentally dropped during rebase.
Deleting this init() method was part of a change just committed, but
was accidentally dropped during a rebase.
Change-Id: I0f22778596ed11e182f3111d9999a0fef727f6cc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17688
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 22 Mar 2019 21:23:21 +0000 (14:23 -0700)]
mem: Clean up the xbars a little.
Get rid of comments which just restate the code, get rid of redundant
"virtual" keywords, add "override"s, fix style, and get rid of
xbar::init which was empty and hiding the parent class init.
Change-Id: I8ce20abee340baa88084d142f2fb8c633ee54ba9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17592
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Gabe Black [Fri, 22 Mar 2019 00:07:58 +0000 (17:07 -0700)]
base: Make AddrRangeMap able to return non-const iterators.
The erase() method only accepts regular iterators which is consistent
with the normal STL map, but the existing find() only returns const
iterators. The STL container can return either depending on if "this"
is const.
Unfortunately there isn't a great way to have only one find
implementation which returns the right type of iterator under the right
conditions. Also, it's not possible to turn a const_iterator into an
iterator, but it is possible to go the other way. This change
duplicates very short functions which return iterators, and for find
does the only thing I could find which avoids having to copy that
whole large function.
Change-Id: I2f789b5d0881feb9adff9978bd40e31731c6a688
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17588
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Javier Bueno [Sat, 23 Mar 2019 22:02:44 +0000 (23:02 +0100)]
configs: fix class reference in CacheConfigs
One reference was not properly updated when changing to absolute import paths
Change-Id: Idf330487d5d08d92ebb4489f16d75429f882bd7a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17541
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Mon, 25 Feb 2019 17:05:09 +0000 (17:05 +0000)]
dev-arm: Set/Unset dma coherent mode from python
With this patch it will be possible to automatically enable/disable the
dma-coherent property for the GenericArmPciHost autogenerated DTB. This
has been done by adding the _dma_coherent param.
Change-Id: I1759fced74e42410462637ca77997a351314a90a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16748
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Isaac Sánchez Barrera [Wed, 20 Mar 2019 13:32:22 +0000 (14:32 +0100)]
base,python: Fix to allow multiple --debug-ignore values.
When adding multiple SimObjects to --debug-ignore, either separating the values with
a colon or adding multiple --debug-ignore flags, the previous code only ignored the
last SimObject in the list. This changeset adds and uses new `ObjectMatch::add` and
`Logger::addIgnore` methods to make the functionality of the flag consistent with
its description.
Change-Id: Ib6967a48611ea59a211f81af2a970c4de429b1be
Signed-off-by: Isaac Sánchez Barrera <isaac.sanchez@bsc.es>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17488
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Daniel R. Carvalho [Thu, 26 Jul 2018 10:07:07 +0000 (12:07 +0200)]
configs: Remove default kernel value from system creation
Kernel was being set using a placeholder and then assigned the
correct value. This would generate the following error if the
placeholder file did not exist:
'IOError: Can't find file <placeholder> on path'
This patch follows the same directions of commit
12eca7ac04ae1ba559bf322b5c625513929d369d and removes the default
values, forcing the user to properly configure the kernel.
Change-Id: I0eb45d12eda6b6efe9a3fe118996b640844a7b34
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11850
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Javier Setoain [Thu, 14 Mar 2019 18:06:05 +0000 (18:06 +0000)]
arch-arm: Add missing fall-through defaults
Change-Id: Ie64b83d754c4719a77c7788879be71304a9b786e
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17289
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Sandipan Das [Wed, 30 Jan 2019 14:48:49 +0000 (20:18 +0530)]
arch-power: Rename program counter registers
The Power ISA specification lists the Program Counter (PC) and
the Next Program Counter (NPC) registers as Current Instruction
Address (CIA) and Next Instruction Address (NIA). This applies
the ISA naming convention for these two registers.
Change-Id: I8b9094ab1c809f4dfdb4d7330c17f360adf063e9
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16603
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Sandipan Das [Wed, 30 Jan 2019 14:48:49 +0000 (20:18 +0530)]
arch-power: Simplify doubleword operand types
Currently, 'sq' and 'uq' are used to represent signed and
unsigned doublewords respectively. Since all recent Power
ISA specifications list 128-bit quadwords as a valid data
type, it may be misleading to use the current terminology
in case support for such operands are added in the future.
So, to simplify this, 'sd' and 'ud' are used to represent
signed and unsigned doublewords respectively.
Change-Id: Ie7831c596fc8f9ddfdf3b652c37cfe26484ebe01
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16602
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Andrea Mondelli [Tue, 19 Mar 2019 17:12:58 +0000 (13:12 -0400)]
misc: missing override specifier
Missing specifier of overridden virtual function
declared in sim_object.hh
Removed redundant "virtual" keyword
Change-Id: I42aa3349b537c9e62607bce20cf1b3aabdb99bf2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17468
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tiago Muck [Tue, 28 Aug 2018 17:44:54 +0000 (12:44 -0500)]
sim-se: Fixed initialization array size
Doubled the size of the zeroed auxiliary vector since 2 * intSize on
aarch64 > sizeof(uint64).
Change-Id: I5196b000a696e9ea3f2b5daa5d5bb071794369aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17088
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
Giacomo Travaglini [Thu, 21 Mar 2019 15:41:04 +0000 (15:41 +0000)]
base: Fix CircularQueue's operator-= when negative subtraction
Using operator-= when the rhs is a negative value is equivalent
to using += on -rhs. This is fixing rounding in that scenario.
Change-Id: Ia22e51f81a6805d27fd6b2115d288bb23421d00f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17528
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Giacomo Travaglini [Fri, 8 Mar 2019 16:01:20 +0000 (16:01 +0000)]
base: Fix CircularQueue when diffing iterators
This patch is fixing CircularQueue iterators' subtraction, in particular
the behaviour when head and tail round multiple times.
Change-Id: Ie79ac8accd30a10cf039cf4def87675b01375d6b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17188
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Andrea Mondelli [Tue, 19 Mar 2019 17:56:59 +0000 (13:56 -0400)]
dev-arm: ambiguous use of getPort()
The recent introduction of getPort() creates a conflict with
the existing method used in arm MMU.
This patch rename the old getPort() in getDMAPort() according
to the returned value (DmaPort class type)
Change-Id: Ief3d83650fd6b08490522341631244be06e380ce
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17469
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Jason Lowe-Power [Sat, 16 Mar 2019 01:29:17 +0000 (18:29 -0700)]
tests: Add ignore for stdin not terminal
Change-Id: I496a9f3a0156557415d455dd2ca54c92577ca5f5
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17455
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>