whitequark [Sun, 5 Jul 2020 23:39:47 +0000 (23:39 +0000)]
docs: use sphinxcontrib-platformpicker.
Fixes #416.
whitequark [Sat, 4 Jul 2020 02:09:35 +0000 (02:09 +0000)]
docs: link to community tutorials until we have an official one.
whitequark [Thu, 2 Jul 2020 23:11:35 +0000 (23:11 +0000)]
docs/lang: document constshifts.
whitequark [Thu, 2 Jul 2020 23:08:10 +0000 (23:08 +0000)]
docs/index: rename to "Language & toolchain".
whitequark [Thu, 2 Jul 2020 22:49:04 +0000 (22:49 +0000)]
test: remove FHDLTestCase.assertRaisesRegex.
This method is only there because I misunderstood the documentation
of unittest.
whitequark [Thu, 2 Jul 2020 22:22:44 +0000 (22:22 +0000)]
compat.fhdl.specials: fix handling of tristate (i=None) pins.
Fixes #406.
whitequark [Thu, 2 Jul 2020 18:26:08 +0000 (18:26 +0000)]
_yosys→_toolchain.yosys
whitequark [Thu, 2 Jul 2020 18:13:54 +0000 (18:13 +0000)]
vendor: `yosys` is not a required tool for proprietary toolchains.
Since commit
b9799b4c, the discovery mechanism for the Yosys required
to produce Verilog is different from the usual require_tool(); namely
it is possible to produce Verilog without a `yosys` binary on PATH.
Fixes #419.
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:40:50 +0000 (14:40 +0000)]
add wheel as setup dependency
whitequark [Wed, 1 Jul 2020 08:58:36 +0000 (08:58 +0000)]
docs/install: use pip/pip3 more consistently.
whitequark [Wed, 1 Jul 2020 08:53:52 +0000 (08:53 +0000)]
docs: clarify naming.
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:34:49 +0000 (14:34 +0000)]
re-add setutools and setuptools_scm
whitequark [Wed, 1 Jul 2020 08:16:28 +0000 (08:16 +0000)]
Revert "Add PEP 518 `pyproject.toml`."
This reverts commit
7fca037f9c14974f499195171bb84c38ebddc1e1.
This broke editable installs and has to be reverted due to a number
of pip issues:
* pypa/pip#6375
* pypa/pip#6434
* pypa/pip#6438
We can put this back once PEP 517/518 support editable installs.
Until then the legacy behavior will suffice, and we should just teach
people to install the dependencies in virtualenvs or something...
whitequark [Wed, 1 Jul 2020 08:03:57 +0000 (08:03 +0000)]
docs: add a crude approximation of intersphinx toctrees.
This is a pretty awful hack. We could do this properly after one of
the following issues is fixed:
* sphinx-doc/sphinx#701
* sphinx-doc/sphinx#1836
whitequark [Wed, 1 Jul 2020 07:00:02 +0000 (07:00 +0000)]
Gracefully handle missing dependencies.
Some people's workflows involve not using `pip`. This is not
a recommended way to use nMigen, but is prevalent enough for good
enough reason that we try to keep them working anyway.
whitequark [Wed, 1 Jul 2020 06:33:03 +0000 (06:33 +0000)]
docs/install: fix dead link.
whitequark [Wed, 1 Jul 2020 06:32:15 +0000 (06:32 +0000)]
docs/install: quote special chars to avoid issues with extended glob.
whitequark [Wed, 1 Jul 2020 06:15:16 +0000 (06:15 +0000)]
docs/install: explain how to install non-editable snapshot from git.
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:31:28 +0000 (14:31 +0000)]
manually remove setuptools and setuptools_scm, moved
to pyproject.toml
whitequark [Wed, 1 Jul 2020 05:58:05 +0000 (05:58 +0000)]
Add PEP 518 `pyproject.toml`.
This is necessary to be able to install nMigen into a virtualenv that
does not have `wheel` installed in certain cases.
See #349.
whitequark [Wed, 1 Jul 2020 05:06:20 +0000 (05:06 +0000)]
docs/install: use `pip install --user` on *nix.
whitequark [Wed, 1 Jul 2020 04:11:51 +0000 (04:11 +0000)]
docs/install: reduce repetition.
whitequark [Wed, 1 Jul 2020 03:59:16 +0000 (03:59 +0000)]
docs: reword slightly.
whitequark [Wed, 1 Jul 2020 03:46:59 +0000 (03:46 +0000)]
docs: explain how to install GTKWave on Windows.
whitequark [Wed, 1 Jul 2020 03:37:29 +0000 (03:37 +0000)]
CI: build docs on all pushes, update only on
whitequark [Wed, 1 Jul 2020 03:32:17 +0000 (03:32 +0000)]
docs: rewrite install instructions to be easier to understand.
whitequark [Tue, 30 Jun 2020 22:29:43 +0000 (22:29 +0000)]
docs: fix syntax.
whitequark [Tue, 30 Jun 2020 22:28:12 +0000 (22:28 +0000)]
docs: fix CI workflow.
whitequark [Tue, 30 Jun 2020 22:26:54 +0000 (22:26 +0000)]
docs: explain that `pip3 install -e` should be run after pulling.
whitequark [Mon, 27 Apr 2020 07:21:31 +0000 (07:21 +0000)]
Add (heavily work in progress) documentation.
To render correctly, the docs require:
* pygments/pygments#1441
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:16:18 +0000 (14:16 +0000)]
manually add import_metadata, import_resources
whitequark [Tue, 30 Jun 2020 22:08:59 +0000 (22:08 +0000)]
Don't use pkg_resources.
This package is deprecated and introduces a massive amount of startup
latency. On my machine with 264 installed Python packages, it reduces
the time required to `import nmigen` from ~100ms to ~200ms.
whitequark [Sun, 28 Jun 2020 05:17:33 +0000 (05:17 +0000)]
lib.cdc: update PulseSynchronizer to follow conventions.
Fixes #370.
whitequark [Sun, 28 Jun 2020 05:04:16 +0000 (05:04 +0000)]
back.pysim: simplify.
Remove _EvalContext, which was a level of indirection serving almost
no purpose. (The only case where it would be useful is repeatedly
resetting a simulation that, each time it is reset, would create new
signals to communicate with between coroutine processes. In that case
the signal states would not be persisted in _SimulatorState, but
would be removed with the _EvalContext that is recreated each time
the simulation is reset. But this could be solved with a weak map
instead.)
This regresses simulator startup time by 10-15% for unknown reasons
but is necessary to align pysim and future cxxsim.
Alan Green [Tue, 23 Jun 2020 12:12:02 +0000 (22:12 +1000)]
_yosys: handle unparseable versions
Do not use yosys binaries with unparseable version numbers. This ensures
that nmigen always knows what version of yosys it is generating RTLIL
for.
The effect of this change is that if the version number of the system
yosys is unparsable, nmigen will attempt to fallback to the builtin
Yosys.
Fixes #409.
whitequark [Sun, 21 Jun 2020 17:28:01 +0000 (17:28 +0000)]
vendor.lattice_machxo2: add back as a compatibility shim.
Gwenhael Goavec-Merou [Sun, 21 Jun 2020 17:24:47 +0000 (19:24 +0200)]
vendor.lattice_machxo*: add MachXO3L support.
whitequark [Sun, 14 Jun 2020 09:38:32 +0000 (09:38 +0000)]
back.verilog: refactor Yosys script generation. NFCI.
In commit
5f30bcbb, back.cxxsim gained a nicer way to generate
a script; this commit brings it to back.verilog too.
whitequark [Sun, 14 Jun 2020 09:25:54 +0000 (09:25 +0000)]
back.cxxrtl: allow injecting black boxes.
whitequark [Sun, 14 Jun 2020 00:04:18 +0000 (00:04 +0000)]
_yosys: add a way to retrieve Yosys data directory.
This is important for CXXRTL, since that's where its include files
are located.
whitequark [Sun, 14 Jun 2020 00:03:36 +0000 (00:03 +0000)]
_yosys: fix typo in error message.
whitequark [Thu, 11 Jun 2020 16:29:12 +0000 (16:29 +0000)]
test: fix example test after commit
a7b8ced9.
whitequark [Thu, 11 Jun 2020 16:19:40 +0000 (16:19 +0000)]
back.cxxrtl: new backend.
whitequark [Thu, 11 Jun 2020 16:12:52 +0000 (16:12 +0000)]
_yosys: translate Yosys warnings to Python warnings.
This isn't used yet (the only Yosys warning we can get is useless),
but will be handy for CXXRTL.
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:07:39 +0000 (14:07 +0000)]
fix yosys version import
Luke Kenneth Casson Leighton [Fri, 31 Dec 2021 14:02:09 +0000 (14:02 +0000)]
manually patch in nmigen-yosys
whitequark [Fri, 22 May 2020 16:50:45 +0000 (16:50 +0000)]
back.verilog: fall back to nmigen_yosys package.
The nmigen-yosys PyPI package provides a custom, minimal build of
Yosys that uses (at the moment) wasmtime-py to deliver a single
WASM binary that can run on many platforms, and eliminates the need
to build Yosys from source.
Not only does this lower barrier to entry for new nMigen developers,
but also decouples nMigen from Yosys' yearly release cycle, which
lets us use new features and drop workarounds for Yosys bugs earlier.
The source for the nmigen-yosys package is provided at:
https://github.com/nmigen/nmigen-yosys
The package is built from upstream source and released automatically
with no manual steps.
Fixes #371.
whitequark [Thu, 11 Jun 2020 15:36:43 +0000 (15:36 +0000)]
nmigen.cli: fix file type autodetection code.
whitequark [Thu, 11 Jun 2020 15:17:49 +0000 (15:17 +0000)]
back.verilog: remove unused imports. NFC.
Adam Greig [Sat, 6 Jun 2020 11:43:25 +0000 (12:43 +0100)]
hdl.xfrm: preserve allow_reset_less when transforming ResetSignal.
Fixes #400.
Shawn Anastasio [Fri, 5 Jun 2020 03:19:46 +0000 (22:19 -0500)]
hdl.rec: preserve shapes when constructing a layout.
Preserve the original user-provided shape, while still checking
its validity. This allows Enum decoders to work when specifying
record fields with Enums.
Fixes #393.
whitequark [Fri, 29 May 2020 17:45:09 +0000 (17:45 +0000)]
setup: exclude tests.
The inclusion of tests in the package was completely unintentional
and a result of my lack of knowledge of setuptools. If you are using
nmigen.test.utils, please copy the parts you need to your own code
because the nmigen.test code can and will change without notice.
whitequark [Fri, 29 May 2020 17:45:09 +0000 (17:45 +0000)]
vendor.lattice_ice40: reword confusing comment. NFC.
Robin Ole Heinemann [Sun, 24 May 2020 15:54:17 +0000 (17:54 +0200)]
hdl.ast: fix typo
whitequark [Thu, 21 May 2020 10:41:23 +0000 (10:41 +0000)]
Update .gitignore.
whitequark [Thu, 21 May 2020 09:49:42 +0000 (09:49 +0000)]
vendor.intel: don't use `write_verilog -decimal`.
See commit
702e41ba for details.
whitequark [Thu, 21 May 2020 09:48:42 +0000 (09:48 +0000)]
vendor.intel: double-quote Tcl values rather than brace-quoting.
For unknown reasons, Quartus treats {foo} and "foo" in completely
different ways, which is not true for normal Tcl code; specifically,
it preserves the braces if they are used. Because of this, since
commit
6cee2804, the vendor.intel package was completely broken.
whitequark [Thu, 21 May 2020 08:57:30 +0000 (08:57 +0000)]
vendor.xilinx_{7series,ultrascale}: don't use `write_verilog -decimal`.
In commit
892cff05, `-decimal` was used when writing Verilog for
Vivado targets because it treats (* keep=32'd1 *) and (* keep=1 *)
differently in violation of Verilog LRM. However, it is possible
to avoid that workaround by using (* keep="TRUE" *). Do that,
and remove `-decimal` to avoid special-casing 32-bit constants.
Refs #373.
whitequark [Wed, 20 May 2020 05:35:47 +0000 (05:35 +0000)]
build.plat: skip clock constraints on unused signals.
It's not very nice to add more internal mutable state to Platform
related classes, but our whole approach for Platform is inherently
stateful, and other solutions (like changing every individual vendor
platform to check for unused signals) are even worse.
Fixes #374.
whitequark [Wed, 20 May 2020 04:58:03 +0000 (04:58 +0000)]
vendor.xilinx_{7series,ultrascale}: add (*keep*) on constrained clocks.
If the clock signal is not a top-level port and has aliases, it can
be optimized out, and then the constraint will no longer apply.
To prevent this, make sure the constrained signal is preferred over
any aliases by using the `keep` attribute.
Vivado does not parse attributes like (* keep = 32'd1 *) as valid
even though, AFAICT, they are equivalent to (* keep = 1 *) or simply
(* keep *) per IEEE 1364. To work around this, use the solution we
currently use for Quartus, which is `write_verilog -decimal`.
Fixes #373.
whitequark [Wed, 20 May 2020 03:18:33 +0000 (03:18 +0000)]
hdl.ast: add const-shift operations.
Also, clean up the rotate code a bit.
Fixes #378.
whitequark [Tue, 19 May 2020 23:43:25 +0000 (23:43 +0000)]
hdl.ast: clarify docs for Value.rotate_{left,right}.
"Rotate modulo 2**len(self)" is redundant because that's just how
rotates work.
whitequark [Tue, 19 May 2020 23:40:49 +0000 (23:40 +0000)]
hdl.dsl: check for unique domain name.
Fixes #385.
whitequark [Tue, 19 May 2020 23:33:14 +0000 (23:33 +0000)]
back.rtlil: handle signed and large Instance parameters correctly.
Fixes #388.
whitequark [Mon, 4 May 2020 05:51:08 +0000 (05:51 +0000)]
tracer: fix get_var_name() to work on toplevel attributes.
E.g. this now works:
>>> class dummy: pass
>>> self = dummy()
>>> self.foo = Signal()
>>> self.foo.name
'foo'
Gwenhael Goavec-Merou [Fri, 8 May 2020 04:42:21 +0000 (06:42 +0200)]
vendor.lattice_machxo2: generate binary bitstreams.
whitequark [Sat, 2 May 2020 10:41:18 +0000 (10:41 +0000)]
plat, vendor: systematically escape net and file names in Tcl.
Before this commit, there was only occasional quoting of some names
used in any Tcl files. (I'm not sure what I was thinking.)
After this commit, any substs that may include Tcl special characters
are escaped. This does not include build names (which are explicitly
restricted to ASCII to avoid this problem), or attribute names (which
are chosen from a predefined set). Ideally we'd use a more principled
approach but Jinja2 does not support custom escaping mechanisms.
Note that Vivado restricts clock names to a more restrictive set that
forbids using Tcl special characters even when escaped.
Fixes #375.
whitequark [Tue, 28 Apr 2020 02:16:12 +0000 (02:16 +0000)]
back.rtlil: fix incorrect escaping of signed parameters.
Also, improve escaping code in general.
whitequark [Mon, 27 Apr 2020 18:06:12 +0000 (18:06 +0000)]
hdl.ast: use SignalSet, not ValueSet, for _[lr]hs_signals().
The implementation of these functions likely predates support for
{Clock,Reset}Signal() in SignalKey.
awygle [Fri, 24 Apr 2020 22:27:04 +0000 (15:27 -0700)]
lib.fifo: add r_rst output for AsyncFIFO{,Buffered}.
Fixes #181.
awygle [Fri, 24 Apr 2020 21:15:00 +0000 (14:15 -0700)]
hdl.ir: typecheck `convert(ports=)` more carefully.
The `ports` argument to the `convert` functions is a frequent hotspot of
beginner issues. Check to make sure it is either a list or a tuple, and
give an appropriately helpful error message if not.
Fixes #362.
whitequark [Fri, 24 Apr 2020 21:09:58 +0000 (21:09 +0000)]
README: link directly to Yosys build instructions.
Teguh Hofstee [Thu, 23 Apr 2020 21:46:10 +0000 (14:46 -0700)]
back.verilog: add workaround for evaluation Verific behavior.
The evaluation version of Verific prints its license information to stdout,
and since it is against the EULA to change that in any way, this behavior
is not possible to fix in Yosys. Add a workaround in nMigen instead.
Teguh Hofstee [Wed, 22 Apr 2020 12:23:14 +0000 (05:23 -0700)]
back.verilog: make Yosys version check compatible with Verific.
Kate Temkin [Mon, 20 Apr 2020 22:25:50 +0000 (16:25 -0600)]
vendor: use nextpnr -12k for -12F devices; remove theoretical devices
nextpnr now supports -12k; which replaces the use of -25k and --idcode
together to build bitstreams compatible with -12F devices. Use this.
This also removes the LFEUM-12K and its 5G counterpart; as per Dave Shah
they're currently only theoretical FPGAs.
anuejn [Thu, 16 Apr 2020 16:46:55 +0000 (18:46 +0200)]
hdl.rec: make Record inherit from UserValue.
Closes #354.
whitequark [Wed, 15 Apr 2020 14:42:46 +0000 (14:42 +0000)]
back.rtlil: translate enum decoders to Yosys enum attributes.
Fixes #254.
whitequark [Tue, 14 Apr 2020 06:17:16 +0000 (06:17 +0000)]
buil.plat: enable strict undefined behavior in Jinja2.
By default, if an operation produces an undefined value (a Jinja2
concept that corresponds to Python's KeyError, AttributeError, etc)
then this value may be printed in a template, which is a nop. This
behavior can hide bugs.
This commit changes the Jinja2 behavior to raise an error instead of
producing an undefined value in all cases. (We produce undefined
values deliberately in a few places. Those are unaffected; it is OK
to use several kinds of undefined values in one Jinja2 environment.)
Fixes #337.
whitequark [Mon, 13 Apr 2020 17:04:13 +0000 (17:04 +0000)]
back.rtlil: don't emit connections to zero width ports.
Fixes #335.
whitequark [Mon, 13 Apr 2020 16:38:36 +0000 (16:38 +0000)]
back.rtlil: refuse to create extremely large wires.
Such wires are likely to trigger pathological behavior in Yosys and,
if applicable, other toolchains that consume Verilog converted from
RTLIL.
Fixes #341.
whitequark [Mon, 13 Apr 2020 15:56:39 +0000 (15:56 +0000)]
back.rtlil: fix expansion of Part() for partial dummy writes.
Before this commit, selecting a part that was fully out of bounds of
a value was correctly implemented as a write to a dummy wire, but
selecting a part that was only partially out of bounds resulted in
a crash.
Fixes #351.
whitequark [Mon, 13 Apr 2020 14:43:43 +0000 (14:43 +0000)]
back.rtlil: fix legalization of Part() with stride.
Also known as word_select().
whitequark [Mon, 13 Apr 2020 13:03:31 +0000 (13:03 +0000)]
Clarify a few comments. NFC.
Dan Ravensloft [Mon, 13 Apr 2020 13:40:39 +0000 (14:40 +0100)]
hdl.ast: add Value.{rotate_left,rotate_right}.
whitequark [Mon, 13 Apr 2020 11:04:25 +0000 (11:04 +0000)]
Travis: require tests to pass on pypy3.
Fixes #147.
whitequark [Mon, 13 Apr 2020 09:40:00 +0000 (09:40 +0000)]
Travis: upgrade to bionic.
whitequark [Sun, 12 Apr 2020 04:56:15 +0000 (04:56 +0000)]
build.run: fix BuildProducts.extract to work with subdirectories.
Fixes #353.
whitequark [Sun, 12 Apr 2020 04:47:40 +0000 (04:47 +0000)]
hdl.rec: improve repr() for Layout.
Fixes #326.
whitequark [Sun, 12 Apr 2020 03:59:56 +0000 (03:59 +0000)]
hdl.ast: improve repr() for Shape.
The default __repr__() from typing.NamedTuple does not include
the module name, so the replacement (which uses the preferred syntax
for specifying these shapes) doesn't either.
whitequark [Sun, 12 Apr 2020 03:28:29 +0000 (03:28 +0000)]
build.plat: don't check for toolchain presence if do_build=False.
Stuart Olsen [Tue, 7 Apr 2020 11:17:14 +0000 (04:17 -0700)]
back.pysim: Clear pending updates after they are effected
Stuart Olsen [Tue, 7 Apr 2020 05:22:45 +0000 (22:22 -0700)]
back.pysim: Eliminate duplicate dict lookup in VCD update
Stuart Olsen [Tue, 7 Apr 2020 05:22:09 +0000 (22:22 -0700)]
back.pysim: Reuse clock simulation commands
whitequark [Sun, 5 Apr 2020 02:00:06 +0000 (02:00 +0000)]
hdl.mem: fix source location of ReadPort.en.
whitequark [Fri, 3 Apr 2020 05:20:42 +0000 (05:20 +0000)]
back.pysim: fix emission of undriven traces to VCD files.
This has been originally implemented in commit
d3775eed (which fixed
`write_vcd(traces=)` to do something at all), but had a flaw where
undriven traces would not be correctly placed in hierarchy. This
used to produce incorrect results on pyvcd 0.1, but started causing
assertion failures on pyvcd 0.2.
Fixes #345.
whitequark [Thu, 2 Apr 2020 11:17:41 +0000 (11:17 +0000)]
setup: bump pyvcd to ~=0.2.
We don't use any of the deprecated functionality, and the added
requirement of Python 3.6+ matches ours.
Having a requirement for pyvcd ~=0.1.4 was actually the cause of
the error I tried to fix in commit
6e1145e2. It had nothing to do
with Jinja2 (though it is definitely still good to have the tighter
requirement on Jinja2); the cause of the error was that pip would
install Jinja2, schedule installing markupsafe, install pyvcd 0.2.0
and then choke on the pyvcd 0.1.4 requirement, which would prevent
it from installing markupsafe &c. Why it does that is beyond me.
Jacob Lifshay [Thu, 2 Apr 2020 02:38:14 +0000 (19:38 -0700)]
Add support for using non-compat Elaboratable instances with compat.fhdl.verilog.convert and compat.run_simulation
Fixes #344
whitequark [Thu, 2 Apr 2020 01:35:39 +0000 (01:35 +0000)]
setup: tighten version constraint on Jinja2.
I remember thinking that not constraining it properly might bite us
someday, but assumed that Jinja2 will always stay version 2. Now it
looks like Jinja2 3.0.0a1 got released, pip picks it by default, and
it's currently broken (something about markupsafe missing).
Do what needed to be done in the first place.
whitequark [Sun, 22 Mar 2020 20:50:07 +0000 (20:50 +0000)]
hdl.ast: implement abs() on values.
WRansohoff [Fri, 20 Mar 2020 08:10:48 +0000 (04:10 -0400)]
vendor.lattice_ice40: add support for SB_[LH]FOSC as default_clk.
These oscillators are only available on iCE40 UltraPlus devices.