yosys.git
10 years agoAdded "stat -width"
Clifford Wolf [Fri, 22 Aug 2014 15:20:28 +0000 (17:20 +0200)]
Added "stat -width"

10 years agoAdded emscripten (emcc) support to build system and some build fixes
Clifford Wolf [Fri, 22 Aug 2014 14:09:13 +0000 (16:09 +0200)]
Added emscripten (emcc) support to build system and some build fixes

10 years agoAdded DPI-C documentation to README file
Clifford Wolf [Fri, 22 Aug 2014 12:37:14 +0000 (14:37 +0200)]
Added DPI-C documentation to README file

10 years agoAdded support for non-standard <plugin>:<c_name> DPI syntax
Clifford Wolf [Fri, 22 Aug 2014 12:30:29 +0000 (14:30 +0200)]
Added support for non-standard <plugin>:<c_name> DPI syntax

10 years agoArchibald Rust and Clifford Wolf: ffi-based dpi_call()
Clifford Wolf [Fri, 22 Aug 2014 12:22:09 +0000 (14:22 +0200)]
Archibald Rust and Clifford Wolf: ffi-based dpi_call()

10 years agoAdded "plugin" command
Clifford Wolf [Fri, 22 Aug 2014 11:58:36 +0000 (13:58 +0200)]
Added "plugin" command

10 years agoUpdated ABC to 4d547a5e065b
Clifford Wolf [Fri, 22 Aug 2014 10:20:23 +0000 (12:20 +0200)]
Updated ABC to 4d547a5e065b

10 years agoCosmetic changes to FSM tests
Clifford Wolf [Thu, 21 Aug 2014 15:40:49 +0000 (17:40 +0200)]
Cosmetic changes to FSM tests

10 years agoFixed small memory leak in ast simplify
Clifford Wolf [Thu, 21 Aug 2014 15:33:40 +0000 (17:33 +0200)]
Fixed small memory leak in ast simplify

10 years agoAdded support for DPI function with different names in C and Verilog
Clifford Wolf [Thu, 21 Aug 2014 15:22:04 +0000 (17:22 +0200)]
Added support for DPI function with different names in C and Verilog

10 years agoAdded AstNode::asInt()
Clifford Wolf [Thu, 21 Aug 2014 15:11:51 +0000 (17:11 +0200)]
Added AstNode::asInt()

10 years agoFixed memory leak in DPI function calls
Clifford Wolf [Thu, 21 Aug 2014 11:09:47 +0000 (13:09 +0200)]
Fixed memory leak in DPI function calls

10 years agoMerge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Thu, 21 Aug 2014 10:58:16 +0000 (12:58 +0200)]
Merge branch 'master' of github.com:cliffordwolf/yosys

10 years agoAdded Verilog/AST support for DPI functions (dpi_call() still unimplemented)
Clifford Wolf [Thu, 21 Aug 2014 10:43:51 +0000 (12:43 +0200)]
Added Verilog/AST support for DPI functions (dpi_call() still unimplemented)

10 years agoAdded support for global tasks and functions
Clifford Wolf [Thu, 21 Aug 2014 10:42:28 +0000 (12:42 +0200)]
Added support for global tasks and functions

10 years agoAdded mod->addGate() methods for new gate types
Clifford Wolf [Tue, 19 Aug 2014 11:44:56 +0000 (13:44 +0200)]
Added mod->addGate() methods for new gate types

10 years agoUsing "via_celltype" in $mul carry-save-acc implementation
Clifford Wolf [Mon, 18 Aug 2014 12:30:20 +0000 (14:30 +0200)]
Using "via_celltype" in $mul carry-save-acc implementation

10 years agoAdded "via_celltype" attribute on task/func
Clifford Wolf [Mon, 18 Aug 2014 12:29:30 +0000 (14:29 +0200)]
Added "via_celltype" attribute on task/func

10 years agoPerformance fix for new $__lcu techmap rule
Clifford Wolf [Sun, 17 Aug 2014 22:27:54 +0000 (00:27 +0200)]
Performance fix for new $__lcu techmap rule

10 years agoReplaced recursive lcu scheme with bk adder
Clifford Wolf [Sun, 17 Aug 2014 22:03:33 +0000 (00:03 +0200)]
Replaced recursive lcu scheme with bk adder

10 years agoAdded const folding of AST_CASE to AST simplifier
Clifford Wolf [Sun, 17 Aug 2014 22:02:30 +0000 (00:02 +0200)]
Added const folding of AST_CASE to AST simplifier

10 years agoFixed proc_{self,share}_dirname error handling
Clifford Wolf [Sun, 17 Aug 2014 00:25:59 +0000 (02:25 +0200)]
Fixed proc_{self,share}_dirname error handling

10 years agoMakefile fixes
Clifford Wolf [Sun, 17 Aug 2014 00:24:53 +0000 (02:24 +0200)]
Makefile fixes

10 years agoImproved AST ProcessGenerator performance
Clifford Wolf [Sun, 17 Aug 2014 00:17:49 +0000 (02:17 +0200)]
Improved AST ProcessGenerator performance

10 years agoImproved sig.remove2() performance
Clifford Wolf [Sun, 17 Aug 2014 00:16:56 +0000 (02:16 +0200)]
Improved sig.remove2() performance

10 years agoUse stackmap<> in AST ProcessGenerator
Clifford Wolf [Sat, 16 Aug 2014 22:57:24 +0000 (00:57 +0200)]
Use stackmap<> in AST ProcessGenerator

10 years agoAdded stackmap<> container
Clifford Wolf [Sat, 16 Aug 2014 22:56:47 +0000 (00:56 +0200)]
Added stackmap<> container

10 years agoRenamed toposort.h to utils.h
Clifford Wolf [Sat, 16 Aug 2014 22:55:35 +0000 (00:55 +0200)]
Renamed toposort.h to utils.h

10 years agoAdded module->uniquify()
Clifford Wolf [Sat, 16 Aug 2014 21:50:36 +0000 (23:50 +0200)]
Added module->uniquify()

10 years agoFixed AOI/OAI expr handling in verilog backend
Clifford Wolf [Sat, 16 Aug 2014 20:05:09 +0000 (22:05 +0200)]
Fixed AOI/OAI expr handling in verilog backend

10 years agoMultiply using a carry-save accumulator
Clifford Wolf [Sat, 16 Aug 2014 19:07:29 +0000 (21:07 +0200)]
Multiply using a carry-save accumulator

10 years agoAdded "test_cell -s <seed>"
Clifford Wolf [Sat, 16 Aug 2014 17:44:31 +0000 (19:44 +0200)]
Added "test_cell -s <seed>"

10 years agoAST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map
Clifford Wolf [Sat, 16 Aug 2014 17:31:59 +0000 (19:31 +0200)]
AST ProcessGenerator: replaced subst_*_{from,to} with subst_*_map

10 years agoAdded additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
Clifford Wolf [Sat, 16 Aug 2014 16:18:30 +0000 (18:18 +0200)]
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_

10 years agoAdded CellTypes::cell_evaluable()
Clifford Wolf [Sat, 16 Aug 2014 14:12:14 +0000 (16:12 +0200)]
Added CellTypes::cell_evaluable()

10 years agoChanges in techmap $__alu interface
Clifford Wolf [Sat, 16 Aug 2014 14:01:58 +0000 (16:01 +0200)]
Changes in techmap $__alu interface

10 years agoAdded "opt -fast"
Clifford Wolf [Sat, 16 Aug 2014 13:34:15 +0000 (15:34 +0200)]
Added "opt -fast"

10 years agoAdded log_spacer()
Clifford Wolf [Sat, 16 Aug 2014 13:34:00 +0000 (15:34 +0200)]
Added log_spacer()

10 years agoBugfix in iopadmap
Clifford Wolf [Fri, 15 Aug 2014 12:29:42 +0000 (14:29 +0200)]
Bugfix in iopadmap

10 years agoRenamed $lut ports to follow A-Y naming scheme
Clifford Wolf [Fri, 15 Aug 2014 12:18:40 +0000 (14:18 +0200)]
Renamed $lut ports to follow A-Y naming scheme

10 years agoRenamed $_INV_ cell type to $_NOT_
Clifford Wolf [Fri, 15 Aug 2014 12:11:40 +0000 (14:11 +0200)]
Renamed $_INV_ cell type to $_NOT_

10 years agoRemoved old doc references to $safe_pmux
Clifford Wolf [Fri, 15 Aug 2014 12:04:35 +0000 (14:04 +0200)]
Removed old doc references to $safe_pmux

10 years agoMore idstring sort_by_* helpers and fixed tpl ordering in techmap
Clifford Wolf [Fri, 15 Aug 2014 00:40:46 +0000 (02:40 +0200)]
More idstring sort_by_* helpers and fixed tpl ordering in techmap

10 years agoAdded Frontend "+/" filename syntax for files from proc_share_dir
Clifford Wolf [Fri, 15 Aug 2014 00:08:02 +0000 (02:08 +0200)]
Added Frontend "+/" filename syntax for files from proc_share_dir

10 years agodocument "techmap -map %<design-name>"
Clifford Wolf [Fri, 15 Aug 2014 00:00:53 +0000 (02:00 +0200)]
document "techmap -map %<design-name>"

10 years agoFixed bug in "read_verilog -ignore_redef"
Clifford Wolf [Thu, 14 Aug 2014 23:53:22 +0000 (01:53 +0200)]
Fixed bug in "read_verilog -ignore_redef"

10 years agoAdded RTLIL::SigSpec::to_sigbit_map()
Clifford Wolf [Thu, 14 Aug 2014 21:14:47 +0000 (23:14 +0200)]
Added RTLIL::SigSpec::to_sigbit_map()

10 years agoChanged the AST genWidthRTLIL subst interface to use a std::map
Clifford Wolf [Thu, 14 Aug 2014 21:02:07 +0000 (23:02 +0200)]
Changed the AST genWidthRTLIL subst interface to use a std::map

10 years agoAdded sig.{replace,remove,extract} variants for std::{map,set} pattern
Clifford Wolf [Thu, 14 Aug 2014 20:32:18 +0000 (22:32 +0200)]
Added sig.{replace,remove,extract} variants for std::{map,set} pattern

10 years agoFixed line numbers when using here-doc macros
Clifford Wolf [Thu, 14 Aug 2014 20:26:30 +0000 (22:26 +0200)]
Fixed line numbers when using here-doc macros

10 years agoFixed handling of task outputs
Clifford Wolf [Thu, 14 Aug 2014 20:26:10 +0000 (22:26 +0200)]
Fixed handling of task outputs

10 years agoSimplified $__arraymul techmap rule
Clifford Wolf [Thu, 14 Aug 2014 18:53:21 +0000 (20:53 +0200)]
Simplified $__arraymul techmap rule

10 years agoAdded module->ports
Clifford Wolf [Thu, 14 Aug 2014 14:13:42 +0000 (16:13 +0200)]
Added module->ports

10 years agoRefactoring of CellType class
Clifford Wolf [Thu, 14 Aug 2014 13:46:51 +0000 (15:46 +0200)]
Refactoring of CellType class

10 years agoRIP $safe_pmux
Clifford Wolf [Thu, 14 Aug 2014 09:39:46 +0000 (11:39 +0200)]
RIP $safe_pmux

10 years agoSome improvements in FSM mapping and recoding
Clifford Wolf [Thu, 14 Aug 2014 09:22:45 +0000 (11:22 +0200)]
Some improvements in FSM mapping and recoding

10 years agoAdded "abc -D" for setting delay target
Clifford Wolf [Thu, 14 Aug 2014 09:05:25 +0000 (11:05 +0200)]
Added "abc -D" for setting delay target

10 years agoUpdated ABC to 4935c2b946de
Clifford Wolf [Thu, 14 Aug 2014 08:19:12 +0000 (10:19 +0200)]
Updated ABC to 4935c2b946de

10 years agoAdded techmap support for actual lookahead carry unit
Clifford Wolf [Wed, 13 Aug 2014 16:40:57 +0000 (18:40 +0200)]
Added techmap support for actual lookahead carry unit

10 years agoPreparations for lookahead ALU support in techmap.v
Clifford Wolf [Wed, 13 Aug 2014 14:36:30 +0000 (16:36 +0200)]
Preparations for lookahead ALU support in techmap.v

10 years agoFilter ANSI escape sequences from ABC output
Clifford Wolf [Wed, 13 Aug 2014 11:40:29 +0000 (13:40 +0200)]
Filter ANSI escape sequences from ABC output

10 years agoNew interface for $__alu in techmap.v
Clifford Wolf [Wed, 13 Aug 2014 11:04:28 +0000 (13:04 +0200)]
New interface for $__alu in techmap.v

10 years agoAdded support for non-standard """ macro bodies
Clifford Wolf [Wed, 13 Aug 2014 11:03:38 +0000 (13:03 +0200)]
Added support for non-standard """ macro bodies

10 years agoFixed handling of constant-true branches in proc_clean
Clifford Wolf [Tue, 12 Aug 2014 15:35:22 +0000 (17:35 +0200)]
Fixed handling of constant-true branches in proc_clean

10 years agoAdded test_verific mode to tests/fsm/generate.py
Clifford Wolf [Tue, 12 Aug 2014 13:43:30 +0000 (15:43 +0200)]
Added test_verific mode to tests/fsm/generate.py

10 years agoFixed SigBit(RTLIL::Wire *wire) constructor
Clifford Wolf [Tue, 12 Aug 2014 13:39:48 +0000 (15:39 +0200)]
Fixed SigBit(RTLIL::Wire *wire) constructor

10 years agoFixed building verific bindings
Clifford Wolf [Tue, 12 Aug 2014 13:21:06 +0000 (15:21 +0200)]
Fixed building verific bindings

10 years agoAdded multi-dim memory test (requires iverilog git head)
Clifford Wolf [Tue, 12 Aug 2014 08:37:47 +0000 (10:37 +0200)]
Added multi-dim memory test (requires iverilog git head)

10 years agoAnother build fix by americanrouter (via reddit)
Clifford Wolf [Mon, 11 Aug 2014 13:55:41 +0000 (15:55 +0200)]
Another build fix by americanrouter (via reddit)

10 years agoFixed FSM mapping for multiple reset-like signals
Clifford Wolf [Sun, 10 Aug 2014 10:04:02 +0000 (12:04 +0200)]
Fixed FSM mapping for multiple reset-like signals

10 years agoFixed "share" for complex scenarios with never-active cells
Clifford Wolf [Sat, 9 Aug 2014 15:07:20 +0000 (17:07 +0200)]
Fixed "share" for complex scenarios with never-active cells

10 years agoDo not share any $reduce_* cells (its complicated and not worth it anyways)
Clifford Wolf [Sat, 9 Aug 2014 13:17:54 +0000 (15:17 +0200)]
Do not share any $reduce_* cells (its complicated and not worth it anyways)

10 years agoSome improvements in fsm_opt and fsm_map for FSM with unreachable states
Clifford Wolf [Sat, 9 Aug 2014 12:49:51 +0000 (14:49 +0200)]
Some improvements in fsm_opt and fsm_map for FSM with unreachable states

10 years agoImproved FSM tests
Clifford Wolf [Fri, 8 Aug 2014 12:30:45 +0000 (14:30 +0200)]
Improved FSM tests

10 years agoAnother fsm_extract bugfix
Clifford Wolf [Fri, 8 Aug 2014 12:55:11 +0000 (14:55 +0200)]
Another fsm_extract bugfix

10 years agoFixed "fsm -export"
Clifford Wolf [Fri, 8 Aug 2014 12:49:06 +0000 (14:49 +0200)]
Fixed "fsm -export"

10 years agoFixed sharing of reduce operator
Clifford Wolf [Fri, 8 Aug 2014 12:24:09 +0000 (14:24 +0200)]
Fixed sharing of reduce operator

10 years agoFixed fsm_extract for wreduced muxes
Clifford Wolf [Fri, 8 Aug 2014 11:47:20 +0000 (13:47 +0200)]
Fixed fsm_extract for wreduced muxes

10 years agoAdded FSM test bench
Clifford Wolf [Fri, 8 Aug 2014 11:12:18 +0000 (13:12 +0200)]
Added FSM test bench

10 years agoAdded "sat -prove-skip"
Clifford Wolf [Fri, 8 Aug 2014 11:11:54 +0000 (13:11 +0200)]
Added "sat -prove-skip"

10 years agoFixed build with gcc-4.6
Clifford Wolf [Thu, 7 Aug 2014 20:37:01 +0000 (22:37 +0200)]
Fixed build with gcc-4.6

10 years agoUse "-keepdc" in "miter -equiv -flatten"
Clifford Wolf [Thu, 7 Aug 2014 14:42:35 +0000 (16:42 +0200)]
Use "-keepdc" in "miter -equiv -flatten"

10 years agoAlso allow "module foobar(input foo, output bar, ...);" syntax
Clifford Wolf [Thu, 7 Aug 2014 14:41:27 +0000 (16:41 +0200)]
Also allow "module foobar(input foo, output bar, ...);" syntax

10 years agoAdded adff2dff.v (for techmap -share_map)
Clifford Wolf [Thu, 7 Aug 2014 14:14:38 +0000 (16:14 +0200)]
Added adff2dff.v (for techmap -share_map)

10 years agoAdded AST_MULTIRANGE (arrays with more than 1 dimension)
Clifford Wolf [Wed, 6 Aug 2014 13:43:46 +0000 (15:43 +0200)]
Added AST_MULTIRANGE (arrays with more than 1 dimension)

10 years agoVarious improvements in memory_dff pass
Clifford Wolf [Wed, 6 Aug 2014 12:31:38 +0000 (14:31 +0200)]
Various improvements in memory_dff pass

10 years agoVarious fixes and improvements in wreduce pass
Clifford Wolf [Tue, 5 Aug 2014 17:01:41 +0000 (19:01 +0200)]
Various fixes and improvements in wreduce pass

10 years agoRemoved old "constmap" from wreduce code
Clifford Wolf [Tue, 5 Aug 2014 14:53:53 +0000 (16:53 +0200)]
Removed old "constmap" from wreduce code

10 years agoAdded support for truncating of wires to wreduce pass
Clifford Wolf [Tue, 5 Aug 2014 12:47:03 +0000 (14:47 +0200)]
Added support for truncating of wires to wreduce pass

10 years agoCleanups and improvements in wreduce pass
Clifford Wolf [Tue, 5 Aug 2014 11:11:04 +0000 (13:11 +0200)]
Cleanups and improvements in wreduce pass

10 years agoAdded mux support to wreduce command
Clifford Wolf [Tue, 5 Aug 2014 10:49:53 +0000 (12:49 +0200)]
Added mux support to wreduce command

10 years agoImproved scope resolution of local regs in Verilog+AST frontend
Clifford Wolf [Tue, 5 Aug 2014 10:15:53 +0000 (12:15 +0200)]
Improved scope resolution of local regs in Verilog+AST frontend

10 years agoFixed AST handling of variables declared inside a functions main block
Clifford Wolf [Tue, 5 Aug 2014 06:35:51 +0000 (08:35 +0200)]
Fixed AST handling of variables declared inside a functions main block

10 years agoAdded "show -signed"
Clifford Wolf [Mon, 4 Aug 2014 13:33:51 +0000 (15:33 +0200)]
Added "show -signed"

10 years agoAdded support for non-standard "module mod_name(...);" syntax
Clifford Wolf [Mon, 4 Aug 2014 13:19:24 +0000 (15:19 +0200)]
Added support for non-standard "module mod_name(...);" syntax

10 years agoAdded RTLIL::IdString::in(...)
Clifford Wolf [Mon, 4 Aug 2014 13:08:35 +0000 (15:08 +0200)]
Added RTLIL::IdString::in(...)

10 years agoFixed "share" for memory read ports
Clifford Wolf [Sun, 3 Aug 2014 18:19:50 +0000 (20:19 +0200)]
Fixed "share" for memory read ports

10 years agoAdded "wreduce" to some of the standard test benches
Clifford Wolf [Sun, 3 Aug 2014 18:03:16 +0000 (20:03 +0200)]
Added "wreduce" to some of the standard test benches

10 years agoProgress in "wreduce" pass
Clifford Wolf [Sun, 3 Aug 2014 18:02:42 +0000 (20:02 +0200)]
Progress in "wreduce" pass

10 years agoAdded "wreduce" command (work in progress)
Clifford Wolf [Sun, 3 Aug 2014 13:02:05 +0000 (15:02 +0200)]
Added "wreduce" command (work in progress)