1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_context.h"
29 #include "intel_batchbuffer.h"
30 #include "intel_buffer_objects.h"
31 #include "intel_decode.h"
32 #include "intel_reg.h"
33 #include "intel_bufmgr.h"
34 #include "intel_buffers.h"
36 struct cached_batch_item
{
37 struct cached_batch_item
*next
;
42 static void clear_cache( struct intel_context
*intel
)
44 struct cached_batch_item
*item
= intel
->batch
.cached_items
;
47 struct cached_batch_item
*next
= item
->next
;
52 intel
->batch
.cached_items
= NULL
;
56 intel_batchbuffer_init(struct intel_context
*intel
)
58 intel_batchbuffer_reset(intel
);
60 if (intel
->gen
== 6) {
61 /* We can't just use brw_state_batch to get a chunk of space for
62 * the gen6 workaround because it involves actually writing to
63 * the buffer, and the kernel doesn't let us write to the batch.
65 intel
->batch
.workaround_bo
= drm_intel_bo_alloc(intel
->bufmgr
,
72 intel_batchbuffer_reset(struct intel_context
*intel
)
74 if (intel
->batch
.last_bo
!= NULL
) {
75 drm_intel_bo_unreference(intel
->batch
.last_bo
);
76 intel
->batch
.last_bo
= NULL
;
78 intel
->batch
.last_bo
= intel
->batch
.bo
;
82 intel
->batch
.bo
= drm_intel_bo_alloc(intel
->bufmgr
, "batchbuffer",
83 intel
->maxBatchSize
, 4096);
85 intel
->batch
.reserved_space
= BATCH_RESERVED
;
86 intel
->batch
.state_batch_offset
= intel
->batch
.bo
->size
;
87 intel
->batch
.used
= 0;
91 intel_batchbuffer_free(struct intel_context
*intel
)
93 drm_intel_bo_unreference(intel
->batch
.last_bo
);
94 drm_intel_bo_unreference(intel
->batch
.bo
);
95 drm_intel_bo_unreference(intel
->batch
.workaround_bo
);
100 /* TODO: Push this whole function into bufmgr.
103 do_flush_locked(struct intel_context
*intel
)
105 struct intel_batchbuffer
*batch
= &intel
->batch
;
108 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4*batch
->used
, batch
->map
);
109 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
110 ret
= drm_intel_bo_subdata(batch
->bo
,
111 batch
->state_batch_offset
,
112 batch
->bo
->size
- batch
->state_batch_offset
,
113 (char *)batch
->map
+ batch
->state_batch_offset
);
116 if (!intel
->intelScreen
->no_hw
) {
119 if (intel
->gen
< 6 || !batch
->is_blit
) {
120 ring
= I915_EXEC_RENDER
;
122 ring
= I915_EXEC_BLT
;
126 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4*batch
->used
, NULL
, 0, 0, ring
);
129 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
130 drm_intel_bo_map(batch
->bo
, false);
131 intel_decode(batch
->bo
->virtual, batch
->used
,
133 intel
->intelScreen
->deviceID
, GL_TRUE
);
134 drm_intel_bo_unmap(batch
->bo
);
136 if (intel
->vtbl
.debug_batch
!= NULL
)
137 intel
->vtbl
.debug_batch(intel
);
141 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(ret
));
144 intel
->vtbl
.new_batch(intel
);
148 _intel_batchbuffer_flush(struct intel_context
*intel
,
149 const char *file
, int line
)
151 if (intel
->batch
.used
== 0)
154 if (intel
->first_post_swapbuffers_batch
== NULL
) {
155 intel
->first_post_swapbuffers_batch
= intel
->batch
.bo
;
156 drm_intel_bo_reference(intel
->first_post_swapbuffers_batch
);
159 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
160 fprintf(stderr
, "%s:%d: Batchbuffer flush with %db used\n", file
, line
,
161 4*intel
->batch
.used
);
163 intel
->batch
.reserved_space
= 0;
165 if (intel
->always_flush_cache
) {
166 intel_batchbuffer_emit_mi_flush(intel
);
169 /* Mark the end of the buffer. */
170 intel_batchbuffer_emit_dword(intel
, MI_BATCH_BUFFER_END
);
171 if (intel
->batch
.used
& 1) {
172 /* Round batchbuffer usage to 2 DWORDs. */
173 intel_batchbuffer_emit_dword(intel
, MI_NOOP
);
176 if (intel
->vtbl
.finish_batch
)
177 intel
->vtbl
.finish_batch(intel
);
179 intel_upload_finish(intel
);
181 /* Check that we didn't just wrap our batchbuffer at a bad time. */
182 assert(!intel
->no_batch_wrap
);
184 do_flush_locked(intel
);
186 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
187 fprintf(stderr
, "waiting for idle\n");
188 drm_intel_bo_wait_rendering(intel
->batch
.bo
);
193 intel_batchbuffer_reset(intel
);
197 /* This is the only way buffers get added to the validate list.
200 intel_batchbuffer_emit_reloc(struct intel_context
*intel
,
201 drm_intel_bo
*buffer
,
202 uint32_t read_domains
, uint32_t write_domain
,
207 ret
= drm_intel_bo_emit_reloc(intel
->batch
.bo
, 4*intel
->batch
.used
,
209 read_domains
, write_domain
);
214 * Using the old buffer offset, write in what the right data would be, in case
215 * the buffer doesn't move and we can short-circuit the relocation processing
218 intel_batchbuffer_emit_dword(intel
, buffer
->offset
+ delta
);
224 intel_batchbuffer_emit_reloc_fenced(struct intel_context
*intel
,
225 drm_intel_bo
*buffer
,
226 uint32_t read_domains
,
227 uint32_t write_domain
,
232 ret
= drm_intel_bo_emit_reloc_fence(intel
->batch
.bo
, 4*intel
->batch
.used
,
234 read_domains
, write_domain
);
239 * Using the old buffer offset, write in what the right data would
240 * be, in case the buffer doesn't move and we can short-circuit the
241 * relocation processing in the kernel
243 intel_batchbuffer_emit_dword(intel
, buffer
->offset
+ delta
);
249 intel_batchbuffer_data(struct intel_context
*intel
,
250 const void *data
, GLuint bytes
, bool is_blit
)
252 assert((bytes
& 3) == 0);
253 intel_batchbuffer_require_space(intel
, bytes
, is_blit
);
254 __memcpy(intel
->batch
.map
+ intel
->batch
.used
, data
, bytes
);
255 intel
->batch
.used
+= bytes
>> 2;
259 intel_batchbuffer_cached_advance(struct intel_context
*intel
)
261 struct cached_batch_item
**prev
= &intel
->batch
.cached_items
, *item
;
262 uint32_t sz
= (intel
->batch
.used
- intel
->batch
.emit
) * sizeof(uint32_t);
263 uint32_t *start
= intel
->batch
.map
+ intel
->batch
.emit
;
264 uint16_t op
= *start
>> 16;
270 old
= intel
->batch
.map
+ item
->header
;
271 if (op
== *old
>> 16) {
272 if (item
->size
== sz
&& memcmp(old
, start
, sz
) == 0) {
273 if (prev
!= &intel
->batch
.cached_items
) {
275 item
->next
= intel
->batch
.cached_items
;
276 intel
->batch
.cached_items
= item
;
278 intel
->batch
.used
= intel
->batch
.emit
;
287 item
= malloc(sizeof(struct cached_batch_item
));
291 item
->next
= intel
->batch
.cached_items
;
292 intel
->batch
.cached_items
= item
;
296 item
->header
= intel
->batch
.emit
;
300 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
301 * implementing two workarounds on gen6. From section 1.4.7.1
302 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
304 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
305 * produced by non-pipelined state commands), software needs to first
306 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
309 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
310 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
312 * And the workaround for these two requires this workaround first:
314 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
315 * BEFORE the pipe-control with a post-sync op and no write-cache
318 * And this last workaround is tricky because of the requirements on
319 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
322 * "1 of the following must also be set:
323 * - Render Target Cache Flush Enable ([12] of DW1)
324 * - Depth Cache Flush Enable ([0] of DW1)
325 * - Stall at Pixel Scoreboard ([1] of DW1)
326 * - Depth Stall ([13] of DW1)
327 * - Post-Sync Operation ([13] of DW1)
328 * - Notify Enable ([8] of DW1)"
330 * The cache flushes require the workaround flush that triggered this
331 * one, so we can't use it. Depth stall would trigger the same.
332 * Post-sync nonzero is what triggered this second workaround, so we
333 * can't use that one either. Notify enable is IRQs, which aren't
334 * really our business. That leaves only stall at scoreboard.
337 intel_emit_post_sync_nonzero_flush(struct intel_context
*intel
)
339 if (!intel
->batch
.need_workaround_flush
)
343 OUT_BATCH(_3DSTATE_PIPE_CONTROL
);
344 OUT_BATCH(PIPE_CONTROL_CS_STALL
|
345 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
346 OUT_BATCH(0); /* address */
347 OUT_BATCH(0); /* write data */
351 OUT_BATCH(_3DSTATE_PIPE_CONTROL
);
352 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE
);
353 OUT_RELOC(intel
->batch
.workaround_bo
,
354 I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
, 0);
355 OUT_BATCH(0); /* write data */
358 intel
->batch
.need_workaround_flush
= false;
361 /* Emit a pipelined flush to either flush render and texture cache for
362 * reading from a FBO-drawn texture, or flush so that frontbuffer
363 * render appears on the screen in DRI1.
365 * This is also used for the always_flush_cache driconf debug option.
368 intel_batchbuffer_emit_mi_flush(struct intel_context
*intel
)
370 if (intel
->gen
>= 6) {
371 if (intel
->batch
.is_blit
) {
373 OUT_BATCH(MI_FLUSH_DW
);
379 if (intel
->gen
== 6) {
380 /* Hardware workaround: SNB B-Spec says:
382 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
383 * Flush Enable =1, a PIPE_CONTROL with any non-zero
384 * post-sync-op is required.
386 intel_emit_post_sync_nonzero_flush(intel
);
390 OUT_BATCH(_3DSTATE_PIPE_CONTROL
);
391 OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH
|
392 PIPE_CONTROL_WRITE_FLUSH
|
393 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
394 PIPE_CONTROL_TC_FLUSH
|
395 PIPE_CONTROL_NO_WRITE
);
396 OUT_BATCH(0); /* write address */
397 OUT_BATCH(0); /* write data */
400 } else if (intel
->gen
>= 4) {
402 OUT_BATCH(_3DSTATE_PIPE_CONTROL
|
403 PIPE_CONTROL_WRITE_FLUSH
|
404 PIPE_CONTROL_NO_WRITE
);
405 OUT_BATCH(0); /* write address */
406 OUT_BATCH(0); /* write data */
407 OUT_BATCH(0); /* write data */