1 /**************************************************************************
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "intel_context.h"
29 #include "intel_batchbuffer.h"
30 #include "intel_buffer_objects.h"
31 #include "intel_decode.h"
32 #include "intel_reg.h"
33 #include "intel_bufmgr.h"
34 #include "intel_buffers.h"
36 struct cached_batch_item
{
37 struct cached_batch_item
*next
;
42 static void clear_cache( struct intel_context
*intel
)
44 struct cached_batch_item
*item
= intel
->batch
.cached_items
;
47 struct cached_batch_item
*next
= item
->next
;
52 intel
->batch
.cached_items
= NULL
;
56 intel_batchbuffer_init(struct intel_context
*intel
)
58 intel_batchbuffer_reset(intel
);
60 if (intel
->gen
== 6) {
61 /* We can't just use brw_state_batch to get a chunk of space for
62 * the gen6 workaround because it involves actually writing to
63 * the buffer, and the kernel doesn't let us write to the batch.
65 intel
->batch
.workaround_bo
= drm_intel_bo_alloc(intel
->bufmgr
,
72 intel_batchbuffer_reset(struct intel_context
*intel
)
74 if (intel
->batch
.last_bo
!= NULL
) {
75 drm_intel_bo_unreference(intel
->batch
.last_bo
);
76 intel
->batch
.last_bo
= NULL
;
78 intel
->batch
.last_bo
= intel
->batch
.bo
;
82 intel
->batch
.bo
= drm_intel_bo_alloc(intel
->bufmgr
, "batchbuffer",
83 intel
->maxBatchSize
, 4096);
85 intel
->batch
.reserved_space
= BATCH_RESERVED
;
86 intel
->batch
.state_batch_offset
= intel
->batch
.bo
->size
;
87 intel
->batch
.used
= 0;
91 intel_batchbuffer_save_state(struct intel_context
*intel
)
93 intel
->batch
.saved
.used
= intel
->batch
.used
;
94 intel
->batch
.saved
.reloc_count
=
95 drm_intel_gem_bo_get_reloc_count(intel
->batch
.bo
);
99 intel_batchbuffer_reset_to_saved(struct intel_context
*intel
)
101 drm_intel_gem_bo_clear_relocs(intel
->batch
.bo
, intel
->batch
.saved
.reloc_count
);
103 intel
->batch
.used
= intel
->batch
.saved
.used
;
105 /* Cached batch state is dead, since we just cleared some unknown part of the
106 * batchbuffer. Assume that the caller resets any other state necessary.
112 intel_batchbuffer_free(struct intel_context
*intel
)
114 drm_intel_bo_unreference(intel
->batch
.last_bo
);
115 drm_intel_bo_unreference(intel
->batch
.bo
);
116 drm_intel_bo_unreference(intel
->batch
.workaround_bo
);
121 /* TODO: Push this whole function into bufmgr.
124 do_flush_locked(struct intel_context
*intel
)
126 struct intel_batchbuffer
*batch
= &intel
->batch
;
129 ret
= drm_intel_bo_subdata(batch
->bo
, 0, 4*batch
->used
, batch
->map
);
130 if (ret
== 0 && batch
->state_batch_offset
!= batch
->bo
->size
) {
131 ret
= drm_intel_bo_subdata(batch
->bo
,
132 batch
->state_batch_offset
,
133 batch
->bo
->size
- batch
->state_batch_offset
,
134 (char *)batch
->map
+ batch
->state_batch_offset
);
137 if (!intel
->intelScreen
->no_hw
) {
140 if (intel
->gen
< 6 || !batch
->is_blit
) {
141 ring
= I915_EXEC_RENDER
;
143 ring
= I915_EXEC_BLT
;
147 ret
= drm_intel_bo_mrb_exec(batch
->bo
, 4*batch
->used
, NULL
, 0, 0, ring
);
150 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
)) {
151 drm_intel_bo_map(batch
->bo
, false);
152 intel_decode(batch
->bo
->virtual, batch
->used
,
154 intel
->intelScreen
->deviceID
, true);
155 drm_intel_bo_unmap(batch
->bo
);
157 if (intel
->vtbl
.debug_batch
!= NULL
)
158 intel
->vtbl
.debug_batch(intel
);
162 fprintf(stderr
, "intel_do_flush_locked failed: %s\n", strerror(-ret
));
165 intel
->vtbl
.new_batch(intel
);
171 _intel_batchbuffer_flush(struct intel_context
*intel
,
172 const char *file
, int line
)
176 /* No batch should be emitted that uses a mapped region, because that would
177 * cause the map to be incoherent with GPU rendering done by the
178 * batchbuffer. To ensure that condition, we assert a condition that is
179 * stronger but easier to implement: that *no* region is mapped.
181 assert(intel
->num_mapped_regions
== 0);
183 if (intel
->batch
.used
== 0)
186 if (intel
->first_post_swapbuffers_batch
== NULL
) {
187 intel
->first_post_swapbuffers_batch
= intel
->batch
.bo
;
188 drm_intel_bo_reference(intel
->first_post_swapbuffers_batch
);
191 if (unlikely(INTEL_DEBUG
& DEBUG_BATCH
))
192 fprintf(stderr
, "%s:%d: Batchbuffer flush with %db used\n", file
, line
,
193 4*intel
->batch
.used
);
195 intel
->batch
.reserved_space
= 0;
197 /* Mark the end of the buffer. */
198 intel_batchbuffer_emit_dword(intel
, MI_BATCH_BUFFER_END
);
199 if (intel
->batch
.used
& 1) {
200 /* Round batchbuffer usage to 2 DWORDs. */
201 intel_batchbuffer_emit_dword(intel
, MI_NOOP
);
204 if (intel
->vtbl
.finish_batch
)
205 intel
->vtbl
.finish_batch(intel
);
207 intel_upload_finish(intel
);
209 /* Check that we didn't just wrap our batchbuffer at a bad time. */
210 assert(!intel
->no_batch_wrap
);
212 ret
= do_flush_locked(intel
);
214 if (unlikely(INTEL_DEBUG
& DEBUG_SYNC
)) {
215 fprintf(stderr
, "waiting for idle\n");
216 drm_intel_bo_wait_rendering(intel
->batch
.bo
);
221 intel_batchbuffer_reset(intel
);
227 /* This is the only way buffers get added to the validate list.
230 intel_batchbuffer_emit_reloc(struct intel_context
*intel
,
231 drm_intel_bo
*buffer
,
232 uint32_t read_domains
, uint32_t write_domain
,
237 ret
= drm_intel_bo_emit_reloc(intel
->batch
.bo
, 4*intel
->batch
.used
,
239 read_domains
, write_domain
);
244 * Using the old buffer offset, write in what the right data would be, in case
245 * the buffer doesn't move and we can short-circuit the relocation processing
248 intel_batchbuffer_emit_dword(intel
, buffer
->offset
+ delta
);
254 intel_batchbuffer_emit_reloc_fenced(struct intel_context
*intel
,
255 drm_intel_bo
*buffer
,
256 uint32_t read_domains
,
257 uint32_t write_domain
,
262 ret
= drm_intel_bo_emit_reloc_fence(intel
->batch
.bo
, 4*intel
->batch
.used
,
264 read_domains
, write_domain
);
269 * Using the old buffer offset, write in what the right data would
270 * be, in case the buffer doesn't move and we can short-circuit the
271 * relocation processing in the kernel
273 intel_batchbuffer_emit_dword(intel
, buffer
->offset
+ delta
);
279 intel_batchbuffer_data(struct intel_context
*intel
,
280 const void *data
, GLuint bytes
, bool is_blit
)
282 assert((bytes
& 3) == 0);
283 intel_batchbuffer_require_space(intel
, bytes
, is_blit
);
284 __memcpy(intel
->batch
.map
+ intel
->batch
.used
, data
, bytes
);
285 intel
->batch
.used
+= bytes
>> 2;
289 intel_batchbuffer_cached_advance(struct intel_context
*intel
)
291 struct cached_batch_item
**prev
= &intel
->batch
.cached_items
, *item
;
292 uint32_t sz
= (intel
->batch
.used
- intel
->batch
.emit
) * sizeof(uint32_t);
293 uint32_t *start
= intel
->batch
.map
+ intel
->batch
.emit
;
294 uint16_t op
= *start
>> 16;
300 old
= intel
->batch
.map
+ item
->header
;
301 if (op
== *old
>> 16) {
302 if (item
->size
== sz
&& memcmp(old
, start
, sz
) == 0) {
303 if (prev
!= &intel
->batch
.cached_items
) {
305 item
->next
= intel
->batch
.cached_items
;
306 intel
->batch
.cached_items
= item
;
308 intel
->batch
.used
= intel
->batch
.emit
;
317 item
= malloc(sizeof(struct cached_batch_item
));
321 item
->next
= intel
->batch
.cached_items
;
322 intel
->batch
.cached_items
= item
;
326 item
->header
= intel
->batch
.emit
;
330 * Restriction [DevSNB, DevIVB]:
332 * Prior to changing Depth/Stencil Buffer state (i.e. any combination of
333 * 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS, 3DSTATE_STENCIL_BUFFER,
334 * 3DSTATE_HIER_DEPTH_BUFFER) SW must first issue a pipelined depth stall
335 * (PIPE_CONTROL with Depth Stall bit set), followed by a pipelined depth
336 * cache flush (PIPE_CONTROL with Depth Flush Bit set), followed by
337 * another pipelined depth stall (PIPE_CONTROL with Depth Stall bit set),
338 * unless SW can otherwise guarantee that the pipeline from WM onwards is
339 * already flushed (e.g., via a preceding MI_FLUSH).
342 intel_emit_depth_stall_flushes(struct intel_context
*intel
)
344 assert(intel
->gen
>= 6 && intel
->gen
<= 7);
347 OUT_BATCH(_3DSTATE_PIPE_CONTROL
);
348 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
);
349 OUT_BATCH(0); /* address */
350 OUT_BATCH(0); /* write data */
354 OUT_BATCH(_3DSTATE_PIPE_CONTROL
);
355 OUT_BATCH(PIPE_CONTROL_DEPTH_CACHE_FLUSH
);
356 OUT_BATCH(0); /* address */
357 OUT_BATCH(0); /* write data */
361 OUT_BATCH(_3DSTATE_PIPE_CONTROL
);
362 OUT_BATCH(PIPE_CONTROL_DEPTH_STALL
);
363 OUT_BATCH(0); /* address */
364 OUT_BATCH(0); /* write data */
369 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
370 * implementing two workarounds on gen6. From section 1.4.7.1
371 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
373 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
374 * produced by non-pipelined state commands), software needs to first
375 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
378 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
379 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
381 * And the workaround for these two requires this workaround first:
383 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
384 * BEFORE the pipe-control with a post-sync op and no write-cache
387 * And this last workaround is tricky because of the requirements on
388 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
391 * "1 of the following must also be set:
392 * - Render Target Cache Flush Enable ([12] of DW1)
393 * - Depth Cache Flush Enable ([0] of DW1)
394 * - Stall at Pixel Scoreboard ([1] of DW1)
395 * - Depth Stall ([13] of DW1)
396 * - Post-Sync Operation ([13] of DW1)
397 * - Notify Enable ([8] of DW1)"
399 * The cache flushes require the workaround flush that triggered this
400 * one, so we can't use it. Depth stall would trigger the same.
401 * Post-sync nonzero is what triggered this second workaround, so we
402 * can't use that one either. Notify enable is IRQs, which aren't
403 * really our business. That leaves only stall at scoreboard.
406 intel_emit_post_sync_nonzero_flush(struct intel_context
*intel
)
408 if (!intel
->batch
.need_workaround_flush
)
412 OUT_BATCH(_3DSTATE_PIPE_CONTROL
);
413 OUT_BATCH(PIPE_CONTROL_CS_STALL
|
414 PIPE_CONTROL_STALL_AT_SCOREBOARD
);
415 OUT_BATCH(0); /* address */
416 OUT_BATCH(0); /* write data */
420 OUT_BATCH(_3DSTATE_PIPE_CONTROL
);
421 OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE
);
422 OUT_RELOC(intel
->batch
.workaround_bo
,
423 I915_GEM_DOMAIN_INSTRUCTION
, I915_GEM_DOMAIN_INSTRUCTION
, 0);
424 OUT_BATCH(0); /* write data */
427 intel
->batch
.need_workaround_flush
= false;
430 /* Emit a pipelined flush to either flush render and texture cache for
431 * reading from a FBO-drawn texture, or flush so that frontbuffer
432 * render appears on the screen in DRI1.
434 * This is also used for the always_flush_cache driconf debug option.
437 intel_batchbuffer_emit_mi_flush(struct intel_context
*intel
)
439 if (intel
->gen
>= 6) {
440 if (intel
->batch
.is_blit
) {
442 OUT_BATCH(MI_FLUSH_DW
);
448 if (intel
->gen
== 6) {
449 /* Hardware workaround: SNB B-Spec says:
451 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache
452 * Flush Enable =1, a PIPE_CONTROL with any non-zero
453 * post-sync-op is required.
455 intel_emit_post_sync_nonzero_flush(intel
);
459 OUT_BATCH(_3DSTATE_PIPE_CONTROL
);
460 OUT_BATCH(PIPE_CONTROL_INSTRUCTION_FLUSH
|
461 PIPE_CONTROL_WRITE_FLUSH
|
462 PIPE_CONTROL_DEPTH_CACHE_FLUSH
|
463 PIPE_CONTROL_VF_CACHE_INVALIDATE
|
464 PIPE_CONTROL_TC_FLUSH
|
465 PIPE_CONTROL_NO_WRITE
|
466 PIPE_CONTROL_CS_STALL
);
467 OUT_BATCH(0); /* write address */
468 OUT_BATCH(0); /* write data */
471 } else if (intel
->gen
>= 4) {
473 OUT_BATCH(_3DSTATE_PIPE_CONTROL
|
474 PIPE_CONTROL_WRITE_FLUSH
|
475 PIPE_CONTROL_NO_WRITE
);
476 OUT_BATCH(0); /* write address */
477 OUT_BATCH(0); /* write data */
478 OUT_BATCH(0); /* write data */