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i915: Only flag context changes if the actual state is changed
[mesa.git] / src / mesa / drivers / dri / intel / intel_blit.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include "main/mtypes.h"
30 #include "main/context.h"
31 #include "main/enums.h"
32 #include "main/colormac.h"
33
34 #include "intel_blit.h"
35 #include "intel_buffers.h"
36 #include "intel_context.h"
37 #include "intel_fbo.h"
38 #include "intel_reg.h"
39 #include "intel_regions.h"
40 #include "intel_batchbuffer.h"
41 #include "intel_mipmap_tree.h"
42
43 #define FILE_DEBUG_FLAG DEBUG_BLIT
44
45 static GLuint translate_raster_op(GLenum logicop)
46 {
47 switch(logicop) {
48 case GL_CLEAR: return 0x00;
49 case GL_AND: return 0x88;
50 case GL_AND_REVERSE: return 0x44;
51 case GL_COPY: return 0xCC;
52 case GL_AND_INVERTED: return 0x22;
53 case GL_NOOP: return 0xAA;
54 case GL_XOR: return 0x66;
55 case GL_OR: return 0xEE;
56 case GL_NOR: return 0x11;
57 case GL_EQUIV: return 0x99;
58 case GL_INVERT: return 0x55;
59 case GL_OR_REVERSE: return 0xDD;
60 case GL_COPY_INVERTED: return 0x33;
61 case GL_OR_INVERTED: return 0xBB;
62 case GL_NAND: return 0x77;
63 case GL_SET: return 0xFF;
64 default: return 0;
65 }
66 }
67
68 static uint32_t
69 br13_for_cpp(int cpp)
70 {
71 switch (cpp) {
72 case 4:
73 return BR13_8888;
74 break;
75 case 2:
76 return BR13_565;
77 break;
78 case 1:
79 return BR13_8;
80 break;
81 default:
82 assert(0);
83 return 0;
84 }
85 }
86
87 /* Copy BitBlt
88 */
89 GLboolean
90 intelEmitCopyBlit(struct intel_context *intel,
91 GLuint cpp,
92 GLshort src_pitch,
93 drm_intel_bo *src_buffer,
94 GLuint src_offset,
95 uint32_t src_tiling,
96 GLshort dst_pitch,
97 drm_intel_bo *dst_buffer,
98 GLuint dst_offset,
99 uint32_t dst_tiling,
100 GLshort src_x, GLshort src_y,
101 GLshort dst_x, GLshort dst_y,
102 GLshort w, GLshort h,
103 GLenum logic_op)
104 {
105 GLuint CMD, BR13, pass = 0;
106 int dst_y2 = dst_y + h;
107 int dst_x2 = dst_x + w;
108 drm_intel_bo *aper_array[3];
109 BATCH_LOCALS;
110
111 if (dst_tiling != I915_TILING_NONE) {
112 if (dst_offset & 4095)
113 return GL_FALSE;
114 if (dst_tiling == I915_TILING_Y)
115 return GL_FALSE;
116 }
117 if (src_tiling != I915_TILING_NONE) {
118 if (src_offset & 4095)
119 return GL_FALSE;
120 if (src_tiling == I915_TILING_Y)
121 return GL_FALSE;
122 }
123
124 /* do space check before going any further */
125 do {
126 aper_array[0] = intel->batch.bo;
127 aper_array[1] = dst_buffer;
128 aper_array[2] = src_buffer;
129
130 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
131 intel_batchbuffer_flush(intel);
132 pass++;
133 } else
134 break;
135 } while (pass < 2);
136
137 if (pass >= 2)
138 return GL_FALSE;
139
140 intel_batchbuffer_require_space(intel, 8 * 4, true);
141 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
142 __FUNCTION__,
143 src_buffer, src_pitch, src_offset, src_x, src_y,
144 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
145
146 src_pitch *= cpp;
147 dst_pitch *= cpp;
148
149 BR13 = br13_for_cpp(cpp) | translate_raster_op(logic_op) << 16;
150
151 switch (cpp) {
152 case 1:
153 case 2:
154 CMD = XY_SRC_COPY_BLT_CMD;
155 break;
156 case 4:
157 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
158 break;
159 default:
160 return GL_FALSE;
161 }
162
163 #ifndef I915
164 if (dst_tiling != I915_TILING_NONE) {
165 CMD |= XY_DST_TILED;
166 dst_pitch /= 4;
167 }
168 if (src_tiling != I915_TILING_NONE) {
169 CMD |= XY_SRC_TILED;
170 src_pitch /= 4;
171 }
172 #endif
173
174 if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
175 return GL_TRUE;
176 }
177
178 assert(dst_x < dst_x2);
179 assert(dst_y < dst_y2);
180
181 BEGIN_BATCH_BLT(8);
182 OUT_BATCH(CMD);
183 OUT_BATCH(BR13 | (uint16_t)dst_pitch);
184 OUT_BATCH((dst_y << 16) | dst_x);
185 OUT_BATCH((dst_y2 << 16) | dst_x2);
186 OUT_RELOC_FENCED(dst_buffer,
187 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
188 dst_offset);
189 OUT_BATCH((src_y << 16) | src_x);
190 OUT_BATCH((uint16_t)src_pitch);
191 OUT_RELOC_FENCED(src_buffer,
192 I915_GEM_DOMAIN_RENDER, 0,
193 src_offset);
194 ADVANCE_BATCH();
195
196 intel_batchbuffer_emit_mi_flush(intel);
197
198 return GL_TRUE;
199 }
200
201
202 /**
203 * Use blitting to clear the renderbuffers named by 'flags'.
204 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
205 * since that might include software renderbuffers or renderbuffers
206 * which we're clearing with triangles.
207 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear
208 */
209 GLbitfield
210 intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
211 {
212 struct intel_context *intel = intel_context(ctx);
213 struct gl_framebuffer *fb = ctx->DrawBuffer;
214 GLuint clear_depth;
215 GLboolean all;
216 GLint cx, cy, cw, ch;
217 GLbitfield fail_mask = 0;
218 BATCH_LOCALS;
219
220 /*
221 * Compute values for clearing the buffers.
222 */
223 clear_depth = 0;
224 if (mask & BUFFER_BIT_DEPTH) {
225 clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
226 }
227 if (mask & BUFFER_BIT_STENCIL) {
228 clear_depth |= (ctx->Stencil.Clear & 0xff) << 24;
229 }
230
231 cx = fb->_Xmin;
232 if (fb->Name == 0)
233 cy = ctx->DrawBuffer->Height - fb->_Ymax;
234 else
235 cy = fb->_Ymin;
236 cw = fb->_Xmax - fb->_Xmin;
237 ch = fb->_Ymax - fb->_Ymin;
238
239 if (cw == 0 || ch == 0)
240 return 0;
241
242 GLuint buf;
243 all = (cw == fb->Width && ch == fb->Height);
244
245 /* Loop over all renderbuffers */
246 for (buf = 0; buf < BUFFER_COUNT && mask; buf++) {
247 const GLbitfield bufBit = 1 << buf;
248 struct intel_renderbuffer *irb;
249 drm_intel_bo *write_buffer;
250 int x1, y1, x2, y2;
251 uint32_t clear_val;
252 uint32_t BR13, CMD;
253 int pitch, cpp;
254 drm_intel_bo *aper_array[2];
255
256 if (!(mask & bufBit))
257 continue;
258
259 /* OK, clear this renderbuffer */
260 irb = intel_get_renderbuffer(fb, buf);
261 write_buffer = intel_region_buffer(intel, irb->region,
262 all ? INTEL_WRITE_FULL :
263 INTEL_WRITE_PART);
264 x1 = cx + irb->region->draw_x;
265 y1 = cy + irb->region->draw_y;
266 x2 = cx + cw + irb->region->draw_x;
267 y2 = cy + ch + irb->region->draw_y;
268
269 pitch = irb->region->pitch;
270 cpp = irb->region->cpp;
271
272 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
273 __FUNCTION__,
274 irb->region->buffer, (pitch * cpp),
275 x1, y1, x2 - x1, y2 - y1);
276
277 BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
278 CMD = XY_COLOR_BLT_CMD;
279
280 /* Setup the blit command */
281 if (cpp == 4) {
282 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
283 if (mask & BUFFER_BIT_DEPTH)
284 CMD |= XY_BLT_WRITE_RGB;
285 if (mask & BUFFER_BIT_STENCIL)
286 CMD |= XY_BLT_WRITE_ALPHA;
287 } else {
288 /* clearing RGBA */
289 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
290 }
291 }
292
293 assert(irb->region->tiling != I915_TILING_Y);
294
295 #ifndef I915
296 if (irb->region->tiling != I915_TILING_NONE) {
297 CMD |= XY_DST_TILED;
298 pitch /= 4;
299 }
300 #endif
301 BR13 |= (pitch * cpp);
302
303 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
304 clear_val = clear_depth;
305 } else {
306 uint8_t clear[4];
307 GLclampf *color = ctx->Color.ClearColor;
308
309 CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]);
310 CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]);
311 CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]);
312 CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]);
313
314 switch (irb->Base.Format) {
315 case MESA_FORMAT_ARGB8888:
316 case MESA_FORMAT_XRGB8888:
317 clear_val = PACK_COLOR_8888(clear[3], clear[0],
318 clear[1], clear[2]);
319 break;
320 case MESA_FORMAT_RGB565:
321 clear_val = PACK_COLOR_565(clear[0], clear[1], clear[2]);
322 break;
323 case MESA_FORMAT_ARGB4444:
324 clear_val = PACK_COLOR_4444(clear[3], clear[0],
325 clear[1], clear[2]);
326 break;
327 case MESA_FORMAT_ARGB1555:
328 clear_val = PACK_COLOR_1555(clear[3], clear[0],
329 clear[1], clear[2]);
330 break;
331 case MESA_FORMAT_A8:
332 clear_val = PACK_COLOR_8888(clear[3], clear[3],
333 clear[3], clear[3]);
334 break;
335 default:
336 fail_mask |= bufBit;
337 mask &= ~bufBit;
338 continue;
339 }
340 }
341
342 assert(x1 < x2);
343 assert(y1 < y2);
344
345 /* do space check before going any further */
346 aper_array[0] = intel->batch.bo;
347 aper_array[1] = write_buffer;
348
349 if (drm_intel_bufmgr_check_aperture_space(aper_array,
350 ARRAY_SIZE(aper_array)) != 0) {
351 intel_batchbuffer_flush(intel);
352 }
353
354 BEGIN_BATCH_BLT(6);
355 OUT_BATCH(CMD);
356 OUT_BATCH(BR13);
357 OUT_BATCH((y1 << 16) | x1);
358 OUT_BATCH((y2 << 16) | x2);
359 OUT_RELOC_FENCED(write_buffer,
360 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
361 0);
362 OUT_BATCH(clear_val);
363 ADVANCE_BATCH();
364
365 if (intel->always_flush_cache)
366 intel_batchbuffer_emit_mi_flush(intel);
367
368 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL)
369 mask &= ~(BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL);
370 else
371 mask &= ~bufBit; /* turn off bit, for faster loop exit */
372 }
373
374 return fail_mask;
375 }
376
377 GLboolean
378 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
379 GLuint cpp,
380 GLubyte *src_bits, GLuint src_size,
381 GLuint fg_color,
382 GLshort dst_pitch,
383 drm_intel_bo *dst_buffer,
384 GLuint dst_offset,
385 uint32_t dst_tiling,
386 GLshort x, GLshort y,
387 GLshort w, GLshort h,
388 GLenum logic_op)
389 {
390 int dwords = ALIGN(src_size, 8) / 4;
391 uint32_t opcode, br13, blit_cmd;
392
393 if (dst_tiling != I915_TILING_NONE) {
394 if (dst_offset & 4095)
395 return GL_FALSE;
396 if (dst_tiling == I915_TILING_Y)
397 return GL_FALSE;
398 }
399
400 assert( logic_op - GL_CLEAR >= 0 );
401 assert( logic_op - GL_CLEAR < 0x10 );
402 assert(dst_pitch > 0);
403
404 if (w < 0 || h < 0)
405 return GL_TRUE;
406
407 dst_pitch *= cpp;
408
409 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
410 __FUNCTION__,
411 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
412
413 intel_batchbuffer_require_space(intel,
414 (8 * 4) +
415 (3 * 4) +
416 dwords * 4, true);
417
418 opcode = XY_SETUP_BLT_CMD;
419 if (cpp == 4)
420 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
421 #ifndef I915
422 if (dst_tiling != I915_TILING_NONE) {
423 opcode |= XY_DST_TILED;
424 dst_pitch /= 4;
425 }
426 #endif
427
428 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
429 br13 |= br13_for_cpp(cpp);
430
431 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
432 if (dst_tiling != I915_TILING_NONE)
433 blit_cmd |= XY_DST_TILED;
434
435 BEGIN_BATCH_BLT(8 + 3);
436 OUT_BATCH(opcode);
437 OUT_BATCH(br13);
438 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
439 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
440 OUT_RELOC_FENCED(dst_buffer,
441 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
442 dst_offset);
443 OUT_BATCH(0); /* bg */
444 OUT_BATCH(fg_color); /* fg */
445 OUT_BATCH(0); /* pattern base addr */
446
447 OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
448 OUT_BATCH((y << 16) | x);
449 OUT_BATCH(((y + h) << 16) | (x + w));
450 ADVANCE_BATCH();
451
452 intel_batchbuffer_data(intel, src_bits, dwords * 4, true);
453
454 intel_batchbuffer_emit_mi_flush(intel);
455
456 return GL_TRUE;
457 }
458
459 /* We don't have a memmove-type blit like some other hardware, so we'll do a
460 * rectangular blit covering a large space, then emit 1-scanline blit at the
461 * end to cover the last if we need.
462 */
463 void
464 intel_emit_linear_blit(struct intel_context *intel,
465 drm_intel_bo *dst_bo,
466 unsigned int dst_offset,
467 drm_intel_bo *src_bo,
468 unsigned int src_offset,
469 unsigned int size)
470 {
471 GLuint pitch, height;
472 GLboolean ok;
473
474 /* The pitch given to the GPU must be DWORD aligned, and
475 * we want width to match pitch. Max width is (1 << 15 - 1),
476 * rounding that down to the nearest DWORD is 1 << 15 - 4
477 */
478 pitch = MIN2(size, (1 << 15) - 4);
479 height = size / pitch;
480 ok = intelEmitCopyBlit(intel, 1,
481 pitch, src_bo, src_offset, I915_TILING_NONE,
482 pitch, dst_bo, dst_offset, I915_TILING_NONE,
483 0, 0, /* src x/y */
484 0, 0, /* dst x/y */
485 pitch, height, /* w, h */
486 GL_COPY);
487 assert(ok);
488
489 src_offset += pitch * height;
490 dst_offset += pitch * height;
491 size -= pitch * height;
492 assert (size < (1 << 15));
493 assert ((size & 3) == 0); /* Pitch must be DWORD aligned */
494 if (size != 0) {
495 ok = intelEmitCopyBlit(intel, 1,
496 size, src_bo, src_offset, I915_TILING_NONE,
497 size, dst_bo, dst_offset, I915_TILING_NONE,
498 0, 0, /* src x/y */
499 0, 0, /* dst x/y */
500 size, 1, /* w, h */
501 GL_COPY);
502 assert(ok);
503 }
504 }
505
506 /**
507 * Used to initialize the alpha value of an ARGB8888 teximage after
508 * loading it from an XRGB8888 source.
509 *
510 * This is very common with glCopyTexImage2D().
511 */
512 void
513 intel_set_teximage_alpha_to_one(struct gl_context *ctx,
514 struct intel_texture_image *intel_image)
515 {
516 struct intel_context *intel = intel_context(ctx);
517 unsigned int image_x, image_y;
518 uint32_t x1, y1, x2, y2;
519 uint32_t BR13, CMD;
520 int pitch, cpp;
521 drm_intel_bo *aper_array[2];
522 struct intel_region *region = intel_image->mt->region;
523 BATCH_LOCALS;
524
525 assert(intel_image->base.TexFormat == MESA_FORMAT_ARGB8888);
526
527 /* get dest x/y in destination texture */
528 intel_miptree_get_image_offset(intel_image->mt,
529 intel_image->level,
530 intel_image->face,
531 0,
532 &image_x, &image_y);
533
534 x1 = image_x;
535 y1 = image_y;
536 x2 = image_x + intel_image->base.Width;
537 y2 = image_y + intel_image->base.Height;
538
539 pitch = region->pitch;
540 cpp = region->cpp;
541
542 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
543 __FUNCTION__,
544 intel_image->mt->region->buffer, (pitch * cpp),
545 x1, y1, x2 - x1, y2 - y1);
546
547 BR13 = br13_for_cpp(cpp) | 0xf0 << 16;
548 CMD = XY_COLOR_BLT_CMD;
549 CMD |= XY_BLT_WRITE_ALPHA;
550
551 assert(region->tiling != I915_TILING_Y);
552
553 #ifndef I915
554 if (region->tiling != I915_TILING_NONE) {
555 CMD |= XY_DST_TILED;
556 pitch /= 4;
557 }
558 #endif
559 BR13 |= (pitch * cpp);
560
561 /* do space check before going any further */
562 aper_array[0] = intel->batch.bo;
563 aper_array[1] = region->buffer;
564
565 if (drm_intel_bufmgr_check_aperture_space(aper_array,
566 ARRAY_SIZE(aper_array)) != 0) {
567 intel_batchbuffer_flush(intel);
568 }
569
570 BEGIN_BATCH_BLT(6);
571 OUT_BATCH(CMD);
572 OUT_BATCH(BR13);
573 OUT_BATCH((y1 << 16) | x1);
574 OUT_BATCH((y2 << 16) | x2);
575 OUT_RELOC_FENCED(region->buffer,
576 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
577 0);
578 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
579 ADVANCE_BATCH();
580
581 intel_batchbuffer_emit_mi_flush(intel);
582 }