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Merge branch 'mesa_7_5_branch' into mesa_7_6_branch
[mesa.git] / src / mesa / drivers / dri / intel / intel_blit.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28
29 #include <stdio.h>
30 #include <errno.h>
31
32 #include "main/mtypes.h"
33 #include "main/context.h"
34 #include "main/enums.h"
35 #include "main/texformat.h"
36 #include "main/colormac.h"
37
38 #include "intel_blit.h"
39 #include "intel_buffers.h"
40 #include "intel_context.h"
41 #include "intel_fbo.h"
42 #include "intel_reg.h"
43 #include "intel_regions.h"
44 #include "intel_batchbuffer.h"
45 #include "intel_chipset.h"
46
47 #define FILE_DEBUG_FLAG DEBUG_BLIT
48
49 /**
50 * Copy the back color buffer to the front color buffer.
51 * Used for SwapBuffers().
52 */
53 void
54 intelCopyBuffer(const __DRIdrawablePrivate * dPriv,
55 const drm_clip_rect_t * rect)
56 {
57
58 struct intel_context *intel;
59 const intelScreenPrivate *intelScreen;
60
61 DBG("%s\n", __FUNCTION__);
62
63 assert(dPriv);
64
65 intel = intelScreenContext(dPriv->driScreenPriv->private);
66 if (!intel)
67 return;
68
69 intelScreen = intel->intelScreen;
70
71 /* The LOCK_HARDWARE is required for the cliprects. Buffer offsets
72 * should work regardless.
73 */
74 LOCK_HARDWARE(intel);
75
76 if (dPriv && dPriv->numClipRects) {
77 struct intel_framebuffer *intel_fb = dPriv->driverPrivate;
78 struct intel_region *src, *dst;
79 int nbox = dPriv->numClipRects;
80 drm_clip_rect_t *pbox = dPriv->pClipRects;
81 int cpp;
82 int src_pitch, dst_pitch;
83 unsigned short src_x, src_y;
84 int BR13, CMD;
85 int i;
86 dri_bo *aper_array[3];
87
88 src = intel_get_rb_region(&intel_fb->Base, BUFFER_BACK_LEFT);
89 dst = intel_get_rb_region(&intel_fb->Base, BUFFER_FRONT_LEFT);
90
91 src_pitch = src->pitch * src->cpp;
92 dst_pitch = dst->pitch * dst->cpp;
93
94 cpp = src->cpp;
95
96 ASSERT(intel_fb);
97 ASSERT(intel_fb->Base.Name == 0); /* Not a user-created FBO */
98 ASSERT(src);
99 ASSERT(dst);
100 ASSERT(src->cpp == dst->cpp);
101
102 if (cpp == 2) {
103 BR13 = (0xCC << 16) | BR13_565;
104 CMD = XY_SRC_COPY_BLT_CMD;
105 }
106 else {
107 BR13 = (0xCC << 16) | BR13_8888;
108 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
109 }
110
111 assert(src->tiling != I915_TILING_Y);
112 assert(dst->tiling != I915_TILING_Y);
113 #ifndef I915
114 if (src->tiling != I915_TILING_NONE) {
115 CMD |= XY_SRC_TILED;
116 src_pitch /= 4;
117 }
118 if (dst->tiling != I915_TILING_NONE) {
119 CMD |= XY_DST_TILED;
120 dst_pitch /= 4;
121 }
122 #endif
123 /* do space/cliprects check before going any further */
124 intel_batchbuffer_require_space(intel->batch, 8 * 4,
125 REFERENCES_CLIPRECTS);
126 again:
127 aper_array[0] = intel->batch->buf;
128 aper_array[1] = dst->buffer;
129 aper_array[2] = src->buffer;
130
131 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
132 intel_batchbuffer_flush(intel->batch);
133 goto again;
134 }
135
136 for (i = 0; i < nbox; i++, pbox++) {
137 drm_clip_rect_t box = *pbox;
138
139 if (rect) {
140 if (!intel_intersect_cliprects(&box, &box, rect))
141 continue;
142 }
143
144 if (box.x1 >= box.x2 ||
145 box.y1 >= box.y2)
146 continue;
147
148 assert(box.x1 < box.x2);
149 assert(box.y1 < box.y2);
150 src_x = box.x1 - dPriv->x + dPriv->backX;
151 src_y = box.y1 - dPriv->y + dPriv->backY;
152
153 BEGIN_BATCH(8, REFERENCES_CLIPRECTS);
154 OUT_BATCH(CMD);
155 OUT_BATCH(BR13 | dst_pitch);
156 OUT_BATCH((box.y1 << 16) | box.x1);
157 OUT_BATCH((box.y2 << 16) | box.x2);
158
159 OUT_RELOC(dst->buffer,
160 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
161 0);
162 OUT_BATCH((src_y << 16) | src_x);
163 OUT_BATCH(src_pitch);
164 OUT_RELOC(src->buffer,
165 I915_GEM_DOMAIN_RENDER, 0,
166 0);
167 ADVANCE_BATCH();
168 }
169
170 /* Flush the rendering and the batch so that the results all land on the
171 * screen in a timely fashion.
172 */
173 intel_batchbuffer_emit_mi_flush(intel->batch);
174 intel_batchbuffer_flush(intel->batch);
175 }
176
177 UNLOCK_HARDWARE(intel);
178 }
179
180 static GLuint translate_raster_op(GLenum logicop)
181 {
182 switch(logicop) {
183 case GL_CLEAR: return 0x00;
184 case GL_AND: return 0x88;
185 case GL_AND_REVERSE: return 0x44;
186 case GL_COPY: return 0xCC;
187 case GL_AND_INVERTED: return 0x22;
188 case GL_NOOP: return 0xAA;
189 case GL_XOR: return 0x66;
190 case GL_OR: return 0xEE;
191 case GL_NOR: return 0x11;
192 case GL_EQUIV: return 0x99;
193 case GL_INVERT: return 0x55;
194 case GL_OR_REVERSE: return 0xDD;
195 case GL_COPY_INVERTED: return 0x33;
196 case GL_OR_INVERTED: return 0xBB;
197 case GL_NAND: return 0x77;
198 case GL_SET: return 0xFF;
199 default: return 0;
200 }
201 }
202
203
204 /* Copy BitBlt
205 */
206 GLboolean
207 intelEmitCopyBlit(struct intel_context *intel,
208 GLuint cpp,
209 GLshort src_pitch,
210 dri_bo *src_buffer,
211 GLuint src_offset,
212 uint32_t src_tiling,
213 GLshort dst_pitch,
214 dri_bo *dst_buffer,
215 GLuint dst_offset,
216 uint32_t dst_tiling,
217 GLshort src_x, GLshort src_y,
218 GLshort dst_x, GLshort dst_y,
219 GLshort w, GLshort h,
220 GLenum logic_op)
221 {
222 GLuint CMD, BR13, pass = 0;
223 int dst_y2 = dst_y + h;
224 int dst_x2 = dst_x + w;
225 dri_bo *aper_array[3];
226 BATCH_LOCALS;
227
228 if (dst_tiling != I915_TILING_NONE) {
229 if (dst_offset & 4095)
230 return GL_FALSE;
231 if (dst_tiling == I915_TILING_Y)
232 return GL_FALSE;
233 }
234 if (src_tiling != I915_TILING_NONE) {
235 if (src_offset & 4095)
236 return GL_FALSE;
237 if (src_tiling == I915_TILING_Y)
238 return GL_FALSE;
239 }
240
241 /* do space/cliprects check before going any further */
242 do {
243 aper_array[0] = intel->batch->buf;
244 aper_array[1] = dst_buffer;
245 aper_array[2] = src_buffer;
246
247 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) {
248 intel_batchbuffer_flush(intel->batch);
249 pass++;
250 } else
251 break;
252 } while (pass < 2);
253
254 if (pass >= 2) {
255 LOCK_HARDWARE(intel);
256 dri_bo_map(dst_buffer, GL_TRUE);
257 dri_bo_map(src_buffer, GL_FALSE);
258 _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset,
259 cpp,
260 dst_pitch,
261 dst_x, dst_y,
262 w, h,
263 (GLubyte *)src_buffer->virtual + src_offset,
264 src_pitch,
265 src_x, src_y);
266
267 dri_bo_unmap(src_buffer);
268 dri_bo_unmap(dst_buffer);
269 UNLOCK_HARDWARE(intel);
270
271 return GL_TRUE;
272 }
273
274 intel_batchbuffer_require_space(intel->batch, 8 * 4, NO_LOOP_CLIPRECTS);
275 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
276 __FUNCTION__,
277 src_buffer, src_pitch, src_offset, src_x, src_y,
278 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h);
279
280 src_pitch *= cpp;
281 dst_pitch *= cpp;
282
283 BR13 = translate_raster_op(logic_op) << 16;
284
285 switch (cpp) {
286 case 1:
287 CMD = XY_SRC_COPY_BLT_CMD;
288 break;
289 case 2:
290 BR13 |= BR13_565;
291 CMD = XY_SRC_COPY_BLT_CMD;
292 break;
293 case 4:
294 BR13 |= BR13_8888;
295 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
296 break;
297 default:
298 return GL_FALSE;
299 }
300
301 #ifndef I915
302 if (dst_tiling != I915_TILING_NONE) {
303 CMD |= XY_DST_TILED;
304 dst_pitch /= 4;
305 }
306 if (src_tiling != I915_TILING_NONE) {
307 CMD |= XY_SRC_TILED;
308 src_pitch /= 4;
309 }
310 #endif
311
312 if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
313 return GL_TRUE;
314 }
315
316 assert(dst_x < dst_x2);
317 assert(dst_y < dst_y2);
318
319 BEGIN_BATCH(8, NO_LOOP_CLIPRECTS);
320 OUT_BATCH(CMD);
321 OUT_BATCH(BR13 | (uint16_t)dst_pitch);
322 OUT_BATCH((dst_y << 16) | dst_x);
323 OUT_BATCH((dst_y2 << 16) | dst_x2);
324 OUT_RELOC(dst_buffer,
325 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
326 dst_offset);
327 OUT_BATCH((src_y << 16) | src_x);
328 OUT_BATCH((uint16_t)src_pitch);
329 OUT_RELOC(src_buffer,
330 I915_GEM_DOMAIN_RENDER, 0,
331 src_offset);
332 ADVANCE_BATCH();
333
334 intel_batchbuffer_emit_mi_flush(intel->batch);
335
336 return GL_TRUE;
337 }
338
339
340 /**
341 * Use blitting to clear the renderbuffers named by 'flags'.
342 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
343 * since that might include software renderbuffers or renderbuffers
344 * which we're clearing with triangles.
345 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear
346 */
347 void
348 intelClearWithBlit(GLcontext *ctx, GLbitfield mask)
349 {
350 struct intel_context *intel = intel_context(ctx);
351 struct gl_framebuffer *fb = ctx->DrawBuffer;
352 GLuint clear_depth;
353 GLbitfield skipBuffers = 0;
354 unsigned int num_cliprects;
355 struct drm_clip_rect *cliprects;
356 int x_off, y_off;
357 BATCH_LOCALS;
358
359 /*
360 * Compute values for clearing the buffers.
361 */
362 clear_depth = 0;
363 if (mask & BUFFER_BIT_DEPTH) {
364 clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear);
365 }
366 if (mask & BUFFER_BIT_STENCIL) {
367 clear_depth |= (ctx->Stencil.Clear & 0xff) << 24;
368 }
369
370 /* If clearing both depth and stencil, skip BUFFER_BIT_STENCIL in
371 * the loop below.
372 */
373 if ((mask & BUFFER_BIT_DEPTH) && (mask & BUFFER_BIT_STENCIL)) {
374 skipBuffers = BUFFER_BIT_STENCIL;
375 }
376
377 /* XXX Move this flush/lock into the following conditional? */
378 intelFlush(&intel->ctx);
379 LOCK_HARDWARE(intel);
380
381 intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
382 if (num_cliprects) {
383 GLint cx, cy, cw, ch;
384 drm_clip_rect_t clear;
385 int i;
386
387 /* Get clear bounds after locking */
388 cx = fb->_Xmin;
389 cy = fb->_Ymin;
390 cw = fb->_Xmax - cx;
391 ch = fb->_Ymax - cy;
392
393 if (fb->Name == 0) {
394 /* clearing a window */
395
396 /* flip top to bottom */
397 clear.x1 = cx + x_off;
398 clear.y1 = intel->driDrawable->y + intel->driDrawable->h - cy - ch;
399 clear.x2 = clear.x1 + cw;
400 clear.y2 = clear.y1 + ch;
401 }
402 else {
403 /* clearing FBO */
404 assert(num_cliprects == 1);
405 assert(cliprects == &intel->fboRect);
406 clear.x1 = cx;
407 clear.y1 = cy;
408 clear.x2 = clear.x1 + cw;
409 clear.y2 = clear.y1 + ch;
410 /* no change to mask */
411 }
412
413 for (i = 0; i < num_cliprects; i++) {
414 const drm_clip_rect_t *box = &cliprects[i];
415 drm_clip_rect_t b;
416 GLuint buf;
417 GLuint clearMask = mask; /* use copy, since we modify it below */
418 GLboolean all = (cw == fb->Width && ch == fb->Height);
419
420 if (!all) {
421 intel_intersect_cliprects(&b, &clear, box);
422 }
423 else {
424 b = *box;
425 }
426
427 if (b.x1 >= b.x2 || b.y1 >= b.y2)
428 continue;
429
430 if (0)
431 _mesa_printf("clear %d,%d..%d,%d, mask %x\n",
432 b.x1, b.y1, b.x2, b.y2, mask);
433
434 /* Loop over all renderbuffers */
435 for (buf = 0; buf < BUFFER_COUNT && clearMask; buf++) {
436 const GLbitfield bufBit = 1 << buf;
437 if ((clearMask & bufBit) && !(bufBit & skipBuffers)) {
438 /* OK, clear this renderbuffer */
439 struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, buf);
440 dri_bo *write_buffer =
441 intel_region_buffer(intel, irb->region,
442 all ? INTEL_WRITE_FULL :
443 INTEL_WRITE_PART);
444
445 GLuint clearVal;
446 GLint pitch, cpp;
447 GLuint BR13, CMD;
448
449 pitch = irb->region->pitch;
450 cpp = irb->region->cpp;
451
452 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
453 __FUNCTION__,
454 irb->region->buffer, (pitch * cpp),
455 irb->region->draw_offset,
456 b.x1, b.y1, b.x2 - b.x1, b.y2 - b.y1);
457
458 BR13 = 0xf0 << 16;
459 CMD = XY_COLOR_BLT_CMD;
460
461 /* Setup the blit command */
462 if (cpp == 4) {
463 BR13 |= BR13_8888;
464 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
465 if (clearMask & BUFFER_BIT_DEPTH)
466 CMD |= XY_BLT_WRITE_RGB;
467 if (clearMask & BUFFER_BIT_STENCIL)
468 CMD |= XY_BLT_WRITE_ALPHA;
469 }
470 else {
471 /* clearing RGBA */
472 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
473 }
474 }
475 else {
476 ASSERT(cpp == 2);
477 BR13 |= BR13_565;
478 }
479
480 assert(irb->region->tiling != I915_TILING_Y);
481
482 #ifndef I915
483 if (irb->region->tiling != I915_TILING_NONE) {
484 CMD |= XY_DST_TILED;
485 pitch /= 4;
486 }
487 #endif
488 BR13 |= (pitch * cpp);
489
490 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) {
491 clearVal = clear_depth;
492 }
493 else {
494 uint8_t clear[4];
495 GLclampf *color = ctx->Color.ClearColor;
496
497 CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]);
498 CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]);
499 CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]);
500 CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]);
501
502 switch (irb->texformat->MesaFormat) {
503 case MESA_FORMAT_ARGB8888:
504 clearVal = intel->ClearColor8888;
505 break;
506 case MESA_FORMAT_RGB565:
507 clearVal = intel->ClearColor565;
508 break;
509 case MESA_FORMAT_ARGB4444:
510 clearVal = PACK_COLOR_4444(clear[3], clear[0],
511 clear[1], clear[2]);
512 break;
513 case MESA_FORMAT_ARGB1555:
514 clearVal = PACK_COLOR_1555(clear[3], clear[0],
515 clear[1], clear[2]);
516 break;
517 default:
518 _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n",
519 irb->texformat->MesaFormat);
520 clearVal = 0;
521 }
522 }
523
524 /*
525 _mesa_debug(ctx, "hardware blit clear buf %d rb id %d\n",
526 buf, irb->Base.Name);
527 */
528
529 assert(b.x1 < b.x2);
530 assert(b.y1 < b.y2);
531
532 BEGIN_BATCH(6, REFERENCES_CLIPRECTS);
533 OUT_BATCH(CMD);
534 OUT_BATCH(BR13);
535 OUT_BATCH((b.y1 << 16) | b.x1);
536 OUT_BATCH((b.y2 << 16) | b.x2);
537 OUT_RELOC(write_buffer,
538 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
539 irb->region->draw_offset);
540 OUT_BATCH(clearVal);
541 ADVANCE_BATCH();
542 clearMask &= ~bufBit; /* turn off bit, for faster loop exit */
543 }
544 }
545 }
546 }
547
548 UNLOCK_HARDWARE(intel);
549 }
550
551 GLboolean
552 intelEmitImmediateColorExpandBlit(struct intel_context *intel,
553 GLuint cpp,
554 GLubyte *src_bits, GLuint src_size,
555 GLuint fg_color,
556 GLshort dst_pitch,
557 dri_bo *dst_buffer,
558 GLuint dst_offset,
559 uint32_t dst_tiling,
560 GLshort x, GLshort y,
561 GLshort w, GLshort h,
562 GLenum logic_op)
563 {
564 int dwords = ALIGN(src_size, 8) / 4;
565 uint32_t opcode, br13, blit_cmd;
566
567 if (dst_tiling != I915_TILING_NONE) {
568 if (dst_offset & 4095)
569 return GL_FALSE;
570 if (dst_tiling == I915_TILING_Y)
571 return GL_FALSE;
572 }
573
574 assert( logic_op - GL_CLEAR >= 0 );
575 assert( logic_op - GL_CLEAR < 0x10 );
576 assert(dst_pitch > 0);
577
578 if (w < 0 || h < 0)
579 return GL_TRUE;
580
581 dst_pitch *= cpp;
582
583 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
584 __FUNCTION__,
585 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords);
586
587 intel_batchbuffer_require_space( intel->batch,
588 (8 * 4) +
589 (3 * 4) +
590 dwords * 4,
591 REFERENCES_CLIPRECTS );
592
593 opcode = XY_SETUP_BLT_CMD;
594 if (cpp == 4)
595 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
596 #ifndef I915
597 if (dst_tiling != I915_TILING_NONE) {
598 opcode |= XY_DST_TILED;
599 dst_pitch /= 4;
600 }
601 #endif
602
603 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
604 if (cpp == 2)
605 br13 |= BR13_565;
606 else
607 br13 |= BR13_8888;
608
609 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */
610 if (dst_tiling != I915_TILING_NONE)
611 blit_cmd |= XY_DST_TILED;
612
613 BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS);
614 OUT_BATCH(opcode);
615 OUT_BATCH(br13);
616 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
617 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
618 OUT_RELOC(dst_buffer,
619 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
620 dst_offset);
621 OUT_BATCH(0); /* bg */
622 OUT_BATCH(fg_color); /* fg */
623 OUT_BATCH(0); /* pattern base addr */
624
625 OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
626 OUT_BATCH((y << 16) | x);
627 OUT_BATCH(((y + h) << 16) | (x + w));
628 ADVANCE_BATCH();
629
630 intel_batchbuffer_data( intel->batch,
631 src_bits,
632 dwords * 4,
633 REFERENCES_CLIPRECTS );
634
635 intel_batchbuffer_emit_mi_flush(intel->batch);
636
637 return GL_TRUE;
638 }
639
640 /* We don't have a memmove-type blit like some other hardware, so we'll do a
641 * rectangular blit covering a large space, then emit 1-scanline blit at the
642 * end to cover the last if we need.
643 */
644 void
645 intel_emit_linear_blit(struct intel_context *intel,
646 drm_intel_bo *dst_bo,
647 unsigned int dst_offset,
648 drm_intel_bo *src_bo,
649 unsigned int src_offset,
650 unsigned int size)
651 {
652 GLuint pitch, height;
653
654 /* The pitch is a signed value. */
655 pitch = MIN2(size, (1 << 15) - 1);
656 height = size / pitch;
657 intelEmitCopyBlit(intel, 1,
658 pitch, src_bo, src_offset, I915_TILING_NONE,
659 pitch, dst_bo, dst_offset, I915_TILING_NONE,
660 0, 0, /* src x/y */
661 0, 0, /* dst x/y */
662 pitch, height, /* w, h */
663 GL_COPY);
664
665 src_offset += pitch * height;
666 dst_offset += pitch * height;
667 size -= pitch * height;
668 assert (size < (1 << 15));
669 if (size != 0) {
670 intelEmitCopyBlit(intel, 1,
671 size, src_bo, src_offset, I915_TILING_NONE,
672 size, dst_bo, dst_offset, I915_TILING_NONE,
673 0, 0, /* src x/y */
674 0, 0, /* dst x/y */
675 size, 1, /* w, h */
676 GL_COPY);
677 }
678 }