1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 #include "main/mtypes.h"
30 #include "main/context.h"
31 #include "main/enums.h"
32 #include "main/colormac.h"
34 #include "intel_blit.h"
35 #include "intel_buffers.h"
36 #include "intel_context.h"
37 #include "intel_fbo.h"
38 #include "intel_reg.h"
39 #include "intel_regions.h"
40 #include "intel_batchbuffer.h"
41 #include "intel_mipmap_tree.h"
43 #define FILE_DEBUG_FLAG DEBUG_BLIT
45 static GLuint
translate_raster_op(GLenum logicop
)
48 case GL_CLEAR
: return 0x00;
49 case GL_AND
: return 0x88;
50 case GL_AND_REVERSE
: return 0x44;
51 case GL_COPY
: return 0xCC;
52 case GL_AND_INVERTED
: return 0x22;
53 case GL_NOOP
: return 0xAA;
54 case GL_XOR
: return 0x66;
55 case GL_OR
: return 0xEE;
56 case GL_NOR
: return 0x11;
57 case GL_EQUIV
: return 0x99;
58 case GL_INVERT
: return 0x55;
59 case GL_OR_REVERSE
: return 0xDD;
60 case GL_COPY_INVERTED
: return 0x33;
61 case GL_OR_INVERTED
: return 0xBB;
62 case GL_NAND
: return 0x77;
63 case GL_SET
: return 0xFF;
90 intelEmitCopyBlit(struct intel_context
*intel
,
93 drm_intel_bo
*src_buffer
,
97 drm_intel_bo
*dst_buffer
,
100 GLshort src_x
, GLshort src_y
,
101 GLshort dst_x
, GLshort dst_y
,
102 GLshort w
, GLshort h
,
105 GLuint CMD
, BR13
, pass
= 0;
106 int dst_y2
= dst_y
+ h
;
107 int dst_x2
= dst_x
+ w
;
108 drm_intel_bo
*aper_array
[3];
111 if (dst_tiling
!= I915_TILING_NONE
) {
112 if (dst_offset
& 4095)
114 if (dst_tiling
== I915_TILING_Y
)
117 if (src_tiling
!= I915_TILING_NONE
) {
118 if (src_offset
& 4095)
120 if (src_tiling
== I915_TILING_Y
)
124 /* do space check before going any further */
126 aper_array
[0] = intel
->batch
.bo
;
127 aper_array
[1] = dst_buffer
;
128 aper_array
[2] = src_buffer
;
130 if (dri_bufmgr_check_aperture_space(aper_array
, 3) != 0) {
131 intel_batchbuffer_flush(intel
);
140 intel_batchbuffer_require_space(intel
, 8 * 4, true);
141 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n",
143 src_buffer
, src_pitch
, src_offset
, src_x
, src_y
,
144 dst_buffer
, dst_pitch
, dst_offset
, dst_x
, dst_y
, w
, h
);
149 /* For big formats (such as floating point), do the copy using 32bpp and
150 * multiply the coordinates.
153 assert(cpp
% 4 == 0);
160 BR13
= br13_for_cpp(cpp
) | translate_raster_op(logic_op
) << 16;
165 CMD
= XY_SRC_COPY_BLT_CMD
;
168 CMD
= XY_SRC_COPY_BLT_CMD
| XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
175 if (dst_tiling
!= I915_TILING_NONE
) {
179 if (src_tiling
!= I915_TILING_NONE
) {
185 if (dst_y2
<= dst_y
|| dst_x2
<= dst_x
) {
189 assert(dst_x
< dst_x2
);
190 assert(dst_y
< dst_y2
);
194 OUT_BATCH(BR13
| (uint16_t)dst_pitch
);
195 OUT_BATCH((dst_y
<< 16) | dst_x
);
196 OUT_BATCH((dst_y2
<< 16) | dst_x2
);
197 OUT_RELOC_FENCED(dst_buffer
,
198 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
200 OUT_BATCH((src_y
<< 16) | src_x
);
201 OUT_BATCH((uint16_t)src_pitch
);
202 OUT_RELOC_FENCED(src_buffer
,
203 I915_GEM_DOMAIN_RENDER
, 0,
207 intel_batchbuffer_emit_mi_flush(intel
);
214 * Use blitting to clear the renderbuffers named by 'flags'.
215 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field
216 * since that might include software renderbuffers or renderbuffers
217 * which we're clearing with triangles.
218 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear
221 intelClearWithBlit(struct gl_context
*ctx
, GLbitfield mask
)
223 struct intel_context
*intel
= intel_context(ctx
);
224 struct gl_framebuffer
*fb
= ctx
->DrawBuffer
;
225 GLuint clear_depth_value
, clear_depth_mask
;
226 GLint cx
, cy
, cw
, ch
;
227 GLbitfield fail_mask
= 0;
231 * Compute values for clearing the buffers.
233 clear_depth_value
= 0;
234 clear_depth_mask
= 0;
235 if (mask
& BUFFER_BIT_DEPTH
) {
236 clear_depth_value
= (GLuint
) (fb
->_DepthMax
* ctx
->Depth
.Clear
);
237 clear_depth_mask
= XY_BLT_WRITE_RGB
;
239 if (mask
& BUFFER_BIT_STENCIL
) {
240 clear_depth_value
|= (ctx
->Stencil
.Clear
& 0xff) << 24;
241 clear_depth_mask
|= XY_BLT_WRITE_ALPHA
;
246 cy
= ctx
->DrawBuffer
->Height
- fb
->_Ymax
;
249 cw
= fb
->_Xmax
- fb
->_Xmin
;
250 ch
= fb
->_Ymax
- fb
->_Ymin
;
252 if (cw
== 0 || ch
== 0)
255 /* Loop over all renderbuffers */
256 mask
&= (1 << BUFFER_COUNT
) - 1;
258 GLuint buf
= _mesa_ffs(mask
) - 1;
259 bool is_depth_stencil
= buf
== BUFFER_DEPTH
|| buf
== BUFFER_STENCIL
;
260 struct intel_renderbuffer
*irb
;
265 drm_intel_bo
*aper_array
[2];
269 irb
= intel_get_renderbuffer(fb
, buf
);
270 if (irb
== NULL
|| irb
->region
== NULL
|| irb
->region
->bo
== NULL
) {
271 fail_mask
|= 1 << buf
;
275 /* OK, clear this renderbuffer */
276 x1
= cx
+ irb
->draw_x
;
277 y1
= cy
+ irb
->draw_y
;
278 x2
= cx
+ cw
+ irb
->draw_x
;
279 y2
= cy
+ ch
+ irb
->draw_y
;
281 pitch
= irb
->region
->pitch
;
282 cpp
= irb
->region
->cpp
;
284 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
286 irb
->region
->bo
, (pitch
* cpp
),
287 x1
, y1
, x2
- x1
, y2
- y1
);
290 CMD
= XY_COLOR_BLT_CMD
;
292 /* Setup the blit command */
294 if (is_depth_stencil
) {
295 CMD
|= clear_depth_mask
;
298 CMD
|= XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
302 assert(irb
->region
->tiling
!= I915_TILING_Y
);
305 if (irb
->region
->tiling
!= I915_TILING_NONE
) {
310 BR13
|= (pitch
* cpp
);
312 if (is_depth_stencil
) {
313 clear_val
= clear_depth_value
;
316 GLfloat
*color
= ctx
->Color
.ClearColor
.f
;
318 _mesa_unclamped_float_rgba_to_ubyte(clear
, color
);
320 switch (irb
->Base
.Format
) {
321 case MESA_FORMAT_ARGB8888
:
322 case MESA_FORMAT_XRGB8888
:
323 clear_val
= PACK_COLOR_8888(clear
[3], clear
[0],
326 case MESA_FORMAT_RGB565
:
327 clear_val
= PACK_COLOR_565(clear
[0], clear
[1], clear
[2]);
329 case MESA_FORMAT_ARGB4444
:
330 clear_val
= PACK_COLOR_4444(clear
[3], clear
[0],
333 case MESA_FORMAT_ARGB1555
:
334 clear_val
= PACK_COLOR_1555(clear
[3], clear
[0],
338 clear_val
= PACK_COLOR_8888(clear
[3], clear
[3],
342 fail_mask
|= 1 << buf
;
347 BR13
|= br13_for_cpp(cpp
);
352 /* do space check before going any further */
353 aper_array
[0] = intel
->batch
.bo
;
354 aper_array
[1] = irb
->region
->bo
;
356 if (drm_intel_bufmgr_check_aperture_space(aper_array
,
357 ARRAY_SIZE(aper_array
)) != 0) {
358 intel_batchbuffer_flush(intel
);
364 OUT_BATCH((y1
<< 16) | x1
);
365 OUT_BATCH((y2
<< 16) | x2
);
366 OUT_RELOC_FENCED(irb
->region
->bo
,
367 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
369 OUT_BATCH(clear_val
);
372 if (intel
->always_flush_cache
)
373 intel_batchbuffer_emit_mi_flush(intel
);
375 if (buf
== BUFFER_DEPTH
|| buf
== BUFFER_STENCIL
)
376 mask
&= ~(BUFFER_BIT_DEPTH
| BUFFER_BIT_STENCIL
);
383 intelEmitImmediateColorExpandBlit(struct intel_context
*intel
,
385 GLubyte
*src_bits
, GLuint src_size
,
388 drm_intel_bo
*dst_buffer
,
391 GLshort x
, GLshort y
,
392 GLshort w
, GLshort h
,
395 int dwords
= ALIGN(src_size
, 8) / 4;
396 uint32_t opcode
, br13
, blit_cmd
;
398 if (dst_tiling
!= I915_TILING_NONE
) {
399 if (dst_offset
& 4095)
401 if (dst_tiling
== I915_TILING_Y
)
405 assert( logic_op
- GL_CLEAR
>= 0 );
406 assert( logic_op
- GL_CLEAR
< 0x10 );
407 assert(dst_pitch
> 0);
414 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n",
416 dst_buffer
, dst_pitch
, dst_offset
, x
, y
, w
, h
, src_size
, dwords
);
418 intel_batchbuffer_require_space(intel
,
423 opcode
= XY_SETUP_BLT_CMD
;
425 opcode
|= XY_BLT_WRITE_ALPHA
| XY_BLT_WRITE_RGB
;
427 if (dst_tiling
!= I915_TILING_NONE
) {
428 opcode
|= XY_DST_TILED
;
433 br13
= dst_pitch
| (translate_raster_op(logic_op
) << 16) | (1 << 29);
434 br13
|= br13_for_cpp(cpp
);
436 blit_cmd
= XY_TEXT_IMMEDIATE_BLIT_CMD
| XY_TEXT_BYTE_PACKED
; /* packing? */
437 if (dst_tiling
!= I915_TILING_NONE
)
438 blit_cmd
|= XY_DST_TILED
;
440 BEGIN_BATCH_BLT(8 + 3);
443 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */
444 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */
445 OUT_RELOC_FENCED(dst_buffer
,
446 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
448 OUT_BATCH(0); /* bg */
449 OUT_BATCH(fg_color
); /* fg */
450 OUT_BATCH(0); /* pattern base addr */
452 OUT_BATCH(blit_cmd
| ((3 - 2) + dwords
));
453 OUT_BATCH((y
<< 16) | x
);
454 OUT_BATCH(((y
+ h
) << 16) | (x
+ w
));
457 intel_batchbuffer_data(intel
, src_bits
, dwords
* 4, true);
459 intel_batchbuffer_emit_mi_flush(intel
);
464 /* We don't have a memmove-type blit like some other hardware, so we'll do a
465 * rectangular blit covering a large space, then emit 1-scanline blit at the
466 * end to cover the last if we need.
469 intel_emit_linear_blit(struct intel_context
*intel
,
470 drm_intel_bo
*dst_bo
,
471 unsigned int dst_offset
,
472 drm_intel_bo
*src_bo
,
473 unsigned int src_offset
,
476 GLuint pitch
, height
;
479 /* The pitch given to the GPU must be DWORD aligned, and
480 * we want width to match pitch. Max width is (1 << 15 - 1),
481 * rounding that down to the nearest DWORD is 1 << 15 - 4
483 pitch
= MIN2(size
, (1 << 15) - 4);
484 height
= size
/ pitch
;
485 ok
= intelEmitCopyBlit(intel
, 1,
486 pitch
, src_bo
, src_offset
, I915_TILING_NONE
,
487 pitch
, dst_bo
, dst_offset
, I915_TILING_NONE
,
490 pitch
, height
, /* w, h */
494 src_offset
+= pitch
* height
;
495 dst_offset
+= pitch
* height
;
496 size
-= pitch
* height
;
497 assert (size
< (1 << 15));
498 assert ((size
& 3) == 0); /* Pitch must be DWORD aligned */
500 ok
= intelEmitCopyBlit(intel
, 1,
501 size
, src_bo
, src_offset
, I915_TILING_NONE
,
502 size
, dst_bo
, dst_offset
, I915_TILING_NONE
,
512 * Used to initialize the alpha value of an ARGB8888 teximage after
513 * loading it from an XRGB8888 source.
515 * This is very common with glCopyTexImage2D().
518 intel_set_teximage_alpha_to_one(struct gl_context
*ctx
,
519 struct intel_texture_image
*intel_image
)
521 struct intel_context
*intel
= intel_context(ctx
);
522 unsigned int image_x
, image_y
;
523 uint32_t x1
, y1
, x2
, y2
;
526 drm_intel_bo
*aper_array
[2];
527 struct intel_region
*region
= intel_image
->mt
->region
;
528 int width
, height
, depth
;
531 intel_miptree_get_dimensions_for_image(&intel_image
->base
.Base
,
532 &width
, &height
, &depth
);
535 assert(intel_image
->base
.Base
.TexFormat
== MESA_FORMAT_ARGB8888
);
537 /* get dest x/y in destination texture */
538 intel_miptree_get_image_offset(intel_image
->mt
,
539 intel_image
->base
.Base
.Level
,
540 intel_image
->base
.Base
.Face
,
546 x2
= image_x
+ width
;
547 y2
= image_y
+ height
;
549 pitch
= region
->pitch
;
552 DBG("%s dst:buf(%p)/%d %d,%d sz:%dx%d\n",
554 intel_image
->mt
->region
->bo
, (pitch
* cpp
),
555 x1
, y1
, x2
- x1
, y2
- y1
);
557 BR13
= br13_for_cpp(cpp
) | 0xf0 << 16;
558 CMD
= XY_COLOR_BLT_CMD
;
559 CMD
|= XY_BLT_WRITE_ALPHA
;
561 assert(region
->tiling
!= I915_TILING_Y
);
564 if (region
->tiling
!= I915_TILING_NONE
) {
569 BR13
|= (pitch
* cpp
);
571 /* do space check before going any further */
572 aper_array
[0] = intel
->batch
.bo
;
573 aper_array
[1] = region
->bo
;
575 if (drm_intel_bufmgr_check_aperture_space(aper_array
,
576 ARRAY_SIZE(aper_array
)) != 0) {
577 intel_batchbuffer_flush(intel
);
583 OUT_BATCH((y1
<< 16) | x1
);
584 OUT_BATCH((y2
<< 16) | x2
);
585 OUT_RELOC_FENCED(region
->bo
,
586 I915_GEM_DOMAIN_RENDER
, I915_GEM_DOMAIN_RENDER
,
588 OUT_BATCH(0xffffffff); /* white, but only alpha gets written */
591 intel_batchbuffer_emit_mi_flush(intel
);