Merge branch 'master' into asm-shader-rework-2
[mesa.git] / src / mesa / drivers / dri / intel / intel_clear.c
1 /**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * Copyright 2009 Intel Corporation.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 **************************************************************************/
28
29 #include "main/glheader.h"
30 #include "main/mtypes.h"
31 #include "swrast/swrast.h"
32 #include "drivers/common/meta.h"
33
34 #include "intel_context.h"
35 #include "intel_blit.h"
36 #include "intel_chipset.h"
37 #include "intel_clear.h"
38 #include "intel_fbo.h"
39 #include "intel_pixel.h"
40 #include "intel_regions.h"
41
42 #define FILE_DEBUG_FLAG DEBUG_BLIT
43
44 static const char *buffer_names[] = {
45 [BUFFER_FRONT_LEFT] = "front",
46 [BUFFER_BACK_LEFT] = "back",
47 [BUFFER_FRONT_RIGHT] = "front right",
48 [BUFFER_BACK_RIGHT] = "back right",
49 [BUFFER_DEPTH] = "depth",
50 [BUFFER_STENCIL] = "stencil",
51 [BUFFER_ACCUM] = "accum",
52 [BUFFER_AUX0] = "aux0",
53 [BUFFER_COLOR0] = "color0",
54 [BUFFER_COLOR1] = "color1",
55 [BUFFER_COLOR2] = "color2",
56 [BUFFER_COLOR3] = "color3",
57 [BUFFER_COLOR4] = "color4",
58 [BUFFER_COLOR5] = "color5",
59 [BUFFER_COLOR6] = "color6",
60 [BUFFER_COLOR7] = "color7",
61 };
62
63 /**
64 * Called by ctx->Driver.Clear.
65 */
66 static void
67 intelClear(GLcontext *ctx, GLbitfield mask)
68 {
69 struct intel_context *intel = intel_context(ctx);
70 const GLuint colorMask = *((GLuint *) & ctx->Color.ColorMask);
71 GLbitfield tri_mask = 0;
72 GLbitfield blit_mask = 0;
73 GLbitfield swrast_mask = 0;
74 struct gl_framebuffer *fb = ctx->DrawBuffer;
75 GLuint i;
76
77 if (0)
78 fprintf(stderr, "%s\n", __FUNCTION__);
79
80 /* HW color buffers (front, back, aux, generic FBO, etc) */
81 if (colorMask == ~0) {
82 /* clear all R,G,B,A */
83 /* XXX FBO: need to check if colorbuffers are software RBOs! */
84 blit_mask |= (mask & BUFFER_BITS_COLOR);
85 }
86 else {
87 /* glColorMask in effect */
88 tri_mask |= (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_BACK_LEFT));
89 }
90
91 /* HW stencil */
92 if (mask & BUFFER_BIT_STENCIL) {
93 const struct intel_region *stencilRegion
94 = intel_get_rb_region(fb, BUFFER_STENCIL);
95 if (stencilRegion) {
96 /* have hw stencil */
97 if (stencilRegion->tiling == I915_TILING_Y ||
98 (ctx->Stencil.WriteMask[0] & 0xff) != 0xff) {
99 /* We have to use the 3D engine if we're clearing a partial mask
100 * of the stencil buffer, or if we're on a 965 which has a tiled
101 * depth/stencil buffer in a layout we can't blit to.
102 */
103 tri_mask |= BUFFER_BIT_STENCIL;
104 }
105 else {
106 /* clearing all stencil bits, use blitting */
107 blit_mask |= BUFFER_BIT_STENCIL;
108 }
109 }
110 }
111
112 /* HW depth */
113 if (mask & BUFFER_BIT_DEPTH) {
114 const struct intel_region *irb = intel_get_rb_region(fb, BUFFER_DEPTH);
115
116 /* clear depth with whatever method is used for stencil (see above) */
117 if (irb->tiling == I915_TILING_Y || tri_mask & BUFFER_BIT_STENCIL)
118 tri_mask |= BUFFER_BIT_DEPTH;
119 else
120 blit_mask |= BUFFER_BIT_DEPTH;
121 }
122
123 /* If we're doing a tri pass for depth/stencil, include a likely color
124 * buffer with it.
125 */
126 if (mask & (BUFFER_BIT_DEPTH | BUFFER_BIT_STENCIL)) {
127 int color_bit = _mesa_ffs(mask & BUFFER_BITS_COLOR);
128 if (color_bit != 0) {
129 tri_mask |= blit_mask & (1 << (color_bit - 1));
130 blit_mask &= ~(1 << (color_bit - 1));
131 }
132 }
133
134 /* SW fallback clearing */
135 swrast_mask = mask & ~tri_mask & ~blit_mask;
136
137 {
138 /* look for non-Intel renderbuffers (clear them with swrast) */
139 GLbitfield blit_or_tri = blit_mask | tri_mask;
140 while (blit_or_tri) {
141 GLuint i = _mesa_ffs(blit_or_tri) - 1;
142 GLbitfield bufBit = 1 << i;
143 if (!fb->Attachment[i].Renderbuffer->ClassID) {
144 blit_mask &= ~bufBit;
145 tri_mask &= ~bufBit;
146 swrast_mask |= bufBit;
147 }
148 blit_or_tri ^= bufBit;
149 }
150 }
151
152 if (blit_mask) {
153 if (INTEL_DEBUG & DEBUG_BLIT) {
154 DBG("blit clear:");
155 for (i = 0; i < BUFFER_COUNT; i++) {
156 if (blit_mask & (1 << i))
157 DBG(" %s", buffer_names[i]);
158 }
159 DBG("\n");
160 }
161 intelClearWithBlit(ctx, blit_mask);
162 }
163
164 if (tri_mask) {
165 if (INTEL_DEBUG & DEBUG_BLIT) {
166 DBG("tri clear:");
167 for (i = 0; i < BUFFER_COUNT; i++) {
168 if (tri_mask & (1 << i))
169 DBG(" %s", buffer_names[i]);
170 }
171 DBG("\n");
172 }
173 _mesa_meta_clear(&intel->ctx, tri_mask);
174 }
175
176 if (swrast_mask) {
177 if (INTEL_DEBUG & DEBUG_BLIT) {
178 DBG("swrast clear:");
179 for (i = 0; i < BUFFER_COUNT; i++) {
180 if (swrast_mask & (1 << i))
181 DBG(" %s", buffer_names[i]);
182 }
183 DBG("\n");
184 }
185 _swrast_Clear(ctx, swrast_mask);
186 }
187 }
188
189
190 void
191 intelInitClearFuncs(struct dd_function_table *functions)
192 {
193 functions->Clear = intelClear;
194 }