git.libre-soc.org Git - mesa.git/blob - src/mesa/drivers/dri/intel/intel

1 /**************************************************************************

2 *

5 *

6 * Permission is hereby granted, free of charge, to any person obtaining a

7 * copy of this software and associated documentation files (the

8 * "Software"), to deal in the Software without restriction, including

9 * without limitation the rights to use, copy, modify, merge, publish,

10 * distribute, sub license, and/or sell copies of the Software, and to

11 * permit persons to whom the Software is furnished to do so, subject to

12 * the following conditions:

13 *

14 * The above copyright notice and this permission notice (including the

15 * next paragraph) shall be included in all copies or substantial portions

16 * of the Software.

17 *

18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS

19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.

21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR

22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,

23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE

24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

25 *

26 **************************************************************************/

28 /* Provide additional functionality on top of bufmgr buffers:

29 * - 2d semantics and blit operations

30 * - refcounting of buffers for multiple images in a buffer.

31 * - refcounting of buffer mappings.

32 * - some logic for moving the buffers to the best memory pools for

33 * given operations.

34 *

35 * Most of this is to make it easier to implement the fixed-layout

36 * mipmap tree required by intel hardware in the face of GL's

37 * programming interface where each image can be specifed in random

38 * order and it isn't clear what layout the tree should have until the

39 * last moment.

40 */

42 #include <sys/ioctl.h>

43 #include <errno.h>

45 #include "intel_context.h"

46 #include "intel_regions.h"

47 #include "intel_blit.h"

48 #include "intel_buffer_objects.h"

49 #include "intel_bufmgr.h"

50 #include "intel_batchbuffer.h"

51 #include "intel_chipset.h"

53 #define FILE_DEBUG_FLAG DEBUG_REGION

55 /* This should be set to the maximum backtrace size desired.

56 * Set it to 0 to disable backtrace debugging.

57 */

58 #define DEBUG_BACKTRACE_SIZE 0

60 #if DEBUG_BACKTRACE_SIZE == 0

61 /* Use the standard debug output */

62 #define _DBG(...) DBG(__VA_ARGS__)

63 #else

64 /* Use backtracing debug output */

65 #define _DBG(...) {debug_backtrace(); DBG(__VA_ARGS__);}

67 /* Backtracing debug support */

68 #include <execinfo.h>

70 static void

71 debug_backtrace(void)

72 {

73 void *trace[DEBUG_BACKTRACE_SIZE];

74 char **strings = NULL;

75 int traceSize;

76 register int i;

    traceSize = backtrace(trace, DEBUG_BACKTRACE_SIZE);

    strings = backtrace_symbols(trace, traceSize);

80 if (strings == NULL) {

81 DBG("no backtrace:");

82 return;

83 }

85 /* Spit out all the strings with a colon separator. Ignore

86 * the first, since we don't really care about the call

87 * to debug_backtrace() itself. Skip until the final "/" in

88 * the trace to avoid really long lines.

89 */

    for (i = 1; i < traceSize; i++) {

       char *p = strings[i], *slash = strings[i];

92 while (*p) {

          if (*p++ == '/') {

94 slash = p;

95 }

96 }

       DBG("%s:", slash);

99 }

100

101 /* Free up the memory, and we're done */

102 free(strings);

103 }

105 #endif

109 /* XXX: Thread safety?

110 */

111 GLubyte *

 intel_region_map(struct intel_context *intel, struct intel_region *region)

113 {

114 intelFlush(&intel->ctx);

115

    _DBG("%s %p\n", __FUNCTION__, region);

117 if (!region->map_refcount++) {

118 if (region->pbo)

119 intel_region_cow(intel, region);

120

       if (region->tiling != I915_TILING_NONE &&

122 intel->intelScreen->kernel_exec_fencing)

123 drm_intel_gem_bo_map_gtt(region->buffer);

124 else

          dri_bo_map(region->buffer, GL_TRUE);

       region->map = region->buffer->virtual;

127 }

128

129 return region->map;

130 }

131

132 void

 intel_region_unmap(struct intel_context *intel, struct intel_region *region)

134 {

    _DBG("%s %p\n", __FUNCTION__, region);

136 if (!--region->map_refcount) {

       if (region->tiling != I915_TILING_NONE &&

138 intel->intelScreen->kernel_exec_fencing)

139 drm_intel_gem_bo_unmap_gtt(region->buffer);

140 else

141 dri_bo_unmap(region->buffer);

142 region->map = NULL;

143 }

144 }

145

146 static struct intel_region *

 intel_region_alloc_internal(struct intel_context *intel,

148 GLuint cpp,

149 GLuint width, GLuint height, GLuint pitch,

150 dri_bo *buffer)

151 {

152 struct intel_region *region;

153

154 if (buffer == NULL) {

       _DBG("%s <-- NULL\n", __FUNCTION__);

156 return NULL;

157 }

158

    region = calloc(sizeof(*region), 1);

160 region->cpp = cpp;

161 region->width = width;

162 region->height = height;

163 region->pitch = pitch;

164 region->refcount = 1;

165 region->buffer = buffer;

166

167 /* Default to no tiling */

168 region->tiling = I915_TILING_NONE;

169 region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;

170

    _DBG("%s <-- %p\n", __FUNCTION__, region);

172 return region;

173 }

174

175 struct intel_region *

 intel_region_alloc(struct intel_context *intel,

177 uint32_t tiling,

178 GLuint cpp, GLuint width, GLuint height, GLuint pitch,

179 GLboolean expect_accelerated_upload)

180 {

181 dri_bo *buffer;

182 struct intel_region *region;

183

184 /* If we're tiled, our allocations are in 8 or 32-row blocks, so

185 * failure to align our height means that we won't allocate enough pages.

186 *

187 * If we're untiled, we still have to align to 2 rows high because the

188 * data port accesses 2x2 blocks even if the bottom row isn't to be

189 * rendered, so failure to align means we could walk off the end of the

190 * GTT and fault.

191 */

192 if (tiling == I915_TILING_X)

       height = ALIGN(height, 8);

194 else if (tiling == I915_TILING_Y)

       height = ALIGN(height, 32);

196 else

       height = ALIGN(height, 2);

198

199 /* If we're untiled, we have to align to 2 rows high because the

200 * data port accesses 2x2 blocks even if the bottom row isn't to be

201 * rendered, so failure to align means we could walk off the end of the

202 * GTT and fault.

203 */

    height = ALIGN(height, 2);

205

206 if (expect_accelerated_upload) {

       buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",

                                              pitch * cpp * height, 64);

209 } else {

       buffer = drm_intel_bo_alloc(intel->bufmgr, "region",

                                   pitch * cpp * height, 64);

212 }

213

    region = intel_region_alloc_internal(intel, cpp, width, height,

215 pitch, buffer);

216

217 if (tiling != I915_TILING_NONE) {

       assert(((pitch * cpp) & 127) == 0);

       drm_intel_bo_set_tiling(buffer, &tiling, pitch * cpp);

       drm_intel_bo_get_tiling(buffer, &region->tiling, &region->bit_6_swizzle);

221 }

222

223 return region;

224 }

225

226 struct intel_region *

 intel_region_alloc_for_handle(struct intel_context *intel,

228 GLuint cpp,

229 GLuint width, GLuint height, GLuint pitch,

230 GLuint handle, const char *name)

231 {

232 struct intel_region *region;

233 dri_bo *buffer;

234 int ret;

235

    buffer = intel_bo_gem_create_from_name(intel->bufmgr, name, handle);

237

    region = intel_region_alloc_internal(intel, cpp,

239 width, height, pitch, buffer);

240 if (region == NULL)

241 return region;

242

    ret = dri_bo_get_tiling(region->buffer, &region->tiling,

244 &region->bit_6_swizzle);

    if (ret != 0) {

       fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",

               handle, name, strerror(-ret));

248 intel_region_release(&region);

249 return NULL;

250 }

251

252 return region;

253 }

254

255 void

 intel_region_reference(struct intel_region **dst, struct intel_region *src)

257 {

258 if (src)

       _DBG("%s %p %d\n", __FUNCTION__, src, src->refcount);

260

261 assert(*dst == NULL);

262 if (src) {

263 src->refcount++;

264 *dst = src;

265 }

266 }

267

268 void

 intel_region_release(struct intel_region **region_handle)

270 {

271 struct intel_region *region = *region_handle;

272

273 if (region == NULL) {

       _DBG("%s NULL\n", __FUNCTION__);

275 return;

276 }

277

    _DBG("%s %p %d\n", __FUNCTION__, region, region->refcount - 1);

279

    ASSERT(region->refcount > 0);

281 region->refcount--;

282

    if (region->refcount == 0) {

       assert(region->map_refcount == 0);

285

286 if (region->pbo)

287 region->pbo->region = NULL;

288 region->pbo = NULL;

289 dri_bo_unreference(region->buffer);

290

       if (region->classic_map != NULL) {

292 drmUnmap(region->classic_map,

                         region->pitch * region->cpp * region->height);

294 }

295

296 free(region);

297 }

298 *region_handle = NULL;

299 }

300

301 /*

302 * XXX Move this into core Mesa?

303 */

304 void

305 _mesa_copy_rect(GLubyte * dst,

306 GLuint cpp,

307 GLuint dst_pitch,

308 GLuint dst_x,

309 GLuint dst_y,

310 GLuint width,

311 GLuint height,

312 const GLubyte * src,

313 GLuint src_pitch, GLuint src_x, GLuint src_y)

314 {

315 GLuint i;

316

317 dst_pitch *= cpp;

318 src_pitch *= cpp;

319 dst += dst_x * cpp;

320 src += src_x * cpp;

321 dst += dst_y * dst_pitch;

322 src += src_y * dst_pitch;

323 width *= cpp;

324

    if (width == dst_pitch && width == src_pitch)

       memcpy(dst, src, height * width);

327 else {

       for (i = 0; i < height; i++) {

          memcpy(dst, src, width);

330 dst += dst_pitch;

331 src += src_pitch;

332 }

333 }

334 }

335

336

337 /* Upload data to a rectangular sub-region. Lots of choices how to do this:

338 *

339 * - memcpy by span to current destination

340 * - upload data as new buffer and blit

341 *

342 * Currently always memcpy.

343 */

344 void

 intel_region_data(struct intel_context *intel,

346 struct intel_region *dst,

347 GLuint dst_offset,

348 GLuint dstx, GLuint dsty,

349 const void *src, GLuint src_pitch,

350 GLuint srcx, GLuint srcy, GLuint width, GLuint height)

351 {

    _DBG("%s\n", __FUNCTION__);

353

354 if (intel == NULL)

355 return;

356

357 if (dst->pbo) {

       if (dstx == 0 &&

           dsty == 0 && width == dst->pitch && height == dst->height)

360 intel_region_release_pbo(intel, dst);

361 else

362 intel_region_cow(intel, dst);

363 }

364

    _mesa_copy_rect(intel_region_map(intel, dst) + dst_offset,

366 dst->cpp,

367 dst->pitch,

                    dstx, dsty, width, height, src, src_pitch, srcx, srcy);

369

370 intel_region_unmap(intel, dst);

371 }

372

373 /* Copy rectangular sub-regions. Need better logic about when to

374 * push buffers into AGP - will currently do so whenever possible.

375 */

376 GLboolean

 intel_region_copy(struct intel_context *intel,

378 struct intel_region *dst,

379 GLuint dst_offset,

380 GLuint dstx, GLuint dsty,

381 struct intel_region *src,

382 GLuint src_offset,

383 GLuint srcx, GLuint srcy, GLuint width, GLuint height,

384 GLenum logicop)

385 {

    _DBG("%s\n", __FUNCTION__);

387

388 if (intel == NULL)

389 return GL_FALSE;

390

391 if (dst->pbo) {

       if (dstx == 0 &&

           dsty == 0 && width == dst->pitch && height == dst->height)

394 intel_region_release_pbo(intel, dst);

395 else

396 intel_region_cow(intel, dst);

397 }

398

    assert(src->cpp == dst->cpp);

400

401 return intelEmitCopyBlit(intel,

402 dst->cpp,

                             src->pitch, src->buffer, src_offset, src->tiling,

                             dst->pitch, dst->buffer, dst_offset, dst->tiling,

                             srcx, srcy, dstx, dsty, width, height,

406 logicop);

407 }

408

409 /* Attach to a pbo, discarding our data. Effectively zero-copy upload

410 * the pbo's data.

411 */

412 void

 intel_region_attach_pbo(struct intel_context *intel,

414 struct intel_region *region,

415 struct intel_buffer_object *pbo)

416 {

417 dri_bo *buffer;

418

    if (region->pbo == pbo)

420 return;

421

    _DBG("%s %p %p\n", __FUNCTION__, region, pbo);

423

424 /* If there is already a pbo attached, break the cow tie now.

425 * Don't call intel_region_release_pbo() as that would

426 * unnecessarily allocate a new buffer we would have to immediately

427 * discard.

428 */

429 if (region->pbo) {

430 region->pbo->region = NULL;

431 region->pbo = NULL;

432 }

433

434 if (region->buffer) {

435 dri_bo_unreference(region->buffer);

436 region->buffer = NULL;

437 }

438

439 /* make sure pbo has a buffer of its own */

    buffer = intel_bufferobj_buffer(intel, pbo, INTEL_WRITE_FULL);

441

442 region->pbo = pbo;

443 region->pbo->region = region;

444 dri_bo_reference(buffer);

445 region->buffer = buffer;

446 }

447

448

449 /* Break the COW tie to the pbo and allocate a new buffer.

450 * The pbo gets to keep the data.

451 */

452 void

 intel_region_release_pbo(struct intel_context *intel,

454 struct intel_region *region)

455 {

    _DBG("%s %p\n", __FUNCTION__, region);

    assert(region->buffer == region->pbo->buffer);

458 region->pbo->region = NULL;

459 region->pbo = NULL;

460 dri_bo_unreference(region->buffer);

461 region->buffer = NULL;

462

    region->buffer = dri_bo_alloc(intel->bufmgr, "region",

                                  region->pitch * region->cpp * region->height,

465 64);

466 }

467

468 /* Break the COW tie to the pbo. Both the pbo and the region end up

469 * with a copy of the data.

470 */

471 void

 intel_region_cow(struct intel_context *intel, struct intel_region *region)

473 {

    struct intel_buffer_object *pbo = region->pbo;

475 GLboolean ok;

476

477 intel_region_release_pbo(intel, region);

478

    assert(region->cpp * region->pitch * region->height == pbo->Base.Size);

480

    _DBG("%s %p (%d bytes)\n", __FUNCTION__, region, pbo->Base.Size);

482

483 /* Now blit from the texture buffer to the new buffer:

484 */

485

486 ok = intelEmitCopyBlit(intel,

487 region->cpp,

                           region->pitch, pbo->buffer, 0, region->tiling,

                           region->pitch, region->buffer, 0, region->tiling,

                           0, 0, 0, 0,

491 region->pitch, region->height,

492 GL_COPY);

493 assert(ok);

494 }

495

496 dri_bo *

 intel_region_buffer(struct intel_context *intel,

498 struct intel_region *region, GLuint flag)

499 {

500 if (region->pbo) {

501 if (flag == INTEL_WRITE_PART)

502 intel_region_cow(intel, region);

503 else if (flag == INTEL_WRITE_FULL)

504 intel_region_release_pbo(intel, region);

505 }

506

507 return region->buffer;

508 }