i965: defined BRW_MAX_MRF
[mesa.git] / src / mesa / drivers / dri / intel / intel_regions.c
1 /**************************************************************************
2 *
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /* Provide additional functionality on top of bufmgr buffers:
29 * - 2d semantics and blit operations
30 * - refcounting of buffers for multiple images in a buffer.
31 * - refcounting of buffer mappings.
32 * - some logic for moving the buffers to the best memory pools for
33 * given operations.
34 *
35 * Most of this is to make it easier to implement the fixed-layout
36 * mipmap tree required by intel hardware in the face of GL's
37 * programming interface where each image can be specifed in random
38 * order and it isn't clear what layout the tree should have until the
39 * last moment.
40 */
41
42 #include <sys/ioctl.h>
43 #include <errno.h>
44
45 #include "intel_context.h"
46 #include "intel_regions.h"
47 #include "intel_blit.h"
48 #include "intel_buffer_objects.h"
49 #include "intel_bufmgr.h"
50 #include "intel_batchbuffer.h"
51 #include "intel_chipset.h"
52
53 #define FILE_DEBUG_FLAG DEBUG_REGION
54
55 /* This should be set to the maximum backtrace size desired.
56 * Set it to 0 to disable backtrace debugging.
57 */
58 #define DEBUG_BACKTRACE_SIZE 0
59
60 #if DEBUG_BACKTRACE_SIZE == 0
61 /* Use the standard debug output */
62 #define _DBG(...) DBG(__VA_ARGS__)
63 #else
64 /* Use backtracing debug output */
65 #define _DBG(...) {debug_backtrace(); DBG(__VA_ARGS__);}
66
67 /* Backtracing debug support */
68 #include <execinfo.h>
69
70 static void
71 debug_backtrace(void)
72 {
73 void *trace[DEBUG_BACKTRACE_SIZE];
74 char **strings = NULL;
75 int traceSize;
76 register int i;
77
78 traceSize = backtrace(trace, DEBUG_BACKTRACE_SIZE);
79 strings = backtrace_symbols(trace, traceSize);
80 if (strings == NULL) {
81 DBG("no backtrace:");
82 return;
83 }
84
85 /* Spit out all the strings with a colon separator. Ignore
86 * the first, since we don't really care about the call
87 * to debug_backtrace() itself. Skip until the final "/" in
88 * the trace to avoid really long lines.
89 */
90 for (i = 1; i < traceSize; i++) {
91 char *p = strings[i], *slash = strings[i];
92 while (*p) {
93 if (*p++ == '/') {
94 slash = p;
95 }
96 }
97
98 DBG("%s:", slash);
99 }
100
101 /* Free up the memory, and we're done */
102 free(strings);
103 }
104
105 #endif
106
107
108
109 /* XXX: Thread safety?
110 */
111 GLubyte *
112 intel_region_map(struct intel_context *intel, struct intel_region *region)
113 {
114 _DBG("%s %p\n", __FUNCTION__, region);
115 if (!region->map_refcount++) {
116 if (region->pbo)
117 intel_region_cow(intel, region);
118
119 if (region->tiling != I915_TILING_NONE &&
120 intel->intelScreen->kernel_exec_fencing)
121 drm_intel_gem_bo_map_gtt(region->buffer);
122 else
123 dri_bo_map(region->buffer, GL_TRUE);
124 region->map = region->buffer->virtual;
125 }
126
127 return region->map;
128 }
129
130 void
131 intel_region_unmap(struct intel_context *intel, struct intel_region *region)
132 {
133 _DBG("%s %p\n", __FUNCTION__, region);
134 if (!--region->map_refcount) {
135 if (region->tiling != I915_TILING_NONE &&
136 intel->intelScreen->kernel_exec_fencing)
137 drm_intel_gem_bo_unmap_gtt(region->buffer);
138 else
139 dri_bo_unmap(region->buffer);
140 region->map = NULL;
141 }
142 }
143
144 static struct intel_region *
145 intel_region_alloc_internal(struct intel_context *intel,
146 GLuint cpp,
147 GLuint width, GLuint height, GLuint pitch,
148 dri_bo *buffer)
149 {
150 struct intel_region *region;
151
152 if (buffer == NULL) {
153 _DBG("%s <-- NULL\n", __FUNCTION__);
154 return NULL;
155 }
156
157 region = calloc(sizeof(*region), 1);
158 region->cpp = cpp;
159 region->width = width;
160 region->height = height;
161 region->pitch = pitch;
162 region->refcount = 1;
163 region->buffer = buffer;
164
165 /* Default to no tiling */
166 region->tiling = I915_TILING_NONE;
167 region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
168
169 _DBG("%s <-- %p\n", __FUNCTION__, region);
170 return region;
171 }
172
173 struct intel_region *
174 intel_region_alloc(struct intel_context *intel,
175 uint32_t tiling,
176 GLuint cpp, GLuint width, GLuint height, GLuint pitch,
177 GLboolean expect_accelerated_upload)
178 {
179 dri_bo *buffer;
180 struct intel_region *region;
181
182 if (expect_accelerated_upload) {
183 buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
184 pitch * cpp * height, 64);
185 } else {
186 buffer = drm_intel_bo_alloc(intel->bufmgr, "region",
187 pitch * cpp * height, 64);
188 }
189
190 region = intel_region_alloc_internal(intel, cpp, width, height,
191 pitch, buffer);
192
193 if (tiling != I915_TILING_NONE) {
194 assert(((pitch * cpp) & 127) == 0);
195 drm_intel_bo_set_tiling(buffer, &tiling, pitch * cpp);
196 drm_intel_bo_get_tiling(buffer, &region->tiling, &region->bit_6_swizzle);
197 }
198
199 return region;
200 }
201
202 struct intel_region *
203 intel_region_alloc_for_handle(struct intel_context *intel,
204 GLuint cpp,
205 GLuint width, GLuint height, GLuint pitch,
206 GLuint handle, const char *name)
207 {
208 struct intel_region *region;
209 dri_bo *buffer;
210 int ret;
211
212 buffer = intel_bo_gem_create_from_name(intel->bufmgr, name, handle);
213
214 region = intel_region_alloc_internal(intel, cpp,
215 width, height, pitch, buffer);
216 if (region == NULL)
217 return region;
218
219 ret = dri_bo_get_tiling(region->buffer, &region->tiling,
220 &region->bit_6_swizzle);
221 if (ret != 0) {
222 fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",
223 handle, name, strerror(-ret));
224 intel_region_release(&region);
225 return NULL;
226 }
227
228 return region;
229 }
230
231 void
232 intel_region_reference(struct intel_region **dst, struct intel_region *src)
233 {
234 if (src)
235 _DBG("%s %p %d\n", __FUNCTION__, src, src->refcount);
236
237 assert(*dst == NULL);
238 if (src) {
239 src->refcount++;
240 *dst = src;
241 }
242 }
243
244 void
245 intel_region_release(struct intel_region **region_handle)
246 {
247 struct intel_region *region = *region_handle;
248
249 if (region == NULL) {
250 _DBG("%s NULL\n", __FUNCTION__);
251 return;
252 }
253
254 _DBG("%s %p %d\n", __FUNCTION__, region, region->refcount - 1);
255
256 ASSERT(region->refcount > 0);
257 region->refcount--;
258
259 if (region->refcount == 0) {
260 assert(region->map_refcount == 0);
261
262 if (region->pbo)
263 region->pbo->region = NULL;
264 region->pbo = NULL;
265 dri_bo_unreference(region->buffer);
266
267 if (region->classic_map != NULL) {
268 drmUnmap(region->classic_map,
269 region->pitch * region->cpp * region->height);
270 }
271
272 free(region);
273 }
274 *region_handle = NULL;
275 }
276
277 /*
278 * XXX Move this into core Mesa?
279 */
280 void
281 _mesa_copy_rect(GLubyte * dst,
282 GLuint cpp,
283 GLuint dst_pitch,
284 GLuint dst_x,
285 GLuint dst_y,
286 GLuint width,
287 GLuint height,
288 const GLubyte * src,
289 GLuint src_pitch, GLuint src_x, GLuint src_y)
290 {
291 GLuint i;
292
293 dst_pitch *= cpp;
294 src_pitch *= cpp;
295 dst += dst_x * cpp;
296 src += src_x * cpp;
297 dst += dst_y * dst_pitch;
298 src += src_y * dst_pitch;
299 width *= cpp;
300
301 if (width == dst_pitch && width == src_pitch)
302 memcpy(dst, src, height * width);
303 else {
304 for (i = 0; i < height; i++) {
305 memcpy(dst, src, width);
306 dst += dst_pitch;
307 src += src_pitch;
308 }
309 }
310 }
311
312
313 /* Upload data to a rectangular sub-region. Lots of choices how to do this:
314 *
315 * - memcpy by span to current destination
316 * - upload data as new buffer and blit
317 *
318 * Currently always memcpy.
319 */
320 void
321 intel_region_data(struct intel_context *intel,
322 struct intel_region *dst,
323 GLuint dst_offset,
324 GLuint dstx, GLuint dsty,
325 const void *src, GLuint src_pitch,
326 GLuint srcx, GLuint srcy, GLuint width, GLuint height)
327 {
328 _DBG("%s\n", __FUNCTION__);
329
330 if (intel == NULL)
331 return;
332
333 if (dst->pbo) {
334 if (dstx == 0 &&
335 dsty == 0 && width == dst->pitch && height == dst->height)
336 intel_region_release_pbo(intel, dst);
337 else
338 intel_region_cow(intel, dst);
339 }
340
341 LOCK_HARDWARE(intel);
342 _mesa_copy_rect(intel_region_map(intel, dst) + dst_offset,
343 dst->cpp,
344 dst->pitch,
345 dstx, dsty, width, height, src, src_pitch, srcx, srcy);
346
347 intel_region_unmap(intel, dst);
348 UNLOCK_HARDWARE(intel);
349 }
350
351 /* Copy rectangular sub-regions. Need better logic about when to
352 * push buffers into AGP - will currently do so whenever possible.
353 */
354 GLboolean
355 intel_region_copy(struct intel_context *intel,
356 struct intel_region *dst,
357 GLuint dst_offset,
358 GLuint dstx, GLuint dsty,
359 struct intel_region *src,
360 GLuint src_offset,
361 GLuint srcx, GLuint srcy, GLuint width, GLuint height,
362 GLenum logicop)
363 {
364 _DBG("%s\n", __FUNCTION__);
365
366 if (intel == NULL)
367 return GL_FALSE;
368
369 if (dst->pbo) {
370 if (dstx == 0 &&
371 dsty == 0 && width == dst->pitch && height == dst->height)
372 intel_region_release_pbo(intel, dst);
373 else
374 intel_region_cow(intel, dst);
375 }
376
377 assert(src->cpp == dst->cpp);
378
379 return intelEmitCopyBlit(intel,
380 dst->cpp,
381 src->pitch, src->buffer, src_offset, src->tiling,
382 dst->pitch, dst->buffer, dst_offset, dst->tiling,
383 srcx, srcy, dstx, dsty, width, height,
384 logicop);
385 }
386
387 /* Attach to a pbo, discarding our data. Effectively zero-copy upload
388 * the pbo's data.
389 */
390 void
391 intel_region_attach_pbo(struct intel_context *intel,
392 struct intel_region *region,
393 struct intel_buffer_object *pbo)
394 {
395 dri_bo *buffer;
396
397 if (region->pbo == pbo)
398 return;
399
400 _DBG("%s %p %p\n", __FUNCTION__, region, pbo);
401
402 /* If there is already a pbo attached, break the cow tie now.
403 * Don't call intel_region_release_pbo() as that would
404 * unnecessarily allocate a new buffer we would have to immediately
405 * discard.
406 */
407 if (region->pbo) {
408 region->pbo->region = NULL;
409 region->pbo = NULL;
410 }
411
412 if (region->buffer) {
413 dri_bo_unreference(region->buffer);
414 region->buffer = NULL;
415 }
416
417 /* make sure pbo has a buffer of its own */
418 buffer = intel_bufferobj_buffer(intel, pbo, INTEL_WRITE_FULL);
419
420 region->pbo = pbo;
421 region->pbo->region = region;
422 dri_bo_reference(buffer);
423 region->buffer = buffer;
424 }
425
426
427 /* Break the COW tie to the pbo and allocate a new buffer.
428 * The pbo gets to keep the data.
429 */
430 void
431 intel_region_release_pbo(struct intel_context *intel,
432 struct intel_region *region)
433 {
434 _DBG("%s %p\n", __FUNCTION__, region);
435 assert(region->buffer == region->pbo->buffer);
436 region->pbo->region = NULL;
437 region->pbo = NULL;
438 dri_bo_unreference(region->buffer);
439 region->buffer = NULL;
440
441 region->buffer = dri_bo_alloc(intel->bufmgr, "region",
442 region->pitch * region->cpp * region->height,
443 64);
444 }
445
446 /* Break the COW tie to the pbo. Both the pbo and the region end up
447 * with a copy of the data.
448 */
449 void
450 intel_region_cow(struct intel_context *intel, struct intel_region *region)
451 {
452 struct intel_buffer_object *pbo = region->pbo;
453
454 intel_region_release_pbo(intel, region);
455
456 assert(region->cpp * region->pitch * region->height == pbo->Base.Size);
457
458 _DBG("%s %p (%d bytes)\n", __FUNCTION__, region, pbo->Base.Size);
459
460 /* Now blit from the texture buffer to the new buffer:
461 */
462
463 LOCK_HARDWARE(intel);
464 assert(intelEmitCopyBlit(intel,
465 region->cpp,
466 region->pitch, pbo->buffer, 0, region->tiling,
467 region->pitch, region->buffer, 0, region->tiling,
468 0, 0, 0, 0,
469 region->pitch, region->height,
470 GL_COPY));
471 UNLOCK_HARDWARE(intel);
472 }
473
474 dri_bo *
475 intel_region_buffer(struct intel_context *intel,
476 struct intel_region *region, GLuint flag)
477 {
478 if (region->pbo) {
479 if (flag == INTEL_WRITE_PART)
480 intel_region_cow(intel, region);
481 else if (flag == INTEL_WRITE_FULL)
482 intel_region_release_pbo(intel, region);
483 }
484
485 return region->buffer;
486 }
487
488 static struct intel_region *
489 intel_recreate_static(struct intel_context *intel,
490 const char *name,
491 struct intel_region *region,
492 intelRegion *region_desc)
493 {
494 intelScreenPrivate *intelScreen = intel->intelScreen;
495 int ret;
496
497 if (region == NULL) {
498 region = calloc(sizeof(*region), 1);
499 region->refcount = 1;
500 _DBG("%s creating new region %p\n", __FUNCTION__, region);
501 }
502 else {
503 _DBG("%s %p\n", __FUNCTION__, region);
504 }
505
506 if (intel->ctx.Visual.rgbBits == 24)
507 region->cpp = 4;
508 else
509 region->cpp = intel->ctx.Visual.rgbBits / 8;
510 region->pitch = intelScreen->pitch;
511 region->width = intelScreen->width;
512 region->height = intelScreen->height;
513
514 if (region->buffer != NULL) {
515 dri_bo_unreference(region->buffer);
516 region->buffer = NULL;
517 }
518
519 if (intel->ttm) {
520 assert(region_desc->bo_handle != -1);
521 region->buffer = intel_bo_gem_create_from_name(intel->bufmgr,
522 name,
523 region_desc->bo_handle);
524
525 ret = dri_bo_get_tiling(region->buffer, &region->tiling,
526 &region->bit_6_swizzle);
527 if (ret != 0) {
528 fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",
529 region_desc->bo_handle, name, strerror(-ret));
530 intel_region_release(&region);
531 return NULL;
532 }
533 } else {
534 if (region->classic_map != NULL) {
535 drmUnmap(region->classic_map,
536 region->pitch * region->cpp * region->height);
537 region->classic_map = NULL;
538 }
539 ret = drmMap(intel->driFd, region_desc->handle,
540 region->pitch * region->cpp * region->height,
541 &region->classic_map);
542 if (ret != 0) {
543 fprintf(stderr, "Failed to drmMap %s buffer\n", name);
544 free(region);
545 return NULL;
546 }
547
548 region->buffer = intel_bo_fake_alloc_static(intel->bufmgr,
549 name,
550 region_desc->offset,
551 region->pitch * region->cpp *
552 region->height,
553 region->classic_map);
554
555 /* The sarea just gives us a boolean for whether it's tiled or not,
556 * instead of which tiling mode it is. Guess.
557 */
558 if (region_desc->tiled) {
559 if (IS_965(intel->intelScreen->deviceID) &&
560 region_desc == &intelScreen->depth)
561 region->tiling = I915_TILING_Y;
562 else
563 region->tiling = I915_TILING_X;
564 } else {
565 region->tiling = I915_TILING_NONE;
566 }
567
568 region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
569 }
570
571 assert(region->buffer != NULL);
572
573 return region;
574 }
575
576 /**
577 * Create intel_region structs to describe the static front, back, and depth
578 * buffers created by the xserver.
579 *
580 * Although FBO's mean we now no longer use these as render targets in
581 * all circumstances, they won't go away until the back and depth
582 * buffers become private, and the front buffer will remain even then.
583 *
584 * Note that these don't allocate video memory, just describe
585 * allocations alread made by the X server.
586 */
587 void
588 intel_recreate_static_regions(struct intel_context *intel)
589 {
590 intelScreenPrivate *intelScreen = intel->intelScreen;
591
592 intel->front_region =
593 intel_recreate_static(intel, "front",
594 intel->front_region,
595 &intelScreen->front);
596
597 intel->back_region =
598 intel_recreate_static(intel, "back",
599 intel->back_region,
600 &intelScreen->back);
601
602 /* Still assumes front.cpp == depth.cpp. We can kill this when we move to
603 * private buffers.
604 */
605 intel->depth_region =
606 intel_recreate_static(intel, "depth",
607 intel->depth_region,
608 &intelScreen->depth);
609 }