Merge branch 'mesa_7_5_branch'
[mesa.git] / src / mesa / drivers / dri / intel / intel_regions.c
1 /**************************************************************************
2 *
3 * Copyright 2006 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 /* Provide additional functionality on top of bufmgr buffers:
29 * - 2d semantics and blit operations
30 * - refcounting of buffers for multiple images in a buffer.
31 * - refcounting of buffer mappings.
32 * - some logic for moving the buffers to the best memory pools for
33 * given operations.
34 *
35 * Most of this is to make it easier to implement the fixed-layout
36 * mipmap tree required by intel hardware in the face of GL's
37 * programming interface where each image can be specifed in random
38 * order and it isn't clear what layout the tree should have until the
39 * last moment.
40 */
41
42 #include <sys/ioctl.h>
43 #include <errno.h>
44
45 #include "intel_context.h"
46 #include "intel_regions.h"
47 #include "intel_blit.h"
48 #include "intel_buffer_objects.h"
49 #include "intel_bufmgr.h"
50 #include "intel_batchbuffer.h"
51 #include "intel_chipset.h"
52
53 #define FILE_DEBUG_FLAG DEBUG_REGION
54
55 /* This should be set to the maximum backtrace size desired.
56 * Set it to 0 to disable backtrace debugging.
57 */
58 #define DEBUG_BACKTRACE_SIZE 0
59
60 #if DEBUG_BACKTRACE_SIZE == 0
61 /* Use the standard debug output */
62 #define _DBG(...) DBG(__VA_ARGS__)
63 #else
64 /* Use backtracing debug output */
65 #define _DBG(...) {debug_backtrace(); DBG(__VA_ARGS__);}
66
67 /* Backtracing debug support */
68 #include <execinfo.h>
69
70 static void
71 debug_backtrace(void)
72 {
73 void *trace[DEBUG_BACKTRACE_SIZE];
74 char **strings = NULL;
75 int traceSize;
76 register int i;
77
78 traceSize = backtrace(trace, DEBUG_BACKTRACE_SIZE);
79 strings = backtrace_symbols(trace, traceSize);
80 if (strings == NULL) {
81 DBG("no backtrace:");
82 return;
83 }
84
85 /* Spit out all the strings with a colon separator. Ignore
86 * the first, since we don't really care about the call
87 * to debug_backtrace() itself. Skip until the final "/" in
88 * the trace to avoid really long lines.
89 */
90 for (i = 1; i < traceSize; i++) {
91 char *p = strings[i], *slash = strings[i];
92 while (*p) {
93 if (*p++ == '/') {
94 slash = p;
95 }
96 }
97
98 DBG("%s:", slash);
99 }
100
101 /* Free up the memory, and we're done */
102 free(strings);
103 }
104
105 #endif
106
107
108
109 /* XXX: Thread safety?
110 */
111 GLubyte *
112 intel_region_map(struct intel_context *intel, struct intel_region *region)
113 {
114 intelFlush(&intel->ctx);
115
116 _DBG("%s %p\n", __FUNCTION__, region);
117 if (!region->map_refcount++) {
118 if (region->pbo)
119 intel_region_cow(intel, region);
120
121 if (region->tiling != I915_TILING_NONE &&
122 intel->intelScreen->kernel_exec_fencing)
123 drm_intel_gem_bo_map_gtt(region->buffer);
124 else
125 dri_bo_map(region->buffer, GL_TRUE);
126 region->map = region->buffer->virtual;
127 }
128
129 return region->map;
130 }
131
132 void
133 intel_region_unmap(struct intel_context *intel, struct intel_region *region)
134 {
135 _DBG("%s %p\n", __FUNCTION__, region);
136 if (!--region->map_refcount) {
137 if (region->tiling != I915_TILING_NONE &&
138 intel->intelScreen->kernel_exec_fencing)
139 drm_intel_gem_bo_unmap_gtt(region->buffer);
140 else
141 dri_bo_unmap(region->buffer);
142 region->map = NULL;
143 }
144 }
145
146 static struct intel_region *
147 intel_region_alloc_internal(struct intel_context *intel,
148 GLuint cpp,
149 GLuint width, GLuint height, GLuint pitch,
150 dri_bo *buffer)
151 {
152 struct intel_region *region;
153
154 if (buffer == NULL) {
155 _DBG("%s <-- NULL\n", __FUNCTION__);
156 return NULL;
157 }
158
159 region = calloc(sizeof(*region), 1);
160 region->cpp = cpp;
161 region->width = width;
162 region->height = height;
163 region->pitch = pitch;
164 region->refcount = 1;
165 region->buffer = buffer;
166
167 /* Default to no tiling */
168 region->tiling = I915_TILING_NONE;
169 region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
170
171 _DBG("%s <-- %p\n", __FUNCTION__, region);
172 return region;
173 }
174
175 struct intel_region *
176 intel_region_alloc(struct intel_context *intel,
177 uint32_t tiling,
178 GLuint cpp, GLuint width, GLuint height, GLuint pitch,
179 GLboolean expect_accelerated_upload)
180 {
181 dri_bo *buffer;
182 struct intel_region *region;
183
184 if (expect_accelerated_upload) {
185 buffer = drm_intel_bo_alloc_for_render(intel->bufmgr, "region",
186 pitch * cpp * height, 64);
187 } else {
188 buffer = drm_intel_bo_alloc(intel->bufmgr, "region",
189 pitch * cpp * height, 64);
190 }
191
192 region = intel_region_alloc_internal(intel, cpp, width, height,
193 pitch, buffer);
194
195 if (tiling != I915_TILING_NONE) {
196 assert(((pitch * cpp) & 127) == 0);
197 drm_intel_bo_set_tiling(buffer, &tiling, pitch * cpp);
198 drm_intel_bo_get_tiling(buffer, &region->tiling, &region->bit_6_swizzle);
199 }
200
201 return region;
202 }
203
204 struct intel_region *
205 intel_region_alloc_for_handle(struct intel_context *intel,
206 GLuint cpp,
207 GLuint width, GLuint height, GLuint pitch,
208 GLuint handle, const char *name)
209 {
210 struct intel_region *region;
211 dri_bo *buffer;
212 int ret;
213
214 buffer = intel_bo_gem_create_from_name(intel->bufmgr, name, handle);
215
216 region = intel_region_alloc_internal(intel, cpp,
217 width, height, pitch, buffer);
218 if (region == NULL)
219 return region;
220
221 ret = dri_bo_get_tiling(region->buffer, &region->tiling,
222 &region->bit_6_swizzle);
223 if (ret != 0) {
224 fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",
225 handle, name, strerror(-ret));
226 intel_region_release(&region);
227 return NULL;
228 }
229
230 return region;
231 }
232
233 void
234 intel_region_reference(struct intel_region **dst, struct intel_region *src)
235 {
236 if (src)
237 _DBG("%s %p %d\n", __FUNCTION__, src, src->refcount);
238
239 assert(*dst == NULL);
240 if (src) {
241 src->refcount++;
242 *dst = src;
243 }
244 }
245
246 void
247 intel_region_release(struct intel_region **region_handle)
248 {
249 struct intel_region *region = *region_handle;
250
251 if (region == NULL) {
252 _DBG("%s NULL\n", __FUNCTION__);
253 return;
254 }
255
256 _DBG("%s %p %d\n", __FUNCTION__, region, region->refcount - 1);
257
258 ASSERT(region->refcount > 0);
259 region->refcount--;
260
261 if (region->refcount == 0) {
262 assert(region->map_refcount == 0);
263
264 if (region->pbo)
265 region->pbo->region = NULL;
266 region->pbo = NULL;
267 dri_bo_unreference(region->buffer);
268
269 if (region->classic_map != NULL) {
270 drmUnmap(region->classic_map,
271 region->pitch * region->cpp * region->height);
272 }
273
274 free(region);
275 }
276 *region_handle = NULL;
277 }
278
279 /*
280 * XXX Move this into core Mesa?
281 */
282 void
283 _mesa_copy_rect(GLubyte * dst,
284 GLuint cpp,
285 GLuint dst_pitch,
286 GLuint dst_x,
287 GLuint dst_y,
288 GLuint width,
289 GLuint height,
290 const GLubyte * src,
291 GLuint src_pitch, GLuint src_x, GLuint src_y)
292 {
293 GLuint i;
294
295 dst_pitch *= cpp;
296 src_pitch *= cpp;
297 dst += dst_x * cpp;
298 src += src_x * cpp;
299 dst += dst_y * dst_pitch;
300 src += src_y * dst_pitch;
301 width *= cpp;
302
303 if (width == dst_pitch && width == src_pitch)
304 memcpy(dst, src, height * width);
305 else {
306 for (i = 0; i < height; i++) {
307 memcpy(dst, src, width);
308 dst += dst_pitch;
309 src += src_pitch;
310 }
311 }
312 }
313
314
315 /* Upload data to a rectangular sub-region. Lots of choices how to do this:
316 *
317 * - memcpy by span to current destination
318 * - upload data as new buffer and blit
319 *
320 * Currently always memcpy.
321 */
322 void
323 intel_region_data(struct intel_context *intel,
324 struct intel_region *dst,
325 GLuint dst_offset,
326 GLuint dstx, GLuint dsty,
327 const void *src, GLuint src_pitch,
328 GLuint srcx, GLuint srcy, GLuint width, GLuint height)
329 {
330 _DBG("%s\n", __FUNCTION__);
331
332 if (intel == NULL)
333 return;
334
335 if (dst->pbo) {
336 if (dstx == 0 &&
337 dsty == 0 && width == dst->pitch && height == dst->height)
338 intel_region_release_pbo(intel, dst);
339 else
340 intel_region_cow(intel, dst);
341 }
342
343 LOCK_HARDWARE(intel);
344 _mesa_copy_rect(intel_region_map(intel, dst) + dst_offset,
345 dst->cpp,
346 dst->pitch,
347 dstx, dsty, width, height, src, src_pitch, srcx, srcy);
348
349 intel_region_unmap(intel, dst);
350 UNLOCK_HARDWARE(intel);
351 }
352
353 /* Copy rectangular sub-regions. Need better logic about when to
354 * push buffers into AGP - will currently do so whenever possible.
355 */
356 GLboolean
357 intel_region_copy(struct intel_context *intel,
358 struct intel_region *dst,
359 GLuint dst_offset,
360 GLuint dstx, GLuint dsty,
361 struct intel_region *src,
362 GLuint src_offset,
363 GLuint srcx, GLuint srcy, GLuint width, GLuint height,
364 GLenum logicop)
365 {
366 _DBG("%s\n", __FUNCTION__);
367
368 if (intel == NULL)
369 return GL_FALSE;
370
371 if (dst->pbo) {
372 if (dstx == 0 &&
373 dsty == 0 && width == dst->pitch && height == dst->height)
374 intel_region_release_pbo(intel, dst);
375 else
376 intel_region_cow(intel, dst);
377 }
378
379 assert(src->cpp == dst->cpp);
380
381 return intelEmitCopyBlit(intel,
382 dst->cpp,
383 src->pitch, src->buffer, src_offset, src->tiling,
384 dst->pitch, dst->buffer, dst_offset, dst->tiling,
385 srcx, srcy, dstx, dsty, width, height,
386 logicop);
387 }
388
389 /* Attach to a pbo, discarding our data. Effectively zero-copy upload
390 * the pbo's data.
391 */
392 void
393 intel_region_attach_pbo(struct intel_context *intel,
394 struct intel_region *region,
395 struct intel_buffer_object *pbo)
396 {
397 dri_bo *buffer;
398
399 if (region->pbo == pbo)
400 return;
401
402 _DBG("%s %p %p\n", __FUNCTION__, region, pbo);
403
404 /* If there is already a pbo attached, break the cow tie now.
405 * Don't call intel_region_release_pbo() as that would
406 * unnecessarily allocate a new buffer we would have to immediately
407 * discard.
408 */
409 if (region->pbo) {
410 region->pbo->region = NULL;
411 region->pbo = NULL;
412 }
413
414 if (region->buffer) {
415 dri_bo_unreference(region->buffer);
416 region->buffer = NULL;
417 }
418
419 /* make sure pbo has a buffer of its own */
420 buffer = intel_bufferobj_buffer(intel, pbo, INTEL_WRITE_FULL);
421
422 region->pbo = pbo;
423 region->pbo->region = region;
424 dri_bo_reference(buffer);
425 region->buffer = buffer;
426 }
427
428
429 /* Break the COW tie to the pbo and allocate a new buffer.
430 * The pbo gets to keep the data.
431 */
432 void
433 intel_region_release_pbo(struct intel_context *intel,
434 struct intel_region *region)
435 {
436 _DBG("%s %p\n", __FUNCTION__, region);
437 assert(region->buffer == region->pbo->buffer);
438 region->pbo->region = NULL;
439 region->pbo = NULL;
440 dri_bo_unreference(region->buffer);
441 region->buffer = NULL;
442
443 region->buffer = dri_bo_alloc(intel->bufmgr, "region",
444 region->pitch * region->cpp * region->height,
445 64);
446 }
447
448 /* Break the COW tie to the pbo. Both the pbo and the region end up
449 * with a copy of the data.
450 */
451 void
452 intel_region_cow(struct intel_context *intel, struct intel_region *region)
453 {
454 struct intel_buffer_object *pbo = region->pbo;
455
456 intel_region_release_pbo(intel, region);
457
458 assert(region->cpp * region->pitch * region->height == pbo->Base.Size);
459
460 _DBG("%s %p (%d bytes)\n", __FUNCTION__, region, pbo->Base.Size);
461
462 /* Now blit from the texture buffer to the new buffer:
463 */
464
465 LOCK_HARDWARE(intel);
466 assert(intelEmitCopyBlit(intel,
467 region->cpp,
468 region->pitch, pbo->buffer, 0, region->tiling,
469 region->pitch, region->buffer, 0, region->tiling,
470 0, 0, 0, 0,
471 region->pitch, region->height,
472 GL_COPY));
473 UNLOCK_HARDWARE(intel);
474 }
475
476 dri_bo *
477 intel_region_buffer(struct intel_context *intel,
478 struct intel_region *region, GLuint flag)
479 {
480 if (region->pbo) {
481 if (flag == INTEL_WRITE_PART)
482 intel_region_cow(intel, region);
483 else if (flag == INTEL_WRITE_FULL)
484 intel_region_release_pbo(intel, region);
485 }
486
487 return region->buffer;
488 }
489
490 static struct intel_region *
491 intel_recreate_static(struct intel_context *intel,
492 const char *name,
493 struct intel_region *region,
494 intelRegion *region_desc)
495 {
496 intelScreenPrivate *intelScreen = intel->intelScreen;
497 int ret;
498
499 if (region == NULL) {
500 region = calloc(sizeof(*region), 1);
501 region->refcount = 1;
502 _DBG("%s creating new region %p\n", __FUNCTION__, region);
503 }
504 else {
505 _DBG("%s %p\n", __FUNCTION__, region);
506 }
507
508 if (intel->ctx.Visual.rgbBits == 24)
509 region->cpp = 4;
510 else
511 region->cpp = intel->ctx.Visual.rgbBits / 8;
512 region->pitch = intelScreen->pitch;
513 region->width = intelScreen->width;
514 region->height = intelScreen->height;
515
516 if (region->buffer != NULL) {
517 dri_bo_unreference(region->buffer);
518 region->buffer = NULL;
519 }
520
521 if (intel->ttm) {
522 assert(region_desc->bo_handle != -1);
523 region->buffer = intel_bo_gem_create_from_name(intel->bufmgr,
524 name,
525 region_desc->bo_handle);
526
527 ret = dri_bo_get_tiling(region->buffer, &region->tiling,
528 &region->bit_6_swizzle);
529 if (ret != 0) {
530 fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",
531 region_desc->bo_handle, name, strerror(-ret));
532 intel_region_release(&region);
533 return NULL;
534 }
535 } else {
536 if (region->classic_map != NULL) {
537 drmUnmap(region->classic_map,
538 region->pitch * region->cpp * region->height);
539 region->classic_map = NULL;
540 }
541 ret = drmMap(intel->driFd, region_desc->handle,
542 region->pitch * region->cpp * region->height,
543 &region->classic_map);
544 if (ret != 0) {
545 fprintf(stderr, "Failed to drmMap %s buffer\n", name);
546 free(region);
547 return NULL;
548 }
549
550 region->buffer = intel_bo_fake_alloc_static(intel->bufmgr,
551 name,
552 region_desc->offset,
553 region->pitch * region->cpp *
554 region->height,
555 region->classic_map);
556
557 /* The sarea just gives us a boolean for whether it's tiled or not,
558 * instead of which tiling mode it is. Guess.
559 */
560 if (region_desc->tiled) {
561 if (IS_965(intel->intelScreen->deviceID) &&
562 region_desc == &intelScreen->depth)
563 region->tiling = I915_TILING_Y;
564 else
565 region->tiling = I915_TILING_X;
566 } else {
567 region->tiling = I915_TILING_NONE;
568 }
569
570 region->bit_6_swizzle = I915_BIT_6_SWIZZLE_NONE;
571 }
572
573 assert(region->buffer != NULL);
574
575 return region;
576 }
577
578 /**
579 * Create intel_region structs to describe the static front, back, and depth
580 * buffers created by the xserver.
581 *
582 * Although FBO's mean we now no longer use these as render targets in
583 * all circumstances, they won't go away until the back and depth
584 * buffers become private, and the front buffer will remain even then.
585 *
586 * Note that these don't allocate video memory, just describe
587 * allocations alread made by the X server.
588 */
589 void
590 intel_recreate_static_regions(struct intel_context *intel)
591 {
592 intelScreenPrivate *intelScreen = intel->intelScreen;
593
594 intel->front_region =
595 intel_recreate_static(intel, "front",
596 intel->front_region,
597 &intelScreen->front);
598
599 intel->back_region =
600 intel_recreate_static(intel, "back",
601 intel->back_region,
602 &intelScreen->back);
603
604 /* Still assumes front.cpp == depth.cpp. We can kill this when we move to
605 * private buffers.
606 */
607 intel->depth_region =
608 intel_recreate_static(intel, "depth",
609 intel->depth_region,
610 &intelScreen->depth);
611 }