git.libre-soc.org Git - mesa.git/blob - src/mesa/drivers/dri/intel/intel

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2 *

5 *

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14 * The above copyright notice and this permission notice (including the

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19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF

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28 /* Provide additional functionality on top of bufmgr buffers:

29 * - 2d semantics and blit operations

30 * - refcounting of buffers for multiple images in a buffer.

31 * - refcounting of buffer mappings.

32 * - some logic for moving the buffers to the best memory pools for

33 * given operations.

34 *

35 * Most of this is to make it easier to implement the fixed-layout

36 * mipmap tree required by intel hardware in the face of GL's

37 * programming interface where each image can be specifed in random

38 * order and it isn't clear what layout the tree should have until the

39 * last moment.

40 */

42 #include <sys/ioctl.h>

43 #include <errno.h>

45 #include "main/hash.h"

46 #include "intel_context.h"

47 #include "intel_regions.h"

48 #include "intel_blit.h"

49 #include "intel_buffer_objects.h"

50 #include "intel_bufmgr.h"

51 #include "intel_batchbuffer.h"

53 #define FILE_DEBUG_FLAG DEBUG_REGION

55 /* This should be set to the maximum backtrace size desired.

56 * Set it to 0 to disable backtrace debugging.

57 */

58 #define DEBUG_BACKTRACE_SIZE 0

60 #if DEBUG_BACKTRACE_SIZE == 0

61 /* Use the standard debug output */

62 #define _DBG(...) DBG(__VA_ARGS__)

63 #else

64 /* Use backtracing debug output */

65 #define _DBG(...) {debug_backtrace(); DBG(__VA_ARGS__);}

67 /* Backtracing debug support */

68 #include <execinfo.h>

70 static void

71 debug_backtrace(void)

72 {

73 void *trace[DEBUG_BACKTRACE_SIZE];

74 char **strings = NULL;

75 int traceSize;

76 register int i;

    traceSize = backtrace(trace, DEBUG_BACKTRACE_SIZE);

    strings = backtrace_symbols(trace, traceSize);

80 if (strings == NULL) {

81 DBG("no backtrace:");

82 return;

83 }

85 /* Spit out all the strings with a colon separator. Ignore

86 * the first, since we don't really care about the call

87 * to debug_backtrace() itself. Skip until the final "/" in

88 * the trace to avoid really long lines.

89 */

    for (i = 1; i < traceSize; i++) {

       char *p = strings[i], *slash = strings[i];

92 while (*p) {

          if (*p++ == '/') {

94 slash = p;

95 }

96 }

       DBG("%s:", slash);

99 }

100

101 /* Free up the memory, and we're done */

102 free(strings);

103 }

105 #endif

109 /* XXX: Thread safety?

110 */

111 void *

 intel_region_map(struct intel_context *intel, struct intel_region *region,

113 GLbitfield mode)

114 {

115 /* We have the region->map_refcount controlling mapping of the BO because

116 * in software fallbacks we may end up mapping the same buffer multiple

117 * times on Mesa's behalf, so we refcount our mappings to make sure that

118 * the pointer stays valid until the end of the unmap chain. However, we

119 * must not emit any batchbuffers between the start of mapping and the end

120 * of unmapping, or further use of the map will be incoherent with the GPU

121 * rendering done by that batchbuffer. Hence we assert in

122 * intel_batchbuffer_flush() that that doesn't happen, which means that the

123 * flush is only needed on first map of the buffer.

124 */

125

    _DBG("%s %p\n", __FUNCTION__, region);

127 if (!region->map_refcount) {

128 intel_flush(&intel->ctx);

129

       if (region->tiling != I915_TILING_NONE)

131 drm_intel_gem_bo_map_gtt(region->bo);

132 else

          drm_intel_bo_map(region->bo, true);

134

       region->map = region->bo->virtual;

136 }

137 if (region->map) {

138 intel->num_mapped_regions++;

139 region->map_refcount++;

140 }

141

142 return region->map;

143 }

144

145 void

 intel_region_unmap(struct intel_context *intel, struct intel_region *region)

147 {

    _DBG("%s %p\n", __FUNCTION__, region);

149 if (!--region->map_refcount) {

       if (region->tiling != I915_TILING_NONE)

151 drm_intel_gem_bo_unmap_gtt(region->bo);

152 else

153 drm_intel_bo_unmap(region->bo);

154

155 region->map = NULL;

156 --intel->num_mapped_regions;

       assert(intel->num_mapped_regions >= 0);

158 }

159 }

160

161 static struct intel_region *

 intel_region_alloc_internal(struct intel_screen *screen,

163 GLuint cpp,

164 GLuint width, GLuint height, GLuint pitch,

165 uint32_t tiling, drm_intel_bo *buffer)

166 {

167 struct intel_region *region;

168

    region = calloc(sizeof(*region), 1);

170 if (region == NULL)

171 return region;

172

173 region->cpp = cpp;

174 region->width = width;

175 region->height = height;

176 region->pitch = pitch;

177 region->refcount = 1;

178 region->bo = buffer;

179 region->tiling = tiling;

180 region->screen = screen;

181

    _DBG("%s <-- %p\n", __FUNCTION__, region);

183 return region;

184 }

185

186 struct intel_region *

 intel_region_alloc(struct intel_screen *screen,

188 uint32_t tiling,

189 GLuint cpp, GLuint width, GLuint height,

190 bool expect_accelerated_upload)

191 {

192 drm_intel_bo *buffer;

193 unsigned long flags = 0;

194 unsigned long aligned_pitch;

195 struct intel_region *region;

196

197 if (expect_accelerated_upload)

198 flags |= BO_ALLOC_FOR_RENDER;

199

    buffer = drm_intel_bo_alloc_tiled(screen->bufmgr, "region",

201 width, height, cpp,

202 &tiling, &aligned_pitch, flags);

203 if (buffer == NULL)

204 return NULL;

205

    region = intel_region_alloc_internal(screen, cpp, width, height,

207 aligned_pitch / cpp, tiling, buffer);

208 if (region == NULL) {

209 drm_intel_bo_unreference(buffer);

210 return NULL;

211 }

212

213 return region;

214 }

215

216 bool

 intel_region_flink(struct intel_region *region, uint32_t *name)

218 {

    if (region->name == 0) {

       if (drm_intel_bo_flink(region->bo, &region->name))

221 return false;

222

       _mesa_HashInsert(region->screen->named_regions,

224 region->name, region);

225 }

226

227 *name = region->name;

228

229 return true;

230 }

231

232 struct intel_region *

 intel_region_alloc_for_handle(struct intel_screen *screen,

234 GLuint cpp,

235 GLuint width, GLuint height, GLuint pitch,

236 GLuint handle, const char *name)

237 {

238 struct intel_region *region, *dummy;

239 drm_intel_bo *buffer;

240 int ret;

241 uint32_t bit_6_swizzle, tiling;

242

    region = _mesa_HashLookup(screen->named_regions, handle);

244 if (region != NULL) {

245 dummy = NULL;

       if (region->width != width || region->height != height ||

           region->cpp != cpp || region->pitch != pitch) {

248 fprintf(stderr,

249 "Region for name %d already exists but is not compatible\n",

250 handle);

251 return NULL;

252 }

253 intel_region_reference(&dummy, region);

254 return dummy;

255 }

256

    buffer = intel_bo_gem_create_from_name(screen->bufmgr, name, handle);

258 if (buffer == NULL)

259 return NULL;

    ret = drm_intel_bo_get_tiling(buffer, &tiling, &bit_6_swizzle);

    if (ret != 0) {

       fprintf(stderr, "Couldn't get tiling of buffer %d (%s): %s\n",

               handle, name, strerror(-ret));

264 drm_intel_bo_unreference(buffer);

265 return NULL;

266 }

267

    region = intel_region_alloc_internal(screen, cpp,

                                         width, height, pitch, tiling, buffer);

270 if (region == NULL) {

271 drm_intel_bo_unreference(buffer);

272 return NULL;

273 }

274

275 region->name = handle;

    _mesa_HashInsert(screen->named_regions, handle, region);

277

278 return region;

279 }

280

281 void

 intel_region_reference(struct intel_region **dst, struct intel_region *src)

283 {

    _DBG("%s: %p(%d) -> %p(%d)\n", __FUNCTION__,

         *dst, *dst ? (*dst)->refcount : 0, src, src ? src->refcount : 0);

286

287 if (src != *dst) {

288 if (*dst)

289 intel_region_release(dst);

290

291 if (src)

292 src->refcount++;

293 *dst = src;

294 }

295 }

296

297 void

 intel_region_release(struct intel_region **region_handle)

299 {

300 struct intel_region *region = *region_handle;

301

302 if (region == NULL) {

       _DBG("%s NULL\n", __FUNCTION__);

304 return;

305 }

306

    _DBG("%s %p %d\n", __FUNCTION__, region, region->refcount - 1);

308

    ASSERT(region->refcount > 0);

310 region->refcount--;

311

    if (region->refcount == 0) {

       assert(region->map_refcount == 0);

314

315 drm_intel_bo_unreference(region->bo);

316

       if (region->name > 0)

          _mesa_HashRemove(region->screen->named_regions, region->name);

319

320 free(region);

321 }

322 *region_handle = NULL;

323 }

324

325 /*

326 * XXX Move this into core Mesa?

327 */

328 void

329 _mesa_copy_rect(GLubyte * dst,

330 GLuint cpp,

331 GLuint dst_pitch,

332 GLuint dst_x,

333 GLuint dst_y,

334 GLuint width,

335 GLuint height,

336 const GLubyte * src,

337 GLuint src_pitch, GLuint src_x, GLuint src_y)

338 {

339 GLuint i;

340

341 dst_pitch *= cpp;

342 src_pitch *= cpp;

343 dst += dst_x * cpp;

344 src += src_x * cpp;

345 dst += dst_y * dst_pitch;

346 src += src_y * src_pitch;

347 width *= cpp;

348

    if (width == dst_pitch && width == src_pitch)

       memcpy(dst, src, height * width);

351 else {

       for (i = 0; i < height; i++) {

          memcpy(dst, src, width);

354 dst += dst_pitch;

355 src += src_pitch;

356 }

357 }

358 }

359

360 /* Copy rectangular sub-regions. Need better logic about when to

361 * push buffers into AGP - will currently do so whenever possible.

362 */

363 bool

 intel_region_copy(struct intel_context *intel,

365 struct intel_region *dst,

366 GLuint dst_offset,

367 GLuint dstx, GLuint dsty,

368 struct intel_region *src,

369 GLuint src_offset,

370 GLuint srcx, GLuint srcy, GLuint width, GLuint height,

371 bool flip,

372 GLenum logicop)

373 {

374 uint32_t src_pitch = src->pitch;

375

    _DBG("%s\n", __FUNCTION__);

377

378 if (intel == NULL)

379 return false;

380

    assert(src->cpp == dst->cpp);

382

383 if (flip)

384 src_pitch = -src_pitch;

385

386 return intelEmitCopyBlit(intel,

387 dst->cpp,

                             src_pitch, src->bo, src_offset, src->tiling,

                             dst->pitch, dst->bo, dst_offset, dst->tiling,

                             srcx, srcy, dstx, dsty, width, height,

391 logicop);

392 }

393

394 /**

395 * This function computes masks that may be used to select the bits of the X

396 * and Y coordinates that indicate the offset within a tile. If the region is

397 * untiled, the masks are set to 0.

398 */

399 void

 intel_region_get_tile_masks(struct intel_region *region,

                             uint32_t *mask_x, uint32_t *mask_y)

402 {

403 int cpp = region->cpp;

404

405 switch (region->tiling) {

406 default:

407 assert(false);

408 case I915_TILING_NONE:

       *mask_x = *mask_y = 0;

410 break;

411 case I915_TILING_X:

       *mask_x = 512 / cpp - 1;

413 *mask_y = 7;

414 break;

415 case I915_TILING_Y:

       *mask_x = 128 / cpp - 1;

417 *mask_y = 31;

418 break;

419 }

420 }

421

422 /**

423 * Compute the offset (in bytes) from the start of the region to the given x

424 * and y coordinate. For tiled regions, caller must ensure that x and y are

425 * multiples of the tile size.

426 */

427 uint32_t

 intel_region_get_aligned_offset(struct intel_region *region, uint32_t x,

429 uint32_t y)

430 {

431 int cpp = region->cpp;

    uint32_t pitch = region->pitch * cpp;

433

434 switch (region->tiling) {

435 default:

436 assert(false);

437 case I915_TILING_NONE:

       return y * pitch + x * cpp;

439 case I915_TILING_X:

       assert((x % (512 / cpp)) == 0);

       assert((y % 8) == 0);

       return y * pitch + x / (512 / cpp) * 4096;

443 case I915_TILING_Y:

       assert((x % (128 / cpp)) == 0);

       assert((y % 32) == 0);

       return y * pitch + x / (128 / cpp) * 4096;

447 }

448 }