1 /**************************************************************************
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
28 #include "main/glheader.h"
29 #include "main/macros.h"
30 #include "main/mtypes.h"
31 #include "main/colormac.h"
33 #include "intel_buffers.h"
34 #include "intel_fbo.h"
35 #include "intel_screen.h"
36 #include "intel_span.h"
37 #include "intel_regions.h"
38 #include "intel_tex.h"
40 #include "swrast/swrast.h"
43 intel_set_span_functions(struct intel_context
*intel
,
44 struct gl_renderbuffer
*rb
);
46 #define SPAN_CACHE_SIZE 4096
49 get_span_cache(struct intel_renderbuffer
*irb
, uint32_t offset
)
51 if (irb
->span_cache
== NULL
) {
52 irb
->span_cache
= _mesa_malloc(SPAN_CACHE_SIZE
);
53 irb
->span_cache_offset
= -1;
56 if ((offset
& ~(SPAN_CACHE_SIZE
- 1)) != irb
->span_cache_offset
) {
57 irb
->span_cache_offset
= offset
& ~(SPAN_CACHE_SIZE
- 1);
58 dri_bo_get_subdata(irb
->region
->buffer
, irb
->span_cache_offset
,
59 SPAN_CACHE_SIZE
, irb
->span_cache
);
64 clear_span_cache(struct intel_renderbuffer
*irb
)
66 irb
->span_cache_offset
= -1;
70 pread_32(struct intel_renderbuffer
*irb
, uint32_t offset
)
72 get_span_cache(irb
, offset
);
74 return *(uint32_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1)));
78 pread_xrgb8888(struct intel_renderbuffer
*irb
, uint32_t offset
)
80 get_span_cache(irb
, offset
);
82 return *(uint32_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1))) |
87 pread_16(struct intel_renderbuffer
*irb
, uint32_t offset
)
89 get_span_cache(irb
, offset
);
91 return *(uint16_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1)));
95 pread_8(struct intel_renderbuffer
*irb
, uint32_t offset
)
97 get_span_cache(irb
, offset
);
99 return *(uint8_t *)(irb
->span_cache
+ (offset
& (SPAN_CACHE_SIZE
- 1)));
103 pwrite_32(struct intel_renderbuffer
*irb
, uint32_t offset
, uint32_t val
)
105 clear_span_cache(irb
);
107 dri_bo_subdata(irb
->region
->buffer
, offset
, 4, &val
);
111 pwrite_xrgb8888(struct intel_renderbuffer
*irb
, uint32_t offset
, uint32_t val
)
113 clear_span_cache(irb
);
115 dri_bo_subdata(irb
->region
->buffer
, offset
, 3, &val
);
119 pwrite_16(struct intel_renderbuffer
*irb
, uint32_t offset
, uint16_t val
)
121 clear_span_cache(irb
);
123 dri_bo_subdata(irb
->region
->buffer
, offset
, 2, &val
);
127 pwrite_8(struct intel_renderbuffer
*irb
, uint32_t offset
, uint8_t val
)
129 clear_span_cache(irb
);
131 dri_bo_subdata(irb
->region
->buffer
, offset
, 1, &val
);
135 z24s8_to_s8z24(uint32_t val
)
137 return (val
<< 24) | (val
>> 8);
141 s8z24_to_z24s8(uint32_t val
)
143 return (val
>> 24) | (val
<< 8);
146 static uint32_t no_tile_swizzle(struct intel_renderbuffer
*irb
,
149 return (y
* irb
->region
->pitch
+ x
) * irb
->region
->cpp
;
153 * Deal with tiled surfaces
156 static uint32_t x_tile_swizzle(struct intel_renderbuffer
*irb
,
161 int x_tile_off
, y_tile_off
;
162 int x_tile_number
, y_tile_number
;
163 int tile_off
, tile_base
;
165 tile_stride
= (irb
->region
->pitch
* irb
->region
->cpp
) << 3;
167 xbyte
= x
* irb
->region
->cpp
;
169 x_tile_off
= xbyte
& 0x1ff;
172 x_tile_number
= xbyte
>> 9;
173 y_tile_number
= y
>> 3;
175 tile_off
= (y_tile_off
<< 9) + x_tile_off
;
177 switch (irb
->region
->bit_6_swizzle
) {
178 case I915_BIT_6_SWIZZLE_NONE
:
180 case I915_BIT_6_SWIZZLE_9
:
181 tile_off
^= ((tile_off
>> 3) & 64);
183 case I915_BIT_6_SWIZZLE_9_10
:
184 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64);
186 case I915_BIT_6_SWIZZLE_9_11
:
187 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 5) & 64);
189 case I915_BIT_6_SWIZZLE_9_10_11
:
190 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64) ^
191 ((tile_off
>> 5) & 64);
194 fprintf(stderr
, "Unknown tile swizzling mode %d\n",
195 irb
->region
->bit_6_swizzle
);
199 tile_base
= (x_tile_number
<< 12) + y_tile_number
* tile_stride
;
202 printf("(%d,%d) -> %d + %d = %d (pitch = %d, tstride = %d)\n",
203 x
, y
, tile_off
, tile_base
,
204 tile_off
+ tile_base
,
205 irb
->region
->pitch
, tile_stride
);
208 return tile_base
+ tile_off
;
211 static uint32_t y_tile_swizzle(struct intel_renderbuffer
*irb
,
216 int x_tile_off
, y_tile_off
;
217 int x_tile_number
, y_tile_number
;
218 int tile_off
, tile_base
;
220 tile_stride
= (irb
->region
->pitch
* irb
->region
->cpp
) << 5;
222 xbyte
= x
* irb
->region
->cpp
;
224 x_tile_off
= xbyte
& 0x7f;
225 y_tile_off
= y
& 0x1f;
227 x_tile_number
= xbyte
>> 7;
228 y_tile_number
= y
>> 5;
230 tile_off
= ((x_tile_off
& ~0xf) << 5) + (y_tile_off
<< 4) +
233 switch (irb
->region
->bit_6_swizzle
) {
234 case I915_BIT_6_SWIZZLE_NONE
:
236 case I915_BIT_6_SWIZZLE_9
:
237 tile_off
^= ((tile_off
>> 3) & 64);
239 case I915_BIT_6_SWIZZLE_9_10
:
240 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64);
242 case I915_BIT_6_SWIZZLE_9_11
:
243 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 5) & 64);
245 case I915_BIT_6_SWIZZLE_9_10_11
:
246 tile_off
^= ((tile_off
>> 3) & 64) ^ ((tile_off
>> 4) & 64) ^
247 ((tile_off
>> 5) & 64);
250 fprintf(stderr
, "Unknown tile swizzling mode %d\n",
251 irb
->region
->bit_6_swizzle
);
255 tile_base
= (x_tile_number
<< 12) + y_tile_number
* tile_stride
;
257 return tile_base
+ tile_off
;
261 break intelWriteRGBASpan_ARGB8888
268 struct intel_context *intel = intel_context(ctx); \
269 struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
270 const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \
271 const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
272 unsigned int num_cliprects; \
273 struct drm_clip_rect *cliprects; \
277 intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
279 /* XXX FBO: this is identical to the macro in spantmp2.h except we get
280 * the cliprect info from the context, not the driDrawable.
281 * Move this into spantmp2.h someday.
283 #define HW_CLIPLOOP() \
285 int _nc = num_cliprects; \
287 int minx = cliprects[_nc].x1 - x_off; \
288 int miny = cliprects[_nc].y1 - y_off; \
289 int maxx = cliprects[_nc].x2 - x_off; \
290 int maxy = cliprects[_nc].y2 - y_off;
296 #define Y_FLIP(_y) ((_y) * yScale + yBias)
298 /* XXX with GEM, these need to tell the kernel */
303 /* Convenience macros to avoid typing the swizzle argument over and over */
304 #define NO_TILE(_X, _Y) no_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
305 #define X_TILE(_X, _Y) x_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
306 #define Y_TILE(_X, _Y) y_tile_swizzle(irb, (_X) + x_off, (_Y) + y_off)
308 /* r5g6b5 color span and pixel functions */
309 #define INTEL_PIXEL_FMT GL_RGB
310 #define INTEL_PIXEL_TYPE GL_UNSIGNED_SHORT_5_6_5
311 #define INTEL_READ_VALUE(offset) pread_16(irb, offset)
312 #define INTEL_WRITE_VALUE(offset, v) pwrite_16(irb, offset, v)
313 #define INTEL_TAG(x) x##_RGB565
314 #include "intel_spantmp.h"
316 /* a8r8g8b8 color span and pixel functions */
317 #define INTEL_PIXEL_FMT GL_BGRA
318 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
319 #define INTEL_READ_VALUE(offset) pread_32(irb, offset)
320 #define INTEL_WRITE_VALUE(offset, v) pwrite_32(irb, offset, v)
321 #define INTEL_TAG(x) x##_ARGB8888
322 #include "intel_spantmp.h"
324 /* x8r8g8b8 color span and pixel functions */
325 #define INTEL_PIXEL_FMT GL_BGRA
326 #define INTEL_PIXEL_TYPE GL_UNSIGNED_INT_8_8_8_8_REV
327 #define INTEL_READ_VALUE(offset) pread_xrgb8888(irb, offset)
328 #define INTEL_WRITE_VALUE(offset, v) pwrite_xrgb8888(irb, offset, v)
329 #define INTEL_TAG(x) x##_xRGB8888
330 #include "intel_spantmp.h"
332 #define LOCAL_DEPTH_VARS \
333 struct intel_context *intel = intel_context(ctx); \
334 struct intel_renderbuffer *irb = intel_renderbuffer(rb); \
335 const GLint yScale = ctx->DrawBuffer->Name ? 1 : -1; \
336 const GLint yBias = ctx->DrawBuffer->Name ? 0 : irb->Base.Height - 1;\
337 unsigned int num_cliprects; \
338 struct drm_clip_rect *cliprects; \
340 intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off);
343 #define LOCAL_STENCIL_VARS LOCAL_DEPTH_VARS
345 /* z16 depthbuffer functions. */
346 #define INTEL_VALUE_TYPE GLushort
347 #define INTEL_WRITE_DEPTH(offset, d) pwrite_16(irb, offset, d)
348 #define INTEL_READ_DEPTH(offset) pread_16(irb, offset)
349 #define INTEL_TAG(name) name##_z16
350 #include "intel_depthtmp.h"
352 /* z24 depthbuffer functions. */
353 #define INTEL_VALUE_TYPE GLuint
354 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, d)
355 #define INTEL_READ_DEPTH(offset) pread_32(irb, offset)
356 #define INTEL_TAG(name) name##_z24
357 #include "intel_depthtmp.h"
359 /* z24s8 depthbuffer functions. */
360 #define INTEL_VALUE_TYPE GLuint
361 #define INTEL_WRITE_DEPTH(offset, d) pwrite_32(irb, offset, z24s8_to_s8z24(d))
362 #define INTEL_READ_DEPTH(offset) s8z24_to_z24s8(pread_32(irb, offset))
363 #define INTEL_TAG(name) name##_z24_s8
364 #include "intel_depthtmp.h"
368 ** 8-bit stencil function (XXX FBO: This is obsolete)
370 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, NO_TILE(_x, _y) + 3, d)
371 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, NO_TILE(_x, _y) + 3);
372 #define TAG(x) intel##x##_z24_s8
373 #include "stenciltmp.h"
376 ** 8-bit x-tile stencil function (XXX FBO: This is obsolete)
378 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, X_TILE(_x, _y) + 3, d)
379 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, X_TILE(_x, _y) + 3);
380 #define TAG(x) intel_XTile_##x##_z24_s8
381 #include "stenciltmp.h"
384 ** 8-bit y-tile stencil function (XXX FBO: This is obsolete)
386 #define WRITE_STENCIL(_x, _y, d) pwrite_8(irb, Y_TILE(_x, _y) + 3, d)
387 #define READ_STENCIL(d, _x, _y) d = pread_8(irb, Y_TILE(_x, _y) + 3)
388 #define TAG(x) intel_YTile_##x##_z24_s8
389 #include "stenciltmp.h"
392 intel_renderbuffer_map(struct intel_context
*intel
, struct gl_renderbuffer
*rb
)
394 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
396 if (irb
== NULL
|| irb
->region
== NULL
)
399 intel_set_span_functions(intel
, rb
);
403 intel_renderbuffer_unmap(struct intel_context
*intel
,
404 struct gl_renderbuffer
*rb
)
406 struct intel_renderbuffer
*irb
= intel_renderbuffer(rb
);
408 if (irb
== NULL
|| irb
->region
== NULL
)
411 clear_span_cache(irb
);
418 * Map or unmap all the renderbuffers which we may need during
419 * software rendering.
420 * XXX in the future, we could probably convey extra information to
421 * reduce the number of mappings needed. I.e. if doing a glReadPixels
422 * from the depth buffer, we really only need one mapping.
424 * XXX Rewrite this function someday.
425 * We can probably just loop over all the renderbuffer attachments,
426 * map/unmap all of them, and not worry about the _ColorDrawBuffers
427 * _ColorReadBuffer, _DepthBuffer or _StencilBuffer fields.
430 intel_map_unmap_buffers(struct intel_context
*intel
, GLboolean map
)
432 GLcontext
*ctx
= &intel
->ctx
;
435 /* color draw buffers */
436 for (j
= 0; j
< ctx
->DrawBuffer
->_NumColorDrawBuffers
; j
++) {
438 intel_renderbuffer_map(intel
, ctx
->DrawBuffer
->_ColorDrawBuffers
[j
]);
440 intel_renderbuffer_unmap(intel
, ctx
->DrawBuffer
->_ColorDrawBuffers
[j
]);
443 /* check for render to textures */
444 for (i
= 0; i
< BUFFER_COUNT
; i
++) {
445 struct gl_renderbuffer_attachment
*att
=
446 ctx
->DrawBuffer
->Attachment
+ i
;
447 struct gl_texture_object
*tex
= att
->Texture
;
449 /* render to texture */
450 ASSERT(att
->Renderbuffer
);
452 intel_tex_map_images(intel
, intel_texture_object(tex
));
454 intel_tex_unmap_images(intel
, intel_texture_object(tex
));
458 /* color read buffers */
460 intel_renderbuffer_map(intel
, ctx
->ReadBuffer
->_ColorReadBuffer
);
462 intel_renderbuffer_unmap(intel
, ctx
->ReadBuffer
->_ColorReadBuffer
);
464 /* depth buffer (Note wrapper!) */
465 if (ctx
->DrawBuffer
->_DepthBuffer
) {
467 intel_renderbuffer_map(intel
, ctx
->DrawBuffer
->_DepthBuffer
->Wrapped
);
469 intel_renderbuffer_unmap(intel
,
470 ctx
->DrawBuffer
->_DepthBuffer
->Wrapped
);
473 /* stencil buffer (Note wrapper!) */
474 if (ctx
->DrawBuffer
->_StencilBuffer
) {
476 intel_renderbuffer_map(intel
,
477 ctx
->DrawBuffer
->_StencilBuffer
->Wrapped
);
479 intel_renderbuffer_unmap(intel
,
480 ctx
->DrawBuffer
->_StencilBuffer
->Wrapped
);
487 * Prepare for softare rendering. Map current read/draw framebuffers'
488 * renderbuffes and all currently bound texture objects.
490 * Old note: Moved locking out to get reasonable span performance.
493 intelSpanRenderStart(GLcontext
* ctx
)
495 struct intel_context
*intel
= intel_context(ctx
);
498 intelFlush(&intel
->ctx
);
499 LOCK_HARDWARE(intel
);
501 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
502 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
503 struct gl_texture_object
*texObj
= ctx
->Texture
.Unit
[i
]._Current
;
504 intel_tex_map_images(intel
, intel_texture_object(texObj
));
508 intel_map_unmap_buffers(intel
, GL_TRUE
);
512 * Called when done softare rendering. Unmap the buffers we mapped in
513 * the above function.
516 intelSpanRenderFinish(GLcontext
* ctx
)
518 struct intel_context
*intel
= intel_context(ctx
);
523 for (i
= 0; i
< ctx
->Const
.MaxTextureImageUnits
; i
++) {
524 if (ctx
->Texture
.Unit
[i
]._ReallyEnabled
) {
525 struct gl_texture_object
*texObj
= ctx
->Texture
.Unit
[i
]._Current
;
526 intel_tex_unmap_images(intel
, intel_texture_object(texObj
));
530 intel_map_unmap_buffers(intel
, GL_FALSE
);
532 UNLOCK_HARDWARE(intel
);
537 intelInitSpanFuncs(GLcontext
* ctx
)
539 struct swrast_device_driver
*swdd
= _swrast_GetDeviceDriverReference(ctx
);
540 swdd
->SpanRenderStart
= intelSpanRenderStart
;
541 swdd
->SpanRenderFinish
= intelSpanRenderFinish
;
546 * Plug in appropriate span read/write functions for the given renderbuffer.
547 * These are used for the software fallbacks.
550 intel_set_span_functions(struct intel_context
*intel
,
551 struct gl_renderbuffer
*rb
)
553 struct intel_renderbuffer
*irb
= (struct intel_renderbuffer
*) rb
;
556 /* If in GEM mode, we need to do the tile address swizzling ourselves,
557 * instead of the fence registers handling it.
560 tiling
= irb
->region
->tiling
;
562 tiling
= I915_TILING_NONE
;
564 if (rb
->_ActualFormat
== GL_RGB5
) {
567 case I915_TILING_NONE
:
569 intelInitPointers_RGB565(rb
);
572 intel_XTile_InitPointers_RGB565(rb
);
575 intel_YTile_InitPointers_RGB565(rb
);
579 else if (rb
->_ActualFormat
== GL_RGB8
) {
582 case I915_TILING_NONE
:
584 intelInitPointers_xRGB8888(rb
);
587 intel_XTile_InitPointers_xRGB8888(rb
);
590 intel_YTile_InitPointers_xRGB8888(rb
);
594 else if (rb
->_ActualFormat
== GL_RGBA8
) {
597 case I915_TILING_NONE
:
599 intelInitPointers_ARGB8888(rb
);
602 intel_XTile_InitPointers_ARGB8888(rb
);
605 intel_YTile_InitPointers_ARGB8888(rb
);
609 else if (rb
->_ActualFormat
== GL_DEPTH_COMPONENT16
) {
611 case I915_TILING_NONE
:
613 intelInitDepthPointers_z16(rb
);
616 intel_XTile_InitDepthPointers_z16(rb
);
619 intel_YTile_InitDepthPointers_z16(rb
);
623 else if (rb
->_ActualFormat
== GL_DEPTH_COMPONENT24
) {
625 case I915_TILING_NONE
:
627 intelInitDepthPointers_z24(rb
);
630 intel_XTile_InitDepthPointers_z24(rb
);
633 intel_YTile_InitDepthPointers_z24(rb
);
637 else if (rb
->_ActualFormat
== GL_DEPTH24_STENCIL8_EXT
) {
639 case I915_TILING_NONE
:
641 intelInitDepthPointers_z24_s8(rb
);
644 intel_XTile_InitDepthPointers_z24_s8(rb
);
647 intel_YTile_InitDepthPointers_z24_s8(rb
);
651 else if (rb
->_ActualFormat
== GL_STENCIL_INDEX8_EXT
) {
653 case I915_TILING_NONE
:
655 intelInitStencilPointers_z24_s8(rb
);
658 intel_XTile_InitStencilPointers_z24_s8(rb
);
661 intel_YTile_InitStencilPointers_z24_s8(rb
);
667 "Unexpected _ActualFormat in intelSetSpanFunctions");