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mesa: remove a bunch of gl_renderbuffer fields
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_common_context.c
1 /**************************************************************************
2
3 Copyright 2000, 2001 ATI Technologies Inc., Ontario, Canada, and
4 VA Linux Systems Inc., Fremont, California.
5 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
6
7 The Weather Channel (TM) funded Tungsten Graphics to develop the
8 initial release of the Radeon 8500 driver under the XFree86 license.
9 This notice must be preserved.
10
11 All Rights Reserved.
12
13 Permission is hereby granted, free of charge, to any person obtaining
14 a copy of this software and associated documentation files (the
15 "Software"), to deal in the Software without restriction, including
16 without limitation the rights to use, copy, modify, merge, publish,
17 distribute, sublicense, and/or sell copies of the Software, and to
18 permit persons to whom the Software is furnished to do so, subject to
19 the following conditions:
20
21 The above copyright notice and this permission notice (including the
22 next paragraph) shall be included in all copies or substantial
23 portions of the Software.
24
25 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
28 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
29 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
30 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
31 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32
33 **************************************************************************/
34
35 #include "radeon_common.h"
36 #include "xmlpool.h" /* for symbolic values of enum-type options */
37 #include "utils.h"
38 #include "vblank.h"
39 #include "drirenderbuffer.h"
40 #include "drivers/common/meta.h"
41 #include "main/context.h"
42 #include "main/framebuffer.h"
43 #include "main/renderbuffer.h"
44 #include "main/state.h"
45 #include "main/simple_list.h"
46 #include "swrast/swrast.h"
47 #include "swrast_setup/swrast_setup.h"
48 #include "tnl/tnl.h"
49
50 #if defined(RADEON_R600)
51 #include "r600_context.h"
52 #endif
53
54 #define DRIVER_DATE "20090101"
55
56 #ifndef RADEON_DEBUG
57 int RADEON_DEBUG = (0);
58 #endif
59
60
61 static const char* get_chip_family_name(int chip_family)
62 {
63 switch(chip_family) {
64 case CHIP_FAMILY_R100: return "R100";
65 case CHIP_FAMILY_RV100: return "RV100";
66 case CHIP_FAMILY_RS100: return "RS100";
67 case CHIP_FAMILY_RV200: return "RV200";
68 case CHIP_FAMILY_RS200: return "RS200";
69 case CHIP_FAMILY_R200: return "R200";
70 case CHIP_FAMILY_RV250: return "RV250";
71 case CHIP_FAMILY_RS300: return "RS300";
72 case CHIP_FAMILY_RV280: return "RV280";
73 case CHIP_FAMILY_R300: return "R300";
74 case CHIP_FAMILY_R350: return "R350";
75 case CHIP_FAMILY_RV350: return "RV350";
76 case CHIP_FAMILY_RV380: return "RV380";
77 case CHIP_FAMILY_R420: return "R420";
78 case CHIP_FAMILY_RV410: return "RV410";
79 case CHIP_FAMILY_RS400: return "RS400";
80 case CHIP_FAMILY_RS600: return "RS600";
81 case CHIP_FAMILY_RS690: return "RS690";
82 case CHIP_FAMILY_RS740: return "RS740";
83 case CHIP_FAMILY_RV515: return "RV515";
84 case CHIP_FAMILY_R520: return "R520";
85 case CHIP_FAMILY_RV530: return "RV530";
86 case CHIP_FAMILY_R580: return "R580";
87 case CHIP_FAMILY_RV560: return "RV560";
88 case CHIP_FAMILY_RV570: return "RV570";
89 case CHIP_FAMILY_R600: return "R600";
90 case CHIP_FAMILY_RV610: return "RV610";
91 case CHIP_FAMILY_RV630: return "RV630";
92 case CHIP_FAMILY_RV670: return "RV670";
93 case CHIP_FAMILY_RV620: return "RV620";
94 case CHIP_FAMILY_RV635: return "RV635";
95 case CHIP_FAMILY_RS780: return "RS780";
96 case CHIP_FAMILY_RS880: return "RS880";
97 case CHIP_FAMILY_RV770: return "RV770";
98 case CHIP_FAMILY_RV730: return "RV730";
99 case CHIP_FAMILY_RV710: return "RV710";
100 case CHIP_FAMILY_RV740: return "RV740";
101 default: return "unknown";
102 }
103 }
104
105
106 /* Return various strings for glGetString().
107 */
108 static const GLubyte *radeonGetString(GLcontext * ctx, GLenum name)
109 {
110 radeonContextPtr radeon = RADEON_CONTEXT(ctx);
111 static char buffer[128];
112
113 switch (name) {
114 case GL_VENDOR:
115 if (IS_R600_CLASS(radeon->radeonScreen))
116 return (GLubyte *) "Advanced Micro Devices, Inc.";
117 else if (IS_R300_CLASS(radeon->radeonScreen))
118 return (GLubyte *) "DRI R300 Project";
119 else
120 return (GLubyte *) "Tungsten Graphics, Inc.";
121
122 case GL_RENDERER:
123 {
124 unsigned offset;
125 GLuint agp_mode = (radeon->radeonScreen->card_type==RADEON_CARD_PCI) ? 0 :
126 radeon->radeonScreen->AGPMode;
127 const char* chipclass;
128 char hardwarename[32];
129
130 if (IS_R600_CLASS(radeon->radeonScreen))
131 chipclass = "R600";
132 else if (IS_R300_CLASS(radeon->radeonScreen))
133 chipclass = "R300";
134 else if (IS_R200_CLASS(radeon->radeonScreen))
135 chipclass = "R200";
136 else
137 chipclass = "R100";
138
139 sprintf(hardwarename, "%s (%s %04X)",
140 chipclass,
141 get_chip_family_name(radeon->radeonScreen->chip_family),
142 radeon->radeonScreen->device_id);
143
144 offset = driGetRendererString(buffer, hardwarename, DRIVER_DATE,
145 agp_mode);
146
147 if (IS_R600_CLASS(radeon->radeonScreen)) {
148 sprintf(&buffer[offset], " TCL");
149 } else if (IS_R300_CLASS(radeon->radeonScreen)) {
150 sprintf(&buffer[offset], " %sTCL",
151 (radeon->radeonScreen->chip_flags & RADEON_CHIPSET_TCL)
152 ? "" : "NO-");
153 } else {
154 sprintf(&buffer[offset], " %sTCL",
155 !(radeon->TclFallback & RADEON_TCL_FALLBACK_TCL_DISABLE)
156 ? "" : "NO-");
157 }
158
159 if (radeon->radeonScreen->driScreen->dri2.enabled)
160 strcat(buffer, " DRI2");
161
162 return (GLubyte *) buffer;
163 }
164
165 default:
166 return NULL;
167 }
168 }
169
170 /* Initialize the driver's misc functions.
171 */
172 static void radeonInitDriverFuncs(struct dd_function_table *functions)
173 {
174 functions->GetString = radeonGetString;
175 }
176
177 /**
178 * Create and initialize all common fields of the context,
179 * including the Mesa context itself.
180 */
181 GLboolean radeonInitContext(radeonContextPtr radeon,
182 struct dd_function_table* functions,
183 const __GLcontextModes * glVisual,
184 __DRIcontextPrivate * driContextPriv,
185 void *sharedContextPrivate)
186 {
187 __DRIscreenPrivate *sPriv = driContextPriv->driScreenPriv;
188 radeonScreenPtr screen = (radeonScreenPtr) (sPriv->private);
189 GLcontext* ctx;
190 GLcontext* shareCtx;
191 int fthrottle_mode;
192
193 /* Fill in additional standard functions. */
194 radeonInitDriverFuncs(functions);
195
196 radeon->radeonScreen = screen;
197 /* Allocate and initialize the Mesa context */
198 if (sharedContextPrivate)
199 shareCtx = ((radeonContextPtr)sharedContextPrivate)->glCtx;
200 else
201 shareCtx = NULL;
202 radeon->glCtx = _mesa_create_context(glVisual, shareCtx,
203 functions, (void *)radeon);
204 if (!radeon->glCtx)
205 return GL_FALSE;
206
207 ctx = radeon->glCtx;
208 driContextPriv->driverPrivate = radeon;
209
210 meta_init_metaops(ctx, &radeon->meta);
211
212 _mesa_meta_init(ctx);
213
214 /* DRI fields */
215 radeon->dri.context = driContextPriv;
216 radeon->dri.screen = sPriv;
217 radeon->dri.hwContext = driContextPriv->hHWContext;
218 radeon->dri.hwLock = &sPriv->pSAREA->lock;
219 radeon->dri.hwLockCount = 0;
220 radeon->dri.fd = sPriv->fd;
221 radeon->dri.drmMinor = sPriv->drm_version.minor;
222
223 radeon->sarea = (drm_radeon_sarea_t *) ((GLubyte *) sPriv->pSAREA +
224 screen->sarea_priv_offset);
225
226 /* Setup IRQs */
227 fthrottle_mode = driQueryOptioni(&radeon->optionCache, "fthrottle_mode");
228 radeon->iw.irq_seq = -1;
229 radeon->irqsEmitted = 0;
230 radeon->do_irqs = (fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS &&
231 radeon->radeonScreen->irq);
232
233 radeon->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
234
235 if (!radeon->do_irqs)
236 fprintf(stderr,
237 "IRQ's not enabled, falling back to %s: %d %d\n",
238 radeon->do_usleeps ? "usleeps" : "busy waits",
239 fthrottle_mode, radeon->radeonScreen->irq);
240
241 radeon->texture_depth = driQueryOptioni (&radeon->optionCache,
242 "texture_depth");
243 if (radeon->texture_depth == DRI_CONF_TEXTURE_DEPTH_FB)
244 radeon->texture_depth = ( glVisual->rgbBits > 16 ) ?
245 DRI_CONF_TEXTURE_DEPTH_32 : DRI_CONF_TEXTURE_DEPTH_16;
246
247 if (IS_R600_CLASS(radeon->radeonScreen)) {
248 radeon->texture_row_align = 256;
249 radeon->texture_rect_row_align = 256;
250 radeon->texture_compressed_row_align = 256;
251 } else if (IS_R200_CLASS(radeon->radeonScreen) ||
252 IS_R100_CLASS(radeon->radeonScreen)) {
253 radeon->texture_row_align = 32;
254 radeon->texture_rect_row_align = 64;
255 radeon->texture_compressed_row_align = 32;
256 } else { /* R300 - not sure this is all correct */
257 int chip_family = radeon->radeonScreen->chip_family;
258 if (chip_family == CHIP_FAMILY_RS600 ||
259 chip_family == CHIP_FAMILY_RS690 ||
260 chip_family == CHIP_FAMILY_RS740)
261 radeon->texture_row_align = 64;
262 else
263 radeon->texture_row_align = 32;
264 radeon->texture_rect_row_align = 64;
265 radeon->texture_compressed_row_align = 64;
266 }
267
268 make_empty_list(&radeon->query.not_flushed_head);
269 radeon_init_dma(radeon);
270
271 return GL_TRUE;
272 }
273
274
275
276 /**
277 * Destroy the command buffer and state atoms.
278 */
279 static void radeon_destroy_atom_list(radeonContextPtr radeon)
280 {
281 struct radeon_state_atom *atom;
282
283 foreach(atom, &radeon->hw.atomlist) {
284 FREE(atom->cmd);
285 if (atom->lastcmd)
286 FREE(atom->lastcmd);
287 }
288
289 }
290
291 /**
292 * Cleanup common context fields.
293 * Called by r200DestroyContext/r300DestroyContext
294 */
295 void radeonDestroyContext(__DRIcontextPrivate *driContextPriv )
296 {
297 #ifdef RADEON_BO_TRACK
298 FILE *track;
299 #endif
300 GET_CURRENT_CONTEXT(ctx);
301 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
302 radeonContextPtr current = ctx ? RADEON_CONTEXT(ctx) : NULL;
303
304 assert(radeon);
305
306 _mesa_meta_free(radeon->glCtx);
307
308 if (radeon == current) {
309 radeon_firevertices(radeon);
310 _mesa_make_current(NULL, NULL, NULL);
311 }
312
313 if (!is_empty_list(&radeon->dma.reserved)) {
314 rcommonFlushCmdBuf( radeon, __FUNCTION__ );
315 }
316
317 radeonFreeDmaRegions(radeon);
318 radeonReleaseArrays(radeon->glCtx, ~0);
319 meta_destroy_metaops(&radeon->meta);
320 if (radeon->vtbl.free_context)
321 radeon->vtbl.free_context(radeon->glCtx);
322 _swsetup_DestroyContext( radeon->glCtx );
323 _tnl_DestroyContext( radeon->glCtx );
324 _vbo_DestroyContext( radeon->glCtx );
325 _swrast_DestroyContext( radeon->glCtx );
326
327 /* free atom list */
328 /* free the Mesa context */
329 _mesa_destroy_context(radeon->glCtx);
330
331 /* _mesa_destroy_context() might result in calls to functions that
332 * depend on the DriverCtx, so don't set it to NULL before.
333 *
334 * radeon->glCtx->DriverCtx = NULL;
335 */
336 /* free the option cache */
337 driDestroyOptionCache(&radeon->optionCache);
338
339 rcommonDestroyCmdBuf(radeon);
340
341 radeon_destroy_atom_list(radeon);
342
343 if (radeon->state.scissor.pClipRects) {
344 FREE(radeon->state.scissor.pClipRects);
345 radeon->state.scissor.pClipRects = 0;
346 }
347 #ifdef RADEON_BO_TRACK
348 track = fopen("/tmp/tracklog", "w");
349 if (track) {
350 radeon_tracker_print(&radeon->radeonScreen->bom->tracker, track);
351 fclose(track);
352 }
353 #endif
354 FREE(radeon);
355 }
356
357 /* Force the context `c' to be unbound from its buffer.
358 */
359 GLboolean radeonUnbindContext(__DRIcontextPrivate * driContextPriv)
360 {
361 radeonContextPtr radeon = (radeonContextPtr) driContextPriv->driverPrivate;
362
363 if (RADEON_DEBUG & RADEON_DRI)
364 fprintf(stderr, "%s ctx %p\n", __FUNCTION__,
365 radeon->glCtx);
366
367 return GL_TRUE;
368 }
369
370
371 static void
372 radeon_make_kernel_renderbuffer_current(radeonContextPtr radeon,
373 struct radeon_framebuffer *draw)
374 {
375 /* if radeon->fake */
376 struct radeon_renderbuffer *rb;
377
378 if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
379 if (!rb->bo) {
380 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
381 radeon->radeonScreen->frontOffset,
382 0,
383 0,
384 RADEON_GEM_DOMAIN_VRAM,
385 0);
386 }
387 rb->cpp = radeon->radeonScreen->cpp;
388 rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
389 }
390 if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
391 if (!rb->bo) {
392 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
393 radeon->radeonScreen->backOffset,
394 0,
395 0,
396 RADEON_GEM_DOMAIN_VRAM,
397 0);
398 }
399 rb->cpp = radeon->radeonScreen->cpp;
400 rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
401 }
402 if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
403 if (!rb->bo) {
404 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
405 radeon->radeonScreen->depthOffset,
406 0,
407 0,
408 RADEON_GEM_DOMAIN_VRAM,
409 0);
410 }
411 rb->cpp = radeon->radeonScreen->cpp;
412 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
413 }
414 if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) {
415 if (!rb->bo) {
416 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
417 radeon->radeonScreen->depthOffset,
418 0,
419 0,
420 RADEON_GEM_DOMAIN_VRAM,
421 0);
422 }
423 rb->cpp = radeon->radeonScreen->cpp;
424 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
425 }
426 }
427
428 static void
429 radeon_make_renderbuffer_current(radeonContextPtr radeon,
430 struct radeon_framebuffer *draw)
431 {
432 int size = 4096*4096*4;
433 /* if radeon->fake */
434 struct radeon_renderbuffer *rb;
435
436 if (radeon->radeonScreen->kernel_mm) {
437 radeon_make_kernel_renderbuffer_current(radeon, draw);
438 return;
439 }
440
441
442 if ((rb = (void *)draw->base.Attachment[BUFFER_FRONT_LEFT].Renderbuffer)) {
443 if (!rb->bo) {
444 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
445 radeon->radeonScreen->frontOffset +
446 radeon->radeonScreen->fbLocation,
447 size,
448 4096,
449 RADEON_GEM_DOMAIN_VRAM,
450 0);
451 }
452 rb->cpp = radeon->radeonScreen->cpp;
453 rb->pitch = radeon->radeonScreen->frontPitch * rb->cpp;
454 }
455 if ((rb = (void *)draw->base.Attachment[BUFFER_BACK_LEFT].Renderbuffer)) {
456 if (!rb->bo) {
457 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
458 radeon->radeonScreen->backOffset +
459 radeon->radeonScreen->fbLocation,
460 size,
461 4096,
462 RADEON_GEM_DOMAIN_VRAM,
463 0);
464 }
465 rb->cpp = radeon->radeonScreen->cpp;
466 rb->pitch = radeon->radeonScreen->backPitch * rb->cpp;
467 }
468 if ((rb = (void *)draw->base.Attachment[BUFFER_DEPTH].Renderbuffer)) {
469 if (!rb->bo) {
470 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
471 radeon->radeonScreen->depthOffset +
472 radeon->radeonScreen->fbLocation,
473 size,
474 4096,
475 RADEON_GEM_DOMAIN_VRAM,
476 0);
477 }
478 rb->cpp = radeon->radeonScreen->cpp;
479 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
480 }
481 if ((rb = (void *)draw->base.Attachment[BUFFER_STENCIL].Renderbuffer)) {
482 if (!rb->bo) {
483 rb->bo = radeon_bo_open(radeon->radeonScreen->bom,
484 radeon->radeonScreen->depthOffset +
485 radeon->radeonScreen->fbLocation,
486 size,
487 4096,
488 RADEON_GEM_DOMAIN_VRAM,
489 0);
490 }
491 rb->cpp = radeon->radeonScreen->cpp;
492 rb->pitch = radeon->radeonScreen->depthPitch * rb->cpp;
493 }
494 }
495
496 static unsigned
497 radeon_bits_per_pixel(const struct radeon_renderbuffer *rb)
498 {
499 return _mesa_get_format_bytes(rb->base.Format) * 8;
500 }
501
502 void
503 radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
504 {
505 unsigned int attachments[10];
506 __DRIbuffer *buffers = NULL;
507 __DRIscreen *screen;
508 struct radeon_renderbuffer *rb;
509 int i, count;
510 struct radeon_framebuffer *draw;
511 radeonContextPtr radeon;
512 char *regname;
513 struct radeon_bo *depth_bo = NULL, *bo;
514
515 if (RADEON_DEBUG & RADEON_DRI)
516 fprintf(stderr, "enter %s, drawable %p\n", __func__, drawable);
517
518 draw = drawable->driverPrivate;
519 screen = context->driScreenPriv;
520 radeon = (radeonContextPtr) context->driverPrivate;
521
522 if (screen->dri2.loader
523 && (screen->dri2.loader->base.version > 2)
524 && (screen->dri2.loader->getBuffersWithFormat != NULL)) {
525 struct radeon_renderbuffer *depth_rb;
526 struct radeon_renderbuffer *stencil_rb;
527
528 i = 0;
529 if ((radeon->is_front_buffer_rendering ||
530 radeon->is_front_buffer_reading ||
531 !draw->color_rb[1])
532 && draw->color_rb[0]) {
533 attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
534 attachments[i++] = radeon_bits_per_pixel(draw->color_rb[0]);
535 }
536
537 if (draw->color_rb[1]) {
538 attachments[i++] = __DRI_BUFFER_BACK_LEFT;
539 attachments[i++] = radeon_bits_per_pixel(draw->color_rb[1]);
540 }
541
542 depth_rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
543 stencil_rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
544
545 if ((depth_rb != NULL) && (stencil_rb != NULL)) {
546 attachments[i++] = __DRI_BUFFER_DEPTH_STENCIL;
547 attachments[i++] = radeon_bits_per_pixel(depth_rb);
548 } else if (depth_rb != NULL) {
549 attachments[i++] = __DRI_BUFFER_DEPTH;
550 attachments[i++] = radeon_bits_per_pixel(depth_rb);
551 } else if (stencil_rb != NULL) {
552 attachments[i++] = __DRI_BUFFER_STENCIL;
553 attachments[i++] = radeon_bits_per_pixel(stencil_rb);
554 }
555
556 buffers = (*screen->dri2.loader->getBuffersWithFormat)(drawable,
557 &drawable->w,
558 &drawable->h,
559 attachments, i / 2,
560 &count,
561 drawable->loaderPrivate);
562 } else if (screen->dri2.loader) {
563 i = 0;
564 if (draw->color_rb[0])
565 attachments[i++] = __DRI_BUFFER_FRONT_LEFT;
566 if (draw->color_rb[1])
567 attachments[i++] = __DRI_BUFFER_BACK_LEFT;
568 if (radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH))
569 attachments[i++] = __DRI_BUFFER_DEPTH;
570 if (radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL))
571 attachments[i++] = __DRI_BUFFER_STENCIL;
572
573 buffers = (*screen->dri2.loader->getBuffers)(drawable,
574 &drawable->w,
575 &drawable->h,
576 attachments, i,
577 &count,
578 drawable->loaderPrivate);
579 }
580
581 if (buffers == NULL)
582 return;
583
584 /* set one cliprect to cover the whole drawable */
585 drawable->x = 0;
586 drawable->y = 0;
587 drawable->backX = 0;
588 drawable->backY = 0;
589 drawable->numClipRects = 1;
590 drawable->pClipRects[0].x1 = 0;
591 drawable->pClipRects[0].y1 = 0;
592 drawable->pClipRects[0].x2 = drawable->w;
593 drawable->pClipRects[0].y2 = drawable->h;
594 drawable->numBackClipRects = 1;
595 drawable->pBackClipRects[0].x1 = 0;
596 drawable->pBackClipRects[0].y1 = 0;
597 drawable->pBackClipRects[0].x2 = drawable->w;
598 drawable->pBackClipRects[0].y2 = drawable->h;
599 for (i = 0; i < count; i++) {
600 switch (buffers[i].attachment) {
601 case __DRI_BUFFER_FRONT_LEFT:
602 rb = draw->color_rb[0];
603 regname = "dri2 front buffer";
604 break;
605 case __DRI_BUFFER_FAKE_FRONT_LEFT:
606 rb = draw->color_rb[0];
607 regname = "dri2 fake front buffer";
608 break;
609 case __DRI_BUFFER_BACK_LEFT:
610 rb = draw->color_rb[1];
611 regname = "dri2 back buffer";
612 break;
613 case __DRI_BUFFER_DEPTH:
614 rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
615 regname = "dri2 depth buffer";
616 break;
617 case __DRI_BUFFER_DEPTH_STENCIL:
618 rb = radeon_get_renderbuffer(&draw->base, BUFFER_DEPTH);
619 regname = "dri2 depth / stencil buffer";
620 break;
621 case __DRI_BUFFER_STENCIL:
622 rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
623 regname = "dri2 stencil buffer";
624 break;
625 case __DRI_BUFFER_ACCUM:
626 default:
627 fprintf(stderr,
628 "unhandled buffer attach event, attacment type %d\n",
629 buffers[i].attachment);
630 return;
631 }
632
633 if (rb == NULL)
634 continue;
635
636 if (rb->bo) {
637 uint32_t name = radeon_gem_name_bo(rb->bo);
638 if (name == buffers[i].name)
639 continue;
640 }
641
642 if (RADEON_DEBUG & RADEON_DRI)
643 fprintf(stderr,
644 "attaching buffer %s, %d, at %d, cpp %d, pitch %d\n",
645 regname, buffers[i].name, buffers[i].attachment,
646 buffers[i].cpp, buffers[i].pitch);
647
648 rb->cpp = buffers[i].cpp;
649 rb->pitch = buffers[i].pitch;
650 rb->base.Width = drawable->w;
651 rb->base.Height = drawable->h;
652 rb->has_surface = 0;
653
654 if (buffers[i].attachment == __DRI_BUFFER_STENCIL && depth_bo) {
655 if (RADEON_DEBUG & RADEON_DRI)
656 fprintf(stderr, "(reusing depth buffer as stencil)\n");
657 bo = depth_bo;
658 radeon_bo_ref(bo);
659 } else {
660 uint32_t tiling_flags = 0, pitch = 0;
661 int ret;
662
663 bo = radeon_bo_open(radeon->radeonScreen->bom,
664 buffers[i].name,
665 0,
666 0,
667 RADEON_GEM_DOMAIN_VRAM,
668 buffers[i].flags);
669
670 if (bo == NULL) {
671
672 fprintf(stderr, "failed to attach %s %d\n",
673 regname, buffers[i].name);
674
675 }
676
677 ret = radeon_bo_get_tiling(bo, &tiling_flags, &pitch);
678 if (tiling_flags & RADEON_TILING_MACRO)
679 bo->flags |= RADEON_BO_FLAGS_MACRO_TILE;
680 if (tiling_flags & RADEON_TILING_MICRO)
681 bo->flags |= RADEON_BO_FLAGS_MICRO_TILE;
682
683 }
684
685 if (buffers[i].attachment == __DRI_BUFFER_DEPTH) {
686 if (draw->base.Visual.depthBits == 16)
687 rb->cpp = 2;
688 depth_bo = bo;
689 }
690
691 radeon_renderbuffer_set_bo(rb, bo);
692 radeon_bo_unref(bo);
693
694 if (buffers[i].attachment == __DRI_BUFFER_DEPTH_STENCIL) {
695 rb = radeon_get_renderbuffer(&draw->base, BUFFER_STENCIL);
696 if (rb != NULL) {
697 struct radeon_bo *stencil_bo = NULL;
698
699 if (rb->bo) {
700 uint32_t name = radeon_gem_name_bo(rb->bo);
701 if (name == buffers[i].name)
702 continue;
703 }
704
705 stencil_bo = bo;
706 radeon_bo_ref(stencil_bo);
707 radeon_renderbuffer_set_bo(rb, stencil_bo);
708 radeon_bo_unref(stencil_bo);
709 }
710 }
711 }
712
713 driUpdateFramebufferSize(radeon->glCtx, drawable);
714 }
715
716 /* Force the context `c' to be the current context and associate with it
717 * buffer `b'.
718 */
719 GLboolean radeonMakeCurrent(__DRIcontextPrivate * driContextPriv,
720 __DRIdrawablePrivate * driDrawPriv,
721 __DRIdrawablePrivate * driReadPriv)
722 {
723 radeonContextPtr radeon;
724 struct radeon_framebuffer *drfb;
725 struct gl_framebuffer *readfb;
726
727 if (!driContextPriv) {
728 if (RADEON_DEBUG & RADEON_DRI)
729 fprintf(stderr, "%s ctx is null\n", __FUNCTION__);
730 _mesa_make_current(NULL, NULL, NULL);
731 return GL_TRUE;
732 }
733
734 radeon = (radeonContextPtr) driContextPriv->driverPrivate;
735 drfb = driDrawPriv->driverPrivate;
736 readfb = driReadPriv->driverPrivate;
737
738 if (driContextPriv->driScreenPriv->dri2.enabled) {
739 radeon_update_renderbuffers(driContextPriv, driDrawPriv);
740 if (driDrawPriv != driReadPriv)
741 radeon_update_renderbuffers(driContextPriv, driReadPriv);
742 _mesa_reference_renderbuffer(&radeon->state.color.rb,
743 &(radeon_get_renderbuffer(&drfb->base, BUFFER_BACK_LEFT)->base));
744 _mesa_reference_renderbuffer(&radeon->state.depth.rb,
745 &(radeon_get_renderbuffer(&drfb->base, BUFFER_DEPTH)->base));
746 } else {
747 radeon_make_renderbuffer_current(radeon, drfb);
748 }
749
750 if (RADEON_DEBUG & RADEON_DRI)
751 fprintf(stderr, "%s ctx %p dfb %p rfb %p\n", __FUNCTION__, radeon->glCtx, drfb, readfb);
752
753 driUpdateFramebufferSize(radeon->glCtx, driDrawPriv);
754 if (driReadPriv != driDrawPriv)
755 driUpdateFramebufferSize(radeon->glCtx, driReadPriv);
756
757 _mesa_make_current(radeon->glCtx, &drfb->base, readfb);
758
759 _mesa_update_state(radeon->glCtx);
760
761 if (radeon->glCtx->DrawBuffer == &drfb->base) {
762 if (driDrawPriv->swap_interval == (unsigned)-1) {
763 int i;
764 driDrawPriv->vblFlags =
765 (radeon->radeonScreen->irq != 0)
766 ? driGetDefaultVBlankFlags(&radeon->
767 optionCache)
768 : VBLANK_FLAG_NO_IRQ;
769
770 driDrawableInitVBlank(driDrawPriv);
771 drfb->vbl_waited = driDrawPriv->vblSeq;
772
773 for (i = 0; i < 2; i++) {
774 if (drfb->color_rb[i])
775 drfb->color_rb[i]->vbl_pending = driDrawPriv->vblSeq;
776 }
777
778 }
779
780 radeon_window_moved(radeon);
781 radeon_draw_buffer(radeon->glCtx, &drfb->base);
782 }
783
784
785 if (RADEON_DEBUG & RADEON_DRI)
786 fprintf(stderr, "End %s\n", __FUNCTION__);
787
788 return GL_TRUE;
789 }
790