2 #ifndef COMMON_CONTEXT_H
3 #define COMMON_CONTEXT_H
6 #include "math/m_vector.h"
8 #include "tnl/t_context.h"
9 #include "main/colormac.h"
11 #include "radeon_debug.h"
12 #include "radeon_screen.h"
13 #include "radeon_drm.h"
15 #include "tnl/t_vertex.h"
17 #include "dri_metaops.h"
18 struct radeon_context
;
20 #include "radeon_bocs_wrapper.h"
22 /* This union is used to avoid warnings/miscompilation
23 with float to uint32_t casts due to strict-aliasing */
24 typedef union { GLfloat f
; uint32_t ui32
; } float_ui32_type
;
26 struct radeon_context
;
27 typedef struct radeon_context radeonContextRec
;
28 typedef struct radeon_context
*radeonContextPtr
;
38 /* Rasterizing fallbacks */
39 /* See correponding strings in r200_swtcl.c */
40 #define RADEON_FALLBACK_TEXTURE 0x0001
41 #define RADEON_FALLBACK_DRAW_BUFFER 0x0002
42 #define RADEON_FALLBACK_STENCIL 0x0004
43 #define RADEON_FALLBACK_RENDER_MODE 0x0008
44 #define RADEON_FALLBACK_BLEND_EQ 0x0010
45 #define RADEON_FALLBACK_BLEND_FUNC 0x0020
46 #define RADEON_FALLBACK_DISABLE 0x0040
47 #define RADEON_FALLBACK_BORDER_MODE 0x0080
48 #define RADEON_FALLBACK_DEPTH_BUFFER 0x0100
49 #define RADEON_FALLBACK_STENCIL_BUFFER 0x0200
51 #define R200_FALLBACK_TEXTURE 0x01
52 #define R200_FALLBACK_DRAW_BUFFER 0x02
53 #define R200_FALLBACK_STENCIL 0x04
54 #define R200_FALLBACK_RENDER_MODE 0x08
55 #define R200_FALLBACK_DISABLE 0x10
56 #define R200_FALLBACK_BORDER_MODE 0x20
58 #define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */
59 #define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */
60 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */
61 #define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */
62 #define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */
63 #define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */
64 #define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */
65 #define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */
66 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */
68 /* The blit width for texture uploads
70 #define BLIT_WIDTH_BYTES 1024
72 /* Use the templated vertex format:
75 #define TAG(x) radeon##x
76 #include "tnl_dd/t_dd_vertex.h"
79 #define RADEON_RB_CLASS 0xdeadbeef
81 struct radeon_renderbuffer
83 struct gl_renderbuffer base
;
86 /* unsigned int offset; */
89 uint32_t draw_offset
; /* FBO */
90 /* boo Xorg 6.8.2 compat */
93 GLuint pf_pending
; /**< sequence number of pending flip */
94 GLuint vbl_pending
; /**< vblank sequence number of pending flip */
98 struct radeon_framebuffer
100 struct gl_framebuffer base
;
102 struct radeon_renderbuffer
*color_rb
[2];
108 int64_t swap_missed_ust
;
111 GLuint swap_missed_count
;
113 /* Drawable page flipping state */
115 GLint pf_current_page
;
121 struct radeon_colorbuffer_state
{
124 struct gl_renderbuffer
*rb
;
125 uint32_t draw_offset
; /* offset into color renderbuffer - FBOs */
128 struct radeon_depthbuffer_state
{
130 struct gl_renderbuffer
*rb
;
133 struct radeon_scissor_state
{
134 drm_clip_rect_t rect
;
137 GLuint numClipRects
; /* Cliprects active */
138 GLuint numAllocedClipRects
; /* Cliprects available */
139 drm_clip_rect_t
*pClipRects
;
142 struct radeon_stencilbuffer_state
{
143 GLuint clear
; /* rb3d_stencilrefmask value */
146 struct radeon_state_atom
{
147 struct radeon_state_atom
*next
, *prev
;
148 const char *name
; /* for debug */
149 int cmd_size
; /* size in bytes */
152 GLuint
*cmd
; /* one or more cmd's */
153 GLuint
*lastcmd
; /* one or more cmd's */
154 GLboolean dirty
; /* dirty-mark in emit_state_list */
155 int (*check
) (GLcontext
*, struct radeon_state_atom
*atom
); /* is this state active? */
156 void (*emit
) (GLcontext
*, struct radeon_state_atom
*atom
);
159 struct radeon_hw_state
{
160 /* Head of the linked list of state atoms. */
161 struct radeon_state_atom atomlist
;
162 int max_state_size
; /* Number of bytes necessary for a full state emit. */
163 int max_post_flush_size
; /* Number of bytes necessary for post flushing emits */
164 GLboolean is_dirty
, all_dirty
;
168 /* Texture related */
169 typedef struct _radeon_texture_image radeon_texture_image
;
171 struct _radeon_texture_image
{
172 struct gl_texture_image base
;
175 * If mt != 0, the image is stored in hardware format in the
176 * given mipmap tree. In this case, base.Data may point into the
177 * mapping of the buffer object that contains the mipmap tree.
179 * If mt == 0, the image is stored in normal memory pointed to
182 struct _radeon_mipmap_tree
*mt
;
183 struct radeon_bo
*bo
;
185 int mtlevel
; /** if mt != 0, this is the image's level in the mipmap tree */
186 int mtface
; /** if mt != 0, this is the image's face in the mipmap tree */
190 static INLINE radeon_texture_image
*get_radeon_texture_image(struct gl_texture_image
*image
)
192 return (radeon_texture_image
*)image
;
196 typedef struct radeon_tex_obj radeonTexObj
, *radeonTexObjPtr
;
198 #define RADEON_TXO_MICRO_TILE (1 << 3)
200 /* Texture object in locally shared texture space.
202 struct radeon_tex_obj
{
203 struct gl_texture_object base
;
204 struct _radeon_mipmap_tree
*mt
;
207 * This is true if we've verified that the mipmap tree above is complete
211 /* Minimum LOD to be used during rendering */
213 /* Miximum LOD to be used during rendering */
216 GLuint override_offset
;
217 GLboolean image_override
; /* Image overridden by GLX_EXT_tfp */
218 GLuint tile_bits
; /* hw texture tile bits used on this texture */
219 struct radeon_bo
*bo
;
221 GLuint pp_txfilter
; /* hardware register values */
223 GLuint pp_txformat_x
;
224 GLuint pp_txsize
; /* npot only */
225 GLuint pp_txpitch
; /* npot only */
226 GLuint pp_border_color
;
227 GLuint pp_cubic_faces
; /* cube face 1,2,3,4 log2 sizes */
229 GLuint pp_txfilter_1
; /* r300 */
231 /* r700 texture states */
232 GLuint SQ_TEX_RESOURCE0
;
233 GLuint SQ_TEX_RESOURCE1
;
234 GLuint SQ_TEX_RESOURCE2
;
235 GLuint SQ_TEX_RESOURCE3
;
236 GLuint SQ_TEX_RESOURCE4
;
237 GLuint SQ_TEX_RESOURCE5
;
238 GLuint SQ_TEX_RESOURCE6
;
240 GLuint SQ_TEX_SAMPLER0
;
241 GLuint SQ_TEX_SAMPLER1
;
242 GLuint SQ_TEX_SAMPLER2
;
244 GLuint TD_PS_SAMPLER0_BORDER_RED
;
245 GLuint TD_PS_SAMPLER0_BORDER_GREEN
;
246 GLuint TD_PS_SAMPLER0_BORDER_BLUE
;
247 GLuint TD_PS_SAMPLER0_BORDER_ALPHA
;
249 GLboolean border_fallback
;
254 static INLINE radeonTexObj
* radeon_tex_obj(struct gl_texture_object
*texObj
)
256 return (radeonTexObj
*)texObj
;
259 /* occlusion query */
260 struct radeon_query_object
{
261 struct gl_query_object Base
;
262 struct radeon_bo
*bo
;
264 GLboolean emitted_begin
;
266 /* Double linked list of not flushed query objects */
267 struct radeon_query_object
*prev
, *next
;
270 /* Need refcounting on dma buffers:
272 struct radeon_dma_buffer
{
273 int refcount
; /* the number of retained regions in buf */
278 struct radeon_bo
*bo
; /** Buffer object where vertex data is stored */
279 int offset
; /** Offset into buffer object, in bytes */
280 int components
; /** Number of components per vertex */
281 int stride
; /** Stride in dwords (may be 0 for repeating) */
282 int count
; /** Number of vertices */
285 #define DMA_BO_FREE_TIME 100
287 struct radeon_dma_bo
{
288 struct radeon_dma_bo
*next
, *prev
;
289 struct radeon_bo
*bo
;
294 /* Active dma region. Allocations for vertices and retained
295 * regions come from here. Also used for emitting random vertices,
296 * these may be flushed by calling flush_current();
298 struct radeon_dma_bo free
;
299 struct radeon_dma_bo wait
;
300 struct radeon_dma_bo reserved
;
301 size_t current_used
; /** Number of bytes allocated and forgotten about */
302 size_t current_vertexptr
; /** End of active vertex region */
306 * If current_vertexptr != current_used then flush must be non-zero.
307 * flush must be called before non-active vertex allocations can be
310 void (*flush
) (GLcontext
*);
315 struct radeon_swtcl_info
{
321 /* Fallback rasterization functions
324 GLenum render_primitive
;
327 struct tnl_attr_map vertex_attrs
[VERT_ATTRIB_MAX
];
328 GLuint vertex_attr_count
;
330 GLuint emit_prediction
;
331 struct radeon_bo
*bo
;
334 #define RADEON_MAX_AOS_ARRAYS 16
335 struct radeon_tcl_info
{
336 struct radeon_aos aos
[RADEON_MAX_AOS_ARRAYS
];
338 struct radeon_bo
*elt_dma_bo
; /** Buffer object that contains element indices */
339 int elt_dma_offset
; /** Offset into this buffer object, in bytes */
342 struct radeon_ioctl
{
343 GLuint vertex_offset
;
345 struct radeon_bo
*bo
;
349 #define RADEON_MAX_PRIMS 64
357 static INLINE GLuint
radeonPackColor(GLuint cpp
,
358 GLubyte r
, GLubyte g
,
359 GLubyte b
, GLubyte a
)
363 return PACK_COLOR_565(r
, g
, b
);
365 return PACK_COLOR_8888(a
, r
, g
, b
);
371 #define MAX_CMD_BUF_SZ (16*1024)
373 #define MAX_DMA_BUF_SZ (64*1024)
375 struct radeon_store
{
378 char cmd_buf
[MAX_CMD_BUF_SZ
];
383 struct radeon_dri_mirror
{
384 __DRIcontext
*context
; /* DRI context */
385 __DRIscreen
*screen
; /* DRI screen */
387 drm_context_t hwContext
;
388 drm_hw_lock_t
*hwLock
;
394 typedef void (*radeon_tri_func
) (radeonContextPtr
,
396 radeonVertex
*, radeonVertex
*);
398 typedef void (*radeon_line_func
) (radeonContextPtr
,
399 radeonVertex
*, radeonVertex
*);
401 typedef void (*radeon_point_func
) (radeonContextPtr
, radeonVertex
*);
403 #define RADEON_MAX_BOS 32
404 struct radeon_state
{
405 struct radeon_colorbuffer_state color
;
406 struct radeon_depthbuffer_state depth
;
407 struct radeon_scissor_state scissor
;
408 struct radeon_stencilbuffer_state stencil
;
412 * This structure holds the command buffer while it is being constructed.
414 * The first batch of commands in the buffer is always the state that needs
415 * to be re-emitted when the context is lost. This batch can be skipped
418 struct radeon_cmdbuf
{
419 struct radeon_cs_manager
*csm
;
420 struct radeon_cs
*cs
;
421 int size
; /** # of dwords total */
422 unsigned int flushing
:1; /** whether we're currently in FlushCmdBufLocked */
425 struct radeon_context
{
427 radeonScreenPtr radeonScreen
; /* Screen private DRI data */
429 /* Texture object bookkeeping
432 float initialMaxAnisotropy
;
433 uint32_t texture_row_align
;
434 uint32_t texture_rect_row_align
;
435 uint32_t texture_compressed_row_align
;
437 struct radeon_dma dma
;
438 struct radeon_hw_state hw
;
439 /* Rasterization and vertex state:
444 DECLARE_RENDERINPUTS(tnl_index_bitset
); /* index of bits for last tnl_install_attrs */
446 /* Drawable, cliprect and scissor information */
447 GLuint numClipRects
; /* Cliprects for the draw buffer */
448 drm_clip_rect_t
*pClipRects
;
449 unsigned int lastStamp
;
450 drm_radeon_sarea_t
*sarea
; /* Private SAREA data */
452 /* Mirrors of some DRI state */
453 struct radeon_dri_mirror dri
;
459 drm_radeon_irq_wait_t iw
;
461 /* Derived state - for r300 only */
462 struct radeon_state state
;
464 struct radeon_swtcl_info swtcl
;
465 struct radeon_tcl_info tcl
;
466 /* Configuration cache
468 driOptionCache optionCache
;
470 struct radeon_cmdbuf cmdbuf
;
472 struct radeon_debug debug
;
474 drm_clip_rect_t fboRect
;
475 GLboolean constant_cliprect
; /* use for FBO or DRI2 rendering */
476 GLboolean front_cliprects
;
479 * Set if rendering has occured to the drawable's front buffer.
481 * This is used in the DRI2 case to detect that glFlush should also copy
482 * the contents of the fake front buffer to the real front buffer.
484 GLboolean front_buffer_dirty
;
487 * Track whether front-buffer rendering is currently enabled
489 * A separate flag is used to track this in order to support MRT more
492 GLboolean is_front_buffer_rendering
;
495 * Track whether front-buffer is the current read target.
497 * This is closely associated with is_front_buffer_rendering, but may
498 * be set separately. The DRI2 fake front buffer must be referenced
501 GLboolean is_front_buffer_reading
;
503 struct dri_metaops meta
;
506 struct radeon_query_object
*current
;
507 struct radeon_state_atom queryobj
;
511 void (*get_lock
)(radeonContextPtr radeon
);
512 void (*update_viewport_offset
)(GLcontext
*ctx
);
513 void (*emit_cs_header
)(struct radeon_cs
*cs
, radeonContextPtr rmesa
);
514 void (*swtcl_flush
)(GLcontext
*ctx
, uint32_t offset
);
515 void (*pre_emit_atoms
)(radeonContextPtr rmesa
);
516 void (*pre_emit_state
)(radeonContextPtr rmesa
);
517 void (*fallback
)(GLcontext
*ctx
, GLuint bit
, GLboolean mode
);
518 void (*free_context
)(GLcontext
*ctx
);
519 void (*emit_query_finish
)(radeonContextPtr radeon
);
520 void (*update_scissor
)(GLcontext
*ctx
);
521 unsigned (*blit
)(GLcontext
*ctx
,
522 struct radeon_bo
*src_bo
,
524 gl_format src_mesaformat
,
528 unsigned src_x_offset
,
529 unsigned src_y_offset
,
530 struct radeon_bo
*dst_bo
,
532 gl_format dst_mesaformat
,
536 unsigned dst_x_offset
,
537 unsigned dst_y_offset
,
544 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
546 static inline __DRIdrawable
* radeon_get_drawable(radeonContextPtr radeon
)
548 return radeon
->dri
.context
->driDrawablePriv
;
551 static inline __DRIdrawable
* radeon_get_readable(radeonContextPtr radeon
)
553 return radeon
->dri
.context
->driReadablePriv
;
557 * This function takes a float and packs it into a uint32_t
559 static INLINE
uint32_t radeonPackFloat32(float fl
)
570 /* This is probably wrong for some values, I need to test this
571 * some more. Range checking would be a good idea also..
573 * But it works for most things. I'll fix it later if someone
574 * else with a better clue doesn't
576 static INLINE
uint32_t radeonPackFloat24(float f
)
580 uint32_t float24
= 0;
585 mantissa
= frexpf(f
, &exponent
);
589 float24
|= (1 << 23);
590 mantissa
= mantissa
* -1.0;
592 /* Handle exponent, bias of 63 */
594 float24
|= (exponent
<< 16);
595 /* Kill 7 LSB of mantissa */
596 float24
|= (radeonPackFloat32(mantissa
) & 0x7FFFFF) >> 7;
601 GLboolean
radeonInitContext(radeonContextPtr radeon
,
602 struct dd_function_table
* functions
,
603 const __GLcontextModes
* glVisual
,
604 __DRIcontext
* driContextPriv
,
605 void *sharedContextPrivate
);
607 void radeonCleanupContext(radeonContextPtr radeon
);
608 GLboolean
radeonUnbindContext(__DRIcontext
* driContextPriv
);
609 void radeon_update_renderbuffers(__DRIcontext
*context
, __DRIdrawable
*drawable
,
610 GLboolean front_only
);
611 GLboolean
radeonMakeCurrent(__DRIcontext
* driContextPriv
,
612 __DRIdrawable
* driDrawPriv
,
613 __DRIdrawable
* driReadPriv
);
614 extern void radeonDestroyContext(__DRIcontext
* driContextPriv
);