git.libre-soc.org Git - mesa.git/blob - src/mesa/drivers/dri/radeon/radeon_common

2 #ifndef COMMON_CONTEXT_H

3 #define COMMON_CONTEXT_H

5 #include "main/mm.h"

6 #include "math/m_vector.h"

7 #include "texmem.h"

8 #include "tnl/t_context.h"

9 #include "main/colormac.h"

11 #include "radeon_debug.h"

12 #include "radeon_screen.h"

13 #include "radeon_drm.h"

14 #include "dri_util.h"

15 #include "tnl/t_vertex.h"

17 struct radeon_context;

19 #include "radeon_bocs_wrapper.h"

21 /* This union is used to avoid warnings/miscompilation

22 with float to uint32_t casts due to strict-aliasing */

 typedef union { GLfloat f; uint32_t ui32; } float_ui32_type;

25 struct radeon_context;

26 typedef struct radeon_context radeonContextRec;

27 typedef struct radeon_context *radeonContextPtr;

30 #define TEX_0 0x1

31 #define TEX_1 0x2

32 #define TEX_2 0x4

33 #define TEX_3 0x8

34 #define TEX_4 0x10

35 #define TEX_5 0x20

37 /* Rasterizing fallbacks */

38 /* See correponding strings in r200_swtcl.c */

39 #define RADEON_FALLBACK_TEXTURE 0x0001

40 #define RADEON_FALLBACK_DRAW_BUFFER 0x0002

41 #define RADEON_FALLBACK_STENCIL 0x0004

42 #define RADEON_FALLBACK_RENDER_MODE 0x0008

43 #define RADEON_FALLBACK_BLEND_EQ 0x0010

44 #define RADEON_FALLBACK_BLEND_FUNC 0x0020

45 #define RADEON_FALLBACK_DISABLE 0x0040

46 #define RADEON_FALLBACK_BORDER_MODE 0x0080

47 #define RADEON_FALLBACK_DEPTH_BUFFER 0x0100

48 #define RADEON_FALLBACK_STENCIL_BUFFER 0x0200

50 #define R200_FALLBACK_TEXTURE 0x01

51 #define R200_FALLBACK_DRAW_BUFFER 0x02

52 #define R200_FALLBACK_STENCIL 0x04

53 #define R200_FALLBACK_RENDER_MODE 0x08

54 #define R200_FALLBACK_DISABLE 0x10

55 #define R200_FALLBACK_BORDER_MODE 0x20

57 #define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */

58 #define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */

59 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */

60 #define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */

61 #define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */

62 #define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */

63 #define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */

64 #define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */

65 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */

67 /* The blit width for texture uploads

68 */

69 #define BLIT_WIDTH_BYTES 1024

71 /* Use the templated vertex format:

72 */

73 #define COLOR_IS_RGBA

74 #define TAG(x) radeon##x

75 #include "tnl_dd/t_dd_vertex.h"

76 #undef TAG

78 #define RADEON_RB_CLASS 0xdeadbeef

80 struct radeon_renderbuffer

81 {

82 struct gl_renderbuffer base;

83 struct radeon_bo *bo;

84 unsigned int cpp;

85 /* unsigned int offset; */

86 unsigned int pitch;

88 uint32_t draw_offset; /* FBO */

89 /* boo Xorg 6.8.2 compat */

90 int has_surface;

92 GLuint pf_pending; /**< sequence number of pending flip */

93 GLuint vbl_pending; /**< vblank sequence number of pending flip */

94 __DRIdrawable *dPriv;

96 /* r6xx+ tiling */

97 GLuint tile_config;

98 GLint group_bytes;

99 GLint num_channels;

100 GLint num_banks;

101 GLint r7xx_bank_op;

102 };

103

104 struct radeon_framebuffer

105 {

106 struct gl_framebuffer base;

107

         struct radeon_renderbuffer *color_rb[2];

109

110 GLuint vbl_waited;

111

112 /* buffer swap */

113 int64_t swap_ust;

114 int64_t swap_missed_ust;

115

116 GLuint swap_count;

117 GLuint swap_missed_count;

118

119 /* Drawable page flipping state */

120 GLboolean pf_active;

121 GLint pf_current_page;

122 GLint pf_num_pages;

123

124 };

125

126

127 struct radeon_colorbuffer_state {

128 GLuint clear;

129 int roundEnable;

130 struct gl_renderbuffer *rb;

131 uint32_t draw_offset; /* offset into color renderbuffer - FBOs */

132 };

133

134 struct radeon_depthbuffer_state {

135 GLuint clear;

136 struct gl_renderbuffer *rb;

137 };

138

139 struct radeon_scissor_state {

140 drm_clip_rect_t rect;

141 GLboolean enabled;

142

143 GLuint numClipRects; /* Cliprects active */

144 GLuint numAllocedClipRects; /* Cliprects available */

145 drm_clip_rect_t *pClipRects;

146 };

147

148 struct radeon_stencilbuffer_state {

149 GLuint clear; /* rb3d_stencilrefmask value */

150 };

151

152 struct radeon_state_atom {

153 struct radeon_state_atom *next, *prev;

154 const char *name; /* for debug */

155 int cmd_size; /* size in bytes */

156 GLuint idx;

157 GLuint is_tcl;

158 GLuint *cmd; /* one or more cmd's */

159 GLuint *lastcmd; /* one or more cmd's */

160 GLboolean dirty; /* dirty-mark in emit_state_list */

         int (*check) (struct gl_context *, struct radeon_state_atom *atom); /* is this state active? */

         void (*emit) (struct gl_context *, struct radeon_state_atom *atom);

163 };

164

165 struct radeon_hw_state {

166 /* Head of the linked list of state atoms. */

167 struct radeon_state_atom atomlist;

168 int max_state_size; /* Number of bytes necessary for a full state emit. */

169 int max_post_flush_size; /* Number of bytes necessary for post flushing emits */

170 GLboolean is_dirty, all_dirty;

171 };

172

173

174 /* Texture related */

175 typedef struct _radeon_texture_image radeon_texture_image;

176

177 struct _radeon_texture_image {

178 struct gl_texture_image base;

179

180 /**

181 * If mt != 0, the image is stored in hardware format in the

182 * given mipmap tree. In this case, base.Data may point into the

183 * mapping of the buffer object that contains the mipmap tree.

184 *

185 * If mt == 0, the image is stored in normal memory pointed to

186 * by base.Data.

187 */

188 struct _radeon_mipmap_tree *mt;

189 struct radeon_bo *bo;

190

191 int mtlevel; /** if mt != 0, this is the image's level in the mipmap tree */

192 int mtface; /** if mt != 0, this is the image's face in the mipmap tree */

193 };

194

195

 static INLINE radeon_texture_image *get_radeon_texture_image(struct gl_texture_image *image)

197 {

198 return (radeon_texture_image*)image;

199 }

200

201

202 typedef struct radeon_tex_obj radeonTexObj, *radeonTexObjPtr;

203

204 #define RADEON_TXO_MICRO_TILE (1 << 3)

205

206 /* Texture object in locally shared texture space.

207 */

208 struct radeon_tex_obj {

209 struct gl_texture_object base;

210 struct _radeon_mipmap_tree *mt;

211

212 /**

213 * This is true if we've verified that the mipmap tree above is complete

214 * and so on.

215 */

216 GLboolean validated;

217 /* Minimum LOD to be used during rendering */

218 unsigned minLod;

219 /* Miximum LOD to be used during rendering */

220 unsigned maxLod;

221

222 GLuint override_offset;

223 GLboolean image_override; /* Image overridden by GLX_EXT_tfp */

224 GLuint tile_bits; /* hw texture tile bits used on this texture */

225 struct radeon_bo *bo;

226

227 GLuint pp_txfilter; /* hardware register values */

228 GLuint pp_txformat;

229 GLuint pp_txformat_x;

230 GLuint pp_txsize; /* npot only */

231 GLuint pp_txpitch; /* npot only */

232 GLuint pp_border_color;

233 GLuint pp_cubic_faces; /* cube face 1,2,3,4 log2 sizes */

234

235 GLuint pp_txfilter_1; /* r300 */

236

237 /* r700 texture states */

238 GLuint SQ_TEX_RESOURCE0;

239 GLuint SQ_TEX_RESOURCE1;

240 GLuint SQ_TEX_RESOURCE2;

241 GLuint SQ_TEX_RESOURCE3;

242 GLuint SQ_TEX_RESOURCE4;

243 GLuint SQ_TEX_RESOURCE5;

244 GLuint SQ_TEX_RESOURCE6;

245

246 GLuint SQ_TEX_RESOURCE7;

247

248 GLuint SQ_TEX_SAMPLER0;

249 GLuint SQ_TEX_SAMPLER1;

250 GLuint SQ_TEX_SAMPLER2;

251

252 GLuint TD_PS_SAMPLER0_BORDER_RED;

253 GLuint TD_PS_SAMPLER0_BORDER_GREEN;

254 GLuint TD_PS_SAMPLER0_BORDER_BLUE;

255 GLuint TD_PS_SAMPLER0_BORDER_ALPHA;

256

257 GLboolean border_fallback;

258

259

260 };

261

 static INLINE radeonTexObj* radeon_tex_obj(struct gl_texture_object *texObj)

263 {

264 return (radeonTexObj*)texObj;

265 }

266

267 /* occlusion query */

268 struct radeon_query_object {

269 struct gl_query_object Base;

270 struct radeon_bo *bo;

271 int curr_offset;

272 GLboolean emitted_begin;

273

274 /* Double linked list of not flushed query objects */

275 struct radeon_query_object *prev, *next;

276 };

277

278 /* Need refcounting on dma buffers:

279 */

280 struct radeon_dma_buffer {

281 int refcount; /* the number of retained regions in buf */

282 drmBufPtr buf;

283 };

284

285 struct radeon_aos {

286 struct radeon_bo *bo; /** Buffer object where vertex data is stored */

287 int offset; /** Offset into buffer object, in bytes */

288 int components; /** Number of components per vertex */

289 int stride; /** Stride in dwords (may be 0 for repeating) */

290 int count; /** Number of vertices */

291 };

292

293 #define DMA_BO_FREE_TIME 100

294

295 struct radeon_dma_bo {

296 struct radeon_dma_bo *next, *prev;

297 struct radeon_bo *bo;

298 int expire_counter;

299 };

300

301 struct radeon_dma {

302 /* Active dma region. Allocations for vertices and retained

303 * regions come from here. Also used for emitting random vertices,

304 * these may be flushed by calling flush_current();

305 */

306 struct radeon_dma_bo free;

307 struct radeon_dma_bo wait;

308 struct radeon_dma_bo reserved;

309 size_t current_used; /** Number of bytes allocated and forgotten about */

310 size_t current_vertexptr; /** End of active vertex region */

311 size_t minimum_size;

312

313 /**

314 * If current_vertexptr != current_used then flush must be non-zero.

315 * flush must be called before non-active vertex allocations can be

316 * performed.

317 */

         void (*flush) (struct gl_context *);

319 };

320

321 /* radeon_swtcl.c

322 */

323 struct radeon_swtcl_info {

324

325 GLuint RenderIndex;

326 GLuint vertex_size;

327 GLubyte *verts;

328

329 /* Fallback rasterization functions

330 */

331 GLuint hw_primitive;

332 GLenum render_primitive;

333 GLuint numverts;

334

335 struct tnl_attr_map vertex_attrs[VERT_ATTRIB_MAX];

336 GLuint vertex_attr_count;

337

338 GLuint emit_prediction;

339 struct radeon_bo *bo;

340 };

341

342 #define RADEON_MAX_AOS_ARRAYS 16

343 struct radeon_tcl_info {

344 struct radeon_aos aos[RADEON_MAX_AOS_ARRAYS];

345 GLuint aos_count;

346 struct radeon_bo *elt_dma_bo; /** Buffer object that contains element indices */

347 int elt_dma_offset; /** Offset into this buffer object, in bytes */

348 };

349

350 struct radeon_ioctl {

351 GLuint vertex_offset;

352 GLuint vertex_max;

353 struct radeon_bo *bo;

354 GLuint vertex_size;

355 };

356

357 #define RADEON_MAX_PRIMS 64

358

359 struct radeon_prim {

360 GLuint start;

361 GLuint end;

362 GLuint prim;

363 };

364

365 static INLINE GLuint radeonPackColor(GLuint cpp,

366 GLubyte r, GLubyte g,

367 GLubyte b, GLubyte a)

368 {

369 switch (cpp) {

370 case 2:

                 return PACK_COLOR_565(r, g, b);

372 case 4:

                 return PACK_COLOR_8888(a, r, g, b);

374 default:

375 return 0;

376 }

377 }

378

379 #define MAX_CMD_BUF_SZ (16*1024)

380

381 #define MAX_DMA_BUF_SZ (64*1024)

382

383 struct radeon_store {

384 GLuint statenr;

385 GLuint primnr;

386 char cmd_buf[MAX_CMD_BUF_SZ];

387 int cmd_used;

388 int elts_start;

389 };

390

391 struct radeon_dri_mirror {

392 __DRIcontext *context; /* DRI context */

393 __DRIscreen *screen; /* DRI screen */

394

395 drm_context_t hwContext;

396 drm_hw_lock_t *hwLock;

397 int hwLockCount;

398 int fd;

399 int drmMinor;

400 };

401

 typedef void (*radeon_tri_func) (radeonContextPtr,

403 radeonVertex *,

404 radeonVertex *, radeonVertex *);

405

 typedef void (*radeon_line_func) (radeonContextPtr,

407 radeonVertex *, radeonVertex *);

408

 typedef void (*radeon_point_func) (radeonContextPtr, radeonVertex *);

410

411 #define RADEON_MAX_BOS 32

412 struct radeon_state {

413 struct radeon_colorbuffer_state color;

414 struct radeon_depthbuffer_state depth;

415 struct radeon_scissor_state scissor;

416 struct radeon_stencilbuffer_state stencil;

417 };

418

419 /**

420 * This structure holds the command buffer while it is being constructed.

421 *

422 * The first batch of commands in the buffer is always the state that needs

423 * to be re-emitted when the context is lost. This batch can be skipped

424 * otherwise.

425 */

426 struct radeon_cmdbuf {

427 struct radeon_cs_manager *csm;

428 struct radeon_cs *cs;

429 int size; /** # of dwords total */

         unsigned int flushing:1; /** whether we're currently in FlushCmdBufLocked */

431 };

432

433 struct radeon_context {

434 struct gl_context *glCtx;

435 radeonScreenPtr radeonScreen; /* Screen private DRI data */

436

437 /* Texture object bookkeeping

438 */

439 int texture_depth;

440 float initialMaxAnisotropy;

441 uint32_t texture_row_align;

442 uint32_t texture_rect_row_align;

443 uint32_t texture_compressed_row_align;

444

445 struct radeon_dma dma;

446 struct radeon_hw_state hw;

447 /* Rasterization and vertex state:

448 */

449 GLuint TclFallback;

450 GLuint Fallback;

451 GLuint NewGLState;

452 DECLARE_RENDERINPUTS(tnl_index_bitset); /* index of bits for last tnl_install_attrs */

453

454 /* Drawable, cliprect and scissor information */

455 GLuint numClipRects; /* Cliprects for the draw buffer */

456 drm_clip_rect_t *pClipRects;

457 unsigned int lastStamp;

458 drm_radeon_sarea_t *sarea; /* Private SAREA data */

459

460 /* Mirrors of some DRI state */

461 struct radeon_dri_mirror dri;

462

463 /* Busy waiting */

464 GLuint do_usleeps;

465 GLuint do_irqs;

466 GLuint irqsEmitted;

467 drm_radeon_irq_wait_t iw;

468

469 /* Derived state - for r300 only */

470 struct radeon_state state;

471

472 struct radeon_swtcl_info swtcl;

473 struct radeon_tcl_info tcl;

474 /* Configuration cache

475 */

476 driOptionCache optionCache;

477

478 struct radeon_cmdbuf cmdbuf;

479

480 struct radeon_debug debug;

481

482 drm_clip_rect_t fboRect;

483 GLboolean constant_cliprect; /* use for FBO or DRI2 rendering */

484 GLboolean front_cliprects;

485

486 /**

487 * Set if rendering has occured to the drawable's front buffer.

488 *

489 * This is used in the DRI2 case to detect that glFlush should also copy

490 * the contents of the fake front buffer to the real front buffer.

491 */

492 GLboolean front_buffer_dirty;

493

494 /**

495 * Track whether front-buffer rendering is currently enabled

496 *

497 * A separate flag is used to track this in order to support MRT more

498 * easily.

499 */

500 GLboolean is_front_buffer_rendering;

501

502 /**

503 * Track whether front-buffer is the current read target.

504 *

505 * This is closely associated with is_front_buffer_rendering, but may

506 * be set separately. The DRI2 fake front buffer must be referenced

507 * either way.

508 */

509 GLboolean is_front_buffer_reading;

510

511 struct {

512 struct radeon_query_object *current;

513 struct radeon_state_atom queryobj;

514 } query;

515

516 struct {

517 void (*get_lock)(radeonContextPtr radeon);

            void (*update_viewport_offset)(struct gl_context *ctx);

            void (*emit_cs_header)(struct radeon_cs *cs, radeonContextPtr rmesa);

            void (*swtcl_flush)(struct gl_context *ctx, uint32_t offset);

521 void (*pre_emit_atoms)(radeonContextPtr rmesa);

522 void (*pre_emit_state)(radeonContextPtr rmesa);

            void (*fallback)(struct gl_context *ctx, GLuint bit, GLboolean mode);

            void (*free_context)(struct gl_context *ctx);

525 void (*emit_query_finish)(radeonContextPtr radeon);

            void (*update_scissor)(struct gl_context *ctx);

527 unsigned (*check_blit)(gl_format mesa_format);

            unsigned (*blit)(struct gl_context *ctx,

529 struct radeon_bo *src_bo,

530 intptr_t src_offset,

531 gl_format src_mesaformat,

532 unsigned src_pitch,

533 unsigned src_width,

534 unsigned src_height,

535 unsigned src_x_offset,

536 unsigned src_y_offset,

537 struct radeon_bo *dst_bo,

538 intptr_t dst_offset,

539 gl_format dst_mesaformat,

540 unsigned dst_pitch,

541 unsigned dst_width,

542 unsigned dst_height,

543 unsigned dst_x_offset,

544 unsigned dst_y_offset,

545 unsigned reg_width,

546 unsigned reg_height,

547 unsigned flip_y);

548 unsigned (*is_format_renderable)(gl_format mesa_format);

549 } vtbl;

550 };

551

552 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))

553

 static inline __DRIdrawable* radeon_get_drawable(radeonContextPtr radeon)

555 {

         return radeon->dri.context->driDrawablePriv;

557 }

558

 static inline __DRIdrawable* radeon_get_readable(radeonContextPtr radeon)

560 {

         return radeon->dri.context->driReadablePriv;

562 }

563

564 /**

565 * This function takes a float and packs it into a uint32_t

566 */

 static INLINE uint32_t radeonPackFloat32(float fl)

568 {

569 union {

570 float fl;

571 uint32_t u;

572 } u;

573

574 u.fl = fl;

575 return u.u;

576 }

577

578 /* This is probably wrong for some values, I need to test this

579 * some more. Range checking would be a good idea also..

580 *

581 * But it works for most things. I'll fix it later if someone

582 * else with a better clue doesn't

583 */

 static INLINE uint32_t radeonPackFloat24(float f)

585 {

586 float mantissa;

587 int exponent;

588 uint32_t float24 = 0;

589

         if (f == 0.0)

591 return 0;

592

         mantissa = frexpf(f, &exponent);

594

595 /* Handle -ve */

         if (mantissa < 0) {

                 float24 |= (1 << 23);

598 mantissa = mantissa * -1.0;

599 }

600 /* Handle exponent, bias of 63 */

601 exponent += 62;

602 float24 |= (exponent << 16);

603 /* Kill 7 LSB of mantissa */

         float24 |= (radeonPackFloat32(mantissa) & 0x7FFFFF) >> 7;

605

606 return float24;

607 }

608

609 GLboolean radeonInitContext(radeonContextPtr radeon,

610 struct dd_function_table* functions,

611 const struct gl_config * glVisual,

612 __DRIcontext * driContextPriv,

613 void *sharedContextPrivate);

614

615 void radeonCleanupContext(radeonContextPtr radeon);

616 GLboolean radeonUnbindContext(__DRIcontext * driContextPriv);

 void radeon_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable,

618 GLboolean front_only);

619 GLboolean radeonMakeCurrent(__DRIcontext * driContextPriv,

620 __DRIdrawable * driDrawPriv,

621 __DRIdrawable * driReadPriv);

 extern void radeonDestroyContext(__DRIcontext * driContextPriv);

623 void radeon_prepare_render(radeonContextPtr radeon);

624

625 #endif