2 #ifndef COMMON_CONTEXT_H
3 #define COMMON_CONTEXT_H
6 #include "math/m_vector.h"
8 #include "tnl/t_context.h"
9 #include "main/colormac.h"
11 #include "radeon_debug.h"
12 #include "radeon_screen.h"
13 #include "radeon_drm.h"
15 #include "tnl/t_vertex.h"
17 struct radeon_context
;
19 #include "radeon_bocs_wrapper.h"
21 /* This union is used to avoid warnings/miscompilation
22 with float to uint32_t casts due to strict-aliasing */
23 typedef union { GLfloat f
; uint32_t ui32
; } float_ui32_type
;
25 struct radeon_context
;
26 typedef struct radeon_context radeonContextRec
;
27 typedef struct radeon_context
*radeonContextPtr
;
37 /* Rasterizing fallbacks */
38 /* See correponding strings in r200_swtcl.c */
39 #define RADEON_FALLBACK_TEXTURE 0x0001
40 #define RADEON_FALLBACK_DRAW_BUFFER 0x0002
41 #define RADEON_FALLBACK_STENCIL 0x0004
42 #define RADEON_FALLBACK_RENDER_MODE 0x0008
43 #define RADEON_FALLBACK_BLEND_EQ 0x0010
44 #define RADEON_FALLBACK_BLEND_FUNC 0x0020
45 #define RADEON_FALLBACK_DISABLE 0x0040
46 #define RADEON_FALLBACK_BORDER_MODE 0x0080
47 #define RADEON_FALLBACK_DEPTH_BUFFER 0x0100
48 #define RADEON_FALLBACK_STENCIL_BUFFER 0x0200
50 #define R200_FALLBACK_TEXTURE 0x01
51 #define R200_FALLBACK_DRAW_BUFFER 0x02
52 #define R200_FALLBACK_STENCIL 0x04
53 #define R200_FALLBACK_RENDER_MODE 0x08
54 #define R200_FALLBACK_DISABLE 0x10
55 #define R200_FALLBACK_BORDER_MODE 0x20
57 #define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */
58 #define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */
59 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */
60 #define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */
61 #define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */
62 #define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */
63 #define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */
64 #define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */
65 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */
67 /* The blit width for texture uploads
69 #define BLIT_WIDTH_BYTES 1024
71 /* Use the templated vertex format:
74 #define TAG(x) radeon##x
75 #include "tnl_dd/t_dd_vertex.h"
78 #define RADEON_RB_CLASS 0xdeadbeef
80 struct radeon_renderbuffer
82 struct gl_renderbuffer base
;
85 /* unsigned int offset; */
88 uint32_t draw_offset
; /* FBO */
89 /* boo Xorg 6.8.2 compat */
92 GLuint pf_pending
; /**< sequence number of pending flip */
93 GLuint vbl_pending
; /**< vblank sequence number of pending flip */
104 struct radeon_framebuffer
106 struct gl_framebuffer base
;
108 struct radeon_renderbuffer
*color_rb
[2];
114 int64_t swap_missed_ust
;
117 GLuint swap_missed_count
;
119 /* Drawable page flipping state */
121 GLint pf_current_page
;
127 struct radeon_colorbuffer_state
{
130 struct gl_renderbuffer
*rb
;
131 uint32_t draw_offset
; /* offset into color renderbuffer - FBOs */
134 struct radeon_depthbuffer_state
{
136 struct gl_renderbuffer
*rb
;
139 struct radeon_scissor_state
{
140 drm_clip_rect_t rect
;
143 GLuint numClipRects
; /* Cliprects active */
144 GLuint numAllocedClipRects
; /* Cliprects available */
145 drm_clip_rect_t
*pClipRects
;
148 struct radeon_stencilbuffer_state
{
149 GLuint clear
; /* rb3d_stencilrefmask value */
152 struct radeon_state_atom
{
153 struct radeon_state_atom
*next
, *prev
;
154 const char *name
; /* for debug */
155 int cmd_size
; /* size in bytes */
158 GLuint
*cmd
; /* one or more cmd's */
159 GLuint
*lastcmd
; /* one or more cmd's */
160 GLboolean dirty
; /* dirty-mark in emit_state_list */
161 int (*check
) (struct gl_context
*, struct radeon_state_atom
*atom
); /* is this state active? */
162 void (*emit
) (struct gl_context
*, struct radeon_state_atom
*atom
);
165 struct radeon_hw_state
{
166 /* Head of the linked list of state atoms. */
167 struct radeon_state_atom atomlist
;
168 int max_state_size
; /* Number of bytes necessary for a full state emit. */
169 int max_post_flush_size
; /* Number of bytes necessary for post flushing emits */
170 GLboolean is_dirty
, all_dirty
;
174 /* Texture related */
175 typedef struct _radeon_texture_image radeon_texture_image
;
177 struct _radeon_texture_image
{
178 struct gl_texture_image base
;
181 * If mt != 0, the image is stored in hardware format in the
182 * given mipmap tree. In this case, base.Data may point into the
183 * mapping of the buffer object that contains the mipmap tree.
185 * If mt == 0, the image is stored in normal memory pointed to
188 struct _radeon_mipmap_tree
*mt
;
189 struct radeon_bo
*bo
;
191 int mtlevel
; /** if mt != 0, this is the image's level in the mipmap tree */
192 int mtface
; /** if mt != 0, this is the image's face in the mipmap tree */
196 static INLINE radeon_texture_image
*get_radeon_texture_image(struct gl_texture_image
*image
)
198 return (radeon_texture_image
*)image
;
202 typedef struct radeon_tex_obj radeonTexObj
, *radeonTexObjPtr
;
204 #define RADEON_TXO_MICRO_TILE (1 << 3)
206 /* Texture object in locally shared texture space.
208 struct radeon_tex_obj
{
209 struct gl_texture_object base
;
210 struct _radeon_mipmap_tree
*mt
;
213 * This is true if we've verified that the mipmap tree above is complete
217 /* Minimum LOD to be used during rendering */
219 /* Miximum LOD to be used during rendering */
222 GLuint override_offset
;
223 GLboolean image_override
; /* Image overridden by GLX_EXT_tfp */
224 GLuint tile_bits
; /* hw texture tile bits used on this texture */
225 struct radeon_bo
*bo
;
227 GLuint pp_txfilter
; /* hardware register values */
229 GLuint pp_txformat_x
;
230 GLuint pp_txsize
; /* npot only */
231 GLuint pp_txpitch
; /* npot only */
232 GLuint pp_border_color
;
233 GLuint pp_cubic_faces
; /* cube face 1,2,3,4 log2 sizes */
235 GLuint pp_txfilter_1
; /* r300 */
237 /* r700 texture states */
238 GLuint SQ_TEX_RESOURCE0
;
239 GLuint SQ_TEX_RESOURCE1
;
240 GLuint SQ_TEX_RESOURCE2
;
241 GLuint SQ_TEX_RESOURCE3
;
242 GLuint SQ_TEX_RESOURCE4
;
243 GLuint SQ_TEX_RESOURCE5
;
244 GLuint SQ_TEX_RESOURCE6
;
246 GLuint SQ_TEX_RESOURCE7
;
248 GLuint SQ_TEX_SAMPLER0
;
249 GLuint SQ_TEX_SAMPLER1
;
250 GLuint SQ_TEX_SAMPLER2
;
252 GLuint TD_PS_SAMPLER0_BORDER_RED
;
253 GLuint TD_PS_SAMPLER0_BORDER_GREEN
;
254 GLuint TD_PS_SAMPLER0_BORDER_BLUE
;
255 GLuint TD_PS_SAMPLER0_BORDER_ALPHA
;
257 GLboolean border_fallback
;
262 static INLINE radeonTexObj
* radeon_tex_obj(struct gl_texture_object
*texObj
)
264 return (radeonTexObj
*)texObj
;
267 /* occlusion query */
268 struct radeon_query_object
{
269 struct gl_query_object Base
;
270 struct radeon_bo
*bo
;
272 GLboolean emitted_begin
;
274 /* Double linked list of not flushed query objects */
275 struct radeon_query_object
*prev
, *next
;
278 /* Need refcounting on dma buffers:
280 struct radeon_dma_buffer
{
281 int refcount
; /* the number of retained regions in buf */
286 struct radeon_bo
*bo
; /** Buffer object where vertex data is stored */
287 int offset
; /** Offset into buffer object, in bytes */
288 int components
; /** Number of components per vertex */
289 int stride
; /** Stride in dwords (may be 0 for repeating) */
290 int count
; /** Number of vertices */
293 #define DMA_BO_FREE_TIME 100
295 struct radeon_dma_bo
{
296 struct radeon_dma_bo
*next
, *prev
;
297 struct radeon_bo
*bo
;
302 /* Active dma region. Allocations for vertices and retained
303 * regions come from here. Also used for emitting random vertices,
304 * these may be flushed by calling flush_current();
306 struct radeon_dma_bo free
;
307 struct radeon_dma_bo wait
;
308 struct radeon_dma_bo reserved
;
309 size_t current_used
; /** Number of bytes allocated and forgotten about */
310 size_t current_vertexptr
; /** End of active vertex region */
314 * If current_vertexptr != current_used then flush must be non-zero.
315 * flush must be called before non-active vertex allocations can be
318 void (*flush
) (struct gl_context
*);
323 struct radeon_swtcl_info
{
329 /* Fallback rasterization functions
332 GLenum render_primitive
;
335 struct tnl_attr_map vertex_attrs
[VERT_ATTRIB_MAX
];
336 GLuint vertex_attr_count
;
338 GLuint emit_prediction
;
339 struct radeon_bo
*bo
;
342 #define RADEON_MAX_AOS_ARRAYS 16
343 struct radeon_tcl_info
{
344 struct radeon_aos aos
[RADEON_MAX_AOS_ARRAYS
];
346 struct radeon_bo
*elt_dma_bo
; /** Buffer object that contains element indices */
347 int elt_dma_offset
; /** Offset into this buffer object, in bytes */
350 struct radeon_ioctl
{
351 GLuint vertex_offset
;
353 struct radeon_bo
*bo
;
357 #define RADEON_MAX_PRIMS 64
365 static INLINE GLuint
radeonPackColor(GLuint cpp
,
366 GLubyte r
, GLubyte g
,
367 GLubyte b
, GLubyte a
)
371 return PACK_COLOR_565(r
, g
, b
);
373 return PACK_COLOR_8888(a
, r
, g
, b
);
379 #define MAX_CMD_BUF_SZ (16*1024)
381 #define MAX_DMA_BUF_SZ (64*1024)
383 struct radeon_store
{
386 char cmd_buf
[MAX_CMD_BUF_SZ
];
391 struct radeon_dri_mirror
{
392 __DRIcontext
*context
; /* DRI context */
393 __DRIscreen
*screen
; /* DRI screen */
395 drm_context_t hwContext
;
396 drm_hw_lock_t
*hwLock
;
402 typedef void (*radeon_tri_func
) (radeonContextPtr
,
404 radeonVertex
*, radeonVertex
*);
406 typedef void (*radeon_line_func
) (radeonContextPtr
,
407 radeonVertex
*, radeonVertex
*);
409 typedef void (*radeon_point_func
) (radeonContextPtr
, radeonVertex
*);
411 #define RADEON_MAX_BOS 32
412 struct radeon_state
{
413 struct radeon_colorbuffer_state color
;
414 struct radeon_depthbuffer_state depth
;
415 struct radeon_scissor_state scissor
;
416 struct radeon_stencilbuffer_state stencil
;
420 * This structure holds the command buffer while it is being constructed.
422 * The first batch of commands in the buffer is always the state that needs
423 * to be re-emitted when the context is lost. This batch can be skipped
426 struct radeon_cmdbuf
{
427 struct radeon_cs_manager
*csm
;
428 struct radeon_cs
*cs
;
429 int size
; /** # of dwords total */
430 unsigned int flushing
:1; /** whether we're currently in FlushCmdBufLocked */
433 struct radeon_context
{
434 struct gl_context
*glCtx
;
435 radeonScreenPtr radeonScreen
; /* Screen private DRI data */
437 /* Texture object bookkeeping
440 float initialMaxAnisotropy
;
441 uint32_t texture_row_align
;
442 uint32_t texture_rect_row_align
;
443 uint32_t texture_compressed_row_align
;
445 struct radeon_dma dma
;
446 struct radeon_hw_state hw
;
447 /* Rasterization and vertex state:
452 DECLARE_RENDERINPUTS(tnl_index_bitset
); /* index of bits for last tnl_install_attrs */
454 /* Drawable, cliprect and scissor information */
455 GLuint numClipRects
; /* Cliprects for the draw buffer */
456 drm_clip_rect_t
*pClipRects
;
457 unsigned int lastStamp
;
458 drm_radeon_sarea_t
*sarea
; /* Private SAREA data */
460 /* Mirrors of some DRI state */
461 struct radeon_dri_mirror dri
;
467 drm_radeon_irq_wait_t iw
;
469 /* Derived state - for r300 only */
470 struct radeon_state state
;
472 struct radeon_swtcl_info swtcl
;
473 struct radeon_tcl_info tcl
;
474 /* Configuration cache
476 driOptionCache optionCache
;
478 struct radeon_cmdbuf cmdbuf
;
480 struct radeon_debug debug
;
482 drm_clip_rect_t fboRect
;
483 GLboolean constant_cliprect
; /* use for FBO or DRI2 rendering */
484 GLboolean front_cliprects
;
487 * Set if rendering has occured to the drawable's front buffer.
489 * This is used in the DRI2 case to detect that glFlush should also copy
490 * the contents of the fake front buffer to the real front buffer.
492 GLboolean front_buffer_dirty
;
495 * Track whether front-buffer rendering is currently enabled
497 * A separate flag is used to track this in order to support MRT more
500 GLboolean is_front_buffer_rendering
;
503 * Track whether front-buffer is the current read target.
505 * This is closely associated with is_front_buffer_rendering, but may
506 * be set separately. The DRI2 fake front buffer must be referenced
509 GLboolean is_front_buffer_reading
;
512 struct radeon_query_object
*current
;
513 struct radeon_state_atom queryobj
;
517 void (*get_lock
)(radeonContextPtr radeon
);
518 void (*update_viewport_offset
)(struct gl_context
*ctx
);
519 void (*emit_cs_header
)(struct radeon_cs
*cs
, radeonContextPtr rmesa
);
520 void (*swtcl_flush
)(struct gl_context
*ctx
, uint32_t offset
);
521 void (*pre_emit_atoms
)(radeonContextPtr rmesa
);
522 void (*pre_emit_state
)(radeonContextPtr rmesa
);
523 void (*fallback
)(struct gl_context
*ctx
, GLuint bit
, GLboolean mode
);
524 void (*free_context
)(struct gl_context
*ctx
);
525 void (*emit_query_finish
)(radeonContextPtr radeon
);
526 void (*update_scissor
)(struct gl_context
*ctx
);
527 unsigned (*check_blit
)(gl_format mesa_format
);
528 unsigned (*blit
)(struct gl_context
*ctx
,
529 struct radeon_bo
*src_bo
,
531 gl_format src_mesaformat
,
535 unsigned src_x_offset
,
536 unsigned src_y_offset
,
537 struct radeon_bo
*dst_bo
,
539 gl_format dst_mesaformat
,
543 unsigned dst_x_offset
,
544 unsigned dst_y_offset
,
548 unsigned (*is_format_renderable
)(gl_format mesa_format
);
552 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
554 static inline __DRIdrawable
* radeon_get_drawable(radeonContextPtr radeon
)
556 return radeon
->dri
.context
->driDrawablePriv
;
559 static inline __DRIdrawable
* radeon_get_readable(radeonContextPtr radeon
)
561 return radeon
->dri
.context
->driReadablePriv
;
565 * This function takes a float and packs it into a uint32_t
567 static INLINE
uint32_t radeonPackFloat32(float fl
)
578 /* This is probably wrong for some values, I need to test this
579 * some more. Range checking would be a good idea also..
581 * But it works for most things. I'll fix it later if someone
582 * else with a better clue doesn't
584 static INLINE
uint32_t radeonPackFloat24(float f
)
588 uint32_t float24
= 0;
593 mantissa
= frexpf(f
, &exponent
);
597 float24
|= (1 << 23);
598 mantissa
= mantissa
* -1.0;
600 /* Handle exponent, bias of 63 */
602 float24
|= (exponent
<< 16);
603 /* Kill 7 LSB of mantissa */
604 float24
|= (radeonPackFloat32(mantissa
) & 0x7FFFFF) >> 7;
609 GLboolean
radeonInitContext(radeonContextPtr radeon
,
610 struct dd_function_table
* functions
,
611 const struct gl_config
* glVisual
,
612 __DRIcontext
* driContextPriv
,
613 void *sharedContextPrivate
);
615 void radeonCleanupContext(radeonContextPtr radeon
);
616 GLboolean
radeonUnbindContext(__DRIcontext
* driContextPriv
);
617 void radeon_update_renderbuffers(__DRIcontext
*context
, __DRIdrawable
*drawable
,
618 GLboolean front_only
);
619 GLboolean
radeonMakeCurrent(__DRIcontext
* driContextPriv
,
620 __DRIdrawable
* driDrawPriv
,
621 __DRIdrawable
* driReadPriv
);
622 extern void radeonDestroyContext(__DRIcontext
* driContextPriv
);
623 void radeon_prepare_render(radeonContextPtr radeon
);