2 #ifndef COMMON_CONTEXT_H
3 #define COMMON_CONTEXT_H
6 #include "math/m_vector.h"
8 #include "tnl/t_context.h"
9 #include "main/colormac.h"
11 #include "radeon_debug.h"
12 #include "radeon_screen.h"
13 #include "radeon_drm.h"
15 #include "tnl/t_vertex.h"
17 #include "dri_metaops.h"
18 struct radeon_context
;
20 #include "radeon_bocs_wrapper.h"
22 /* This union is used to avoid warnings/miscompilation
23 with float to uint32_t casts due to strict-aliasing */
24 typedef union { GLfloat f
; uint32_t ui32
; } float_ui32_type
;
26 struct radeon_context
;
27 typedef struct radeon_context radeonContextRec
;
28 typedef struct radeon_context
*radeonContextPtr
;
38 /* Rasterizing fallbacks */
39 /* See correponding strings in r200_swtcl.c */
40 #define RADEON_FALLBACK_TEXTURE 0x0001
41 #define RADEON_FALLBACK_DRAW_BUFFER 0x0002
42 #define RADEON_FALLBACK_STENCIL 0x0004
43 #define RADEON_FALLBACK_RENDER_MODE 0x0008
44 #define RADEON_FALLBACK_BLEND_EQ 0x0010
45 #define RADEON_FALLBACK_BLEND_FUNC 0x0020
46 #define RADEON_FALLBACK_DISABLE 0x0040
47 #define RADEON_FALLBACK_BORDER_MODE 0x0080
48 #define RADEON_FALLBACK_DEPTH_BUFFER 0x0100
49 #define RADEON_FALLBACK_STENCIL_BUFFER 0x0200
51 #define R200_FALLBACK_TEXTURE 0x01
52 #define R200_FALLBACK_DRAW_BUFFER 0x02
53 #define R200_FALLBACK_STENCIL 0x04
54 #define R200_FALLBACK_RENDER_MODE 0x08
55 #define R200_FALLBACK_DISABLE 0x10
56 #define R200_FALLBACK_BORDER_MODE 0x20
58 #define RADEON_TCL_FALLBACK_RASTER 0x1 /* rasterization */
59 #define RADEON_TCL_FALLBACK_UNFILLED 0x2 /* unfilled tris */
60 #define RADEON_TCL_FALLBACK_LIGHT_TWOSIDE 0x4 /* twoside tris */
61 #define RADEON_TCL_FALLBACK_MATERIAL 0x8 /* material in vb */
62 #define RADEON_TCL_FALLBACK_TEXGEN_0 0x10 /* texgen, unit 0 */
63 #define RADEON_TCL_FALLBACK_TEXGEN_1 0x20 /* texgen, unit 1 */
64 #define RADEON_TCL_FALLBACK_TEXGEN_2 0x40 /* texgen, unit 2 */
65 #define RADEON_TCL_FALLBACK_TCL_DISABLE 0x80 /* user disable */
66 #define RADEON_TCL_FALLBACK_FOGCOORDSPEC 0x100 /* fogcoord, sep. spec light */
68 /* The blit width for texture uploads
70 #define BLIT_WIDTH_BYTES 1024
72 /* Use the templated vertex format:
75 #define TAG(x) radeon##x
76 #include "tnl_dd/t_dd_vertex.h"
79 #define RADEON_RB_CLASS 0xdeadbeef
81 struct radeon_renderbuffer
83 struct gl_renderbuffer base
;
86 /* unsigned int offset; */
89 uint32_t draw_offset
; /* FBO */
90 /* boo Xorg 6.8.2 compat */
93 GLuint pf_pending
; /**< sequence number of pending flip */
94 GLuint vbl_pending
; /**< vblank sequence number of pending flip */
95 __DRIdrawablePrivate
*dPriv
;
98 struct radeon_framebuffer
100 struct gl_framebuffer base
;
102 struct radeon_renderbuffer
*color_rb
[2];
108 int64_t swap_missed_ust
;
111 GLuint swap_missed_count
;
113 /* Drawable page flipping state */
115 GLint pf_current_page
;
121 struct radeon_colorbuffer_state
{
124 struct gl_renderbuffer
*rb
;
125 uint32_t draw_offset
; /* offset into color renderbuffer - FBOs */
128 struct radeon_depthbuffer_state
{
130 struct gl_renderbuffer
*rb
;
133 struct radeon_scissor_state
{
134 drm_clip_rect_t rect
;
137 GLuint numClipRects
; /* Cliprects active */
138 GLuint numAllocedClipRects
; /* Cliprects available */
139 drm_clip_rect_t
*pClipRects
;
142 struct radeon_stencilbuffer_state
{
143 GLuint clear
; /* rb3d_stencilrefmask value */
146 struct radeon_state_atom
{
147 struct radeon_state_atom
*next
, *prev
;
148 const char *name
; /* for debug */
149 int cmd_size
; /* size in bytes */
152 GLuint
*cmd
; /* one or more cmd's */
153 GLuint
*lastcmd
; /* one or more cmd's */
154 GLboolean dirty
; /* dirty-mark in emit_state_list */
155 int (*check
) (GLcontext
*, struct radeon_state_atom
*atom
); /* is this state active? */
156 void (*emit
) (GLcontext
*, struct radeon_state_atom
*atom
);
159 struct radeon_hw_state
{
160 /* Head of the linked list of state atoms. */
161 struct radeon_state_atom atomlist
;
162 int max_state_size
; /* Number of bytes necessary for a full state emit. */
163 int max_post_flush_size
; /* Number of bytes necessary for post flushing emits */
164 GLboolean is_dirty
, all_dirty
;
168 /* Texture related */
169 typedef struct _radeon_texture_image radeon_texture_image
;
171 struct _radeon_texture_image
{
172 struct gl_texture_image base
;
175 * If mt != 0, the image is stored in hardware format in the
176 * given mipmap tree. In this case, base.Data may point into the
177 * mapping of the buffer object that contains the mipmap tree.
179 * If mt == 0, the image is stored in normal memory pointed to
182 struct _radeon_mipmap_tree
*mt
;
183 struct radeon_bo
*bo
;
185 int mtlevel
; /** if mt != 0, this is the image's level in the mipmap tree */
186 int mtface
; /** if mt != 0, this is the image's face in the mipmap tree */
190 static INLINE radeon_texture_image
*get_radeon_texture_image(struct gl_texture_image
*image
)
192 return (radeon_texture_image
*)image
;
196 typedef struct radeon_tex_obj radeonTexObj
, *radeonTexObjPtr
;
198 #define RADEON_TXO_MICRO_TILE (1 << 3)
200 /* Texture object in locally shared texture space.
202 struct radeon_tex_obj
{
203 struct gl_texture_object base
;
204 struct _radeon_mipmap_tree
*mt
;
207 * This is true if we've verified that the mipmap tree above is complete
212 GLuint override_offset
;
213 GLboolean image_override
; /* Image overridden by GLX_EXT_tfp */
214 GLuint tile_bits
; /* hw texture tile bits used on this texture */
215 struct radeon_bo
*bo
;
217 GLuint pp_txfilter
; /* hardware register values */
219 GLuint pp_txformat_x
;
220 GLuint pp_txsize
; /* npot only */
221 GLuint pp_txpitch
; /* npot only */
222 GLuint pp_border_color
;
223 GLuint pp_cubic_faces
; /* cube face 1,2,3,4 log2 sizes */
225 GLuint pp_txfilter_1
; /* r300 */
227 /* r700 texture states */
228 GLuint SQ_TEX_RESOURCE0
;
229 GLuint SQ_TEX_RESOURCE1
;
230 GLuint SQ_TEX_RESOURCE2
;
231 GLuint SQ_TEX_RESOURCE3
;
232 GLuint SQ_TEX_RESOURCE4
;
233 GLuint SQ_TEX_RESOURCE5
;
234 GLuint SQ_TEX_RESOURCE6
;
236 GLuint SQ_TEX_SAMPLER0
;
237 GLuint SQ_TEX_SAMPLER1
;
238 GLuint SQ_TEX_SAMPLER2
;
240 GLuint TD_PS_SAMPLER0_BORDER_RED
;
241 GLuint TD_PS_SAMPLER0_BORDER_GREEN
;
242 GLuint TD_PS_SAMPLER0_BORDER_BLUE
;
243 GLuint TD_PS_SAMPLER0_BORDER_ALPHA
;
245 GLboolean border_fallback
;
250 static INLINE radeonTexObj
* radeon_tex_obj(struct gl_texture_object
*texObj
)
252 return (radeonTexObj
*)texObj
;
255 /* occlusion query */
256 struct radeon_query_object
{
257 struct gl_query_object Base
;
258 struct radeon_bo
*bo
;
260 GLboolean emitted_begin
;
262 /* Double linked list of not flushed query objects */
263 struct radeon_query_object
*prev
, *next
;
266 /* Need refcounting on dma buffers:
268 struct radeon_dma_buffer
{
269 int refcount
; /* the number of retained regions in buf */
274 struct radeon_bo
*bo
; /** Buffer object where vertex data is stored */
275 int offset
; /** Offset into buffer object, in bytes */
276 int components
; /** Number of components per vertex */
277 int stride
; /** Stride in dwords (may be 0 for repeating) */
278 int count
; /** Number of vertices */
281 #define DMA_BO_FREE_TIME 100
283 struct radeon_dma_bo
{
284 struct radeon_dma_bo
*next
, *prev
;
285 struct radeon_bo
*bo
;
290 /* Active dma region. Allocations for vertices and retained
291 * regions come from here. Also used for emitting random vertices,
292 * these may be flushed by calling flush_current();
294 struct radeon_dma_bo free
;
295 struct radeon_dma_bo wait
;
296 struct radeon_dma_bo reserved
;
297 size_t current_used
; /** Number of bytes allocated and forgotten about */
298 size_t current_vertexptr
; /** End of active vertex region */
302 * If current_vertexptr != current_used then flush must be non-zero.
303 * flush must be called before non-active vertex allocations can be
306 void (*flush
) (GLcontext
*);
311 struct radeon_swtcl_info
{
317 /* Fallback rasterization functions
320 GLenum render_primitive
;
323 struct tnl_attr_map vertex_attrs
[VERT_ATTRIB_MAX
];
324 GLuint vertex_attr_count
;
326 GLuint emit_prediction
;
329 #define RADEON_MAX_AOS_ARRAYS 16
330 struct radeon_tcl_info
{
331 struct radeon_aos aos
[RADEON_MAX_AOS_ARRAYS
];
333 struct radeon_bo
*elt_dma_bo
; /** Buffer object that contains element indices */
334 int elt_dma_offset
; /** Offset into this buffer object, in bytes */
337 struct radeon_ioctl
{
338 GLuint vertex_offset
;
340 struct radeon_bo
*bo
;
344 #define RADEON_MAX_PRIMS 64
352 static INLINE GLuint
radeonPackColor(GLuint cpp
,
353 GLubyte r
, GLubyte g
,
354 GLubyte b
, GLubyte a
)
358 return PACK_COLOR_565(r
, g
, b
);
360 return PACK_COLOR_8888(a
, r
, g
, b
);
366 #define MAX_CMD_BUF_SZ (16*1024)
368 #define MAX_DMA_BUF_SZ (64*1024)
370 struct radeon_store
{
373 char cmd_buf
[MAX_CMD_BUF_SZ
];
378 struct radeon_dri_mirror
{
379 __DRIcontextPrivate
*context
; /* DRI context */
380 __DRIscreenPrivate
*screen
; /* DRI screen */
382 drm_context_t hwContext
;
383 drm_hw_lock_t
*hwLock
;
389 typedef void (*radeon_tri_func
) (radeonContextPtr
,
391 radeonVertex
*, radeonVertex
*);
393 typedef void (*radeon_line_func
) (radeonContextPtr
,
394 radeonVertex
*, radeonVertex
*);
396 typedef void (*radeon_point_func
) (radeonContextPtr
, radeonVertex
*);
398 #define RADEON_MAX_BOS 32
399 struct radeon_state
{
400 struct radeon_colorbuffer_state color
;
401 struct radeon_depthbuffer_state depth
;
402 struct radeon_scissor_state scissor
;
403 struct radeon_stencilbuffer_state stencil
;
405 struct radeon_cs_space_check bos
[RADEON_MAX_BOS
];
406 int validated_bo_count
;
410 * This structure holds the command buffer while it is being constructed.
412 * The first batch of commands in the buffer is always the state that needs
413 * to be re-emitted when the context is lost. This batch can be skipped
416 struct radeon_cmdbuf
{
417 struct radeon_cs_manager
*csm
;
418 struct radeon_cs
*cs
;
419 int size
; /** # of dwords total */
420 unsigned int flushing
:1; /** whether we're currently in FlushCmdBufLocked */
423 struct radeon_context
{
425 radeonScreenPtr radeonScreen
; /* Screen private DRI data */
427 /* Texture object bookkeeping
430 float initialMaxAnisotropy
;
431 uint32_t texture_row_align
;
432 uint32_t texture_rect_row_align
;
433 uint32_t texture_compressed_row_align
;
435 struct radeon_dma dma
;
436 struct radeon_hw_state hw
;
437 /* Rasterization and vertex state:
442 DECLARE_RENDERINPUTS(tnl_index_bitset
); /* index of bits for last tnl_install_attrs */
444 /* Drawable, cliprect and scissor information */
445 GLuint numClipRects
; /* Cliprects for the draw buffer */
446 drm_clip_rect_t
*pClipRects
;
447 unsigned int lastStamp
;
448 drm_radeon_sarea_t
*sarea
; /* Private SAREA data */
450 /* Mirrors of some DRI state */
451 struct radeon_dri_mirror dri
;
457 drm_radeon_irq_wait_t iw
;
459 /* Derived state - for r300 only */
460 struct radeon_state state
;
462 struct radeon_swtcl_info swtcl
;
463 struct radeon_tcl_info tcl
;
464 /* Configuration cache
466 driOptionCache optionCache
;
468 struct radeon_cmdbuf cmdbuf
;
470 struct radeon_debug debug
;
472 drm_clip_rect_t fboRect
;
473 GLboolean constant_cliprect
; /* use for FBO or DRI2 rendering */
474 GLboolean front_cliprects
;
477 * Set if rendering has occured to the drawable's front buffer.
479 * This is used in the DRI2 case to detect that glFlush should also copy
480 * the contents of the fake front buffer to the real front buffer.
482 GLboolean front_buffer_dirty
;
485 * Track whether front-buffer rendering is currently enabled
487 * A separate flag is used to track this in order to support MRT more
490 GLboolean is_front_buffer_rendering
;
493 * Track whether front-buffer is the current read target.
495 * This is closely associated with is_front_buffer_rendering, but may
496 * be set separately. The DRI2 fake front buffer must be referenced
499 GLboolean is_front_buffer_reading
;
501 struct dri_metaops meta
;
504 struct radeon_query_object
*current
;
505 struct radeon_query_object not_flushed_head
;
506 struct radeon_state_atom queryobj
;
510 void (*get_lock
)(radeonContextPtr radeon
);
511 void (*update_viewport_offset
)(GLcontext
*ctx
);
512 void (*emit_cs_header
)(struct radeon_cs
*cs
, radeonContextPtr rmesa
);
513 void (*swtcl_flush
)(GLcontext
*ctx
, uint32_t offset
);
514 void (*pre_emit_atoms
)(radeonContextPtr rmesa
);
515 void (*pre_emit_state
)(radeonContextPtr rmesa
);
516 void (*fallback
)(GLcontext
*ctx
, GLuint bit
, GLboolean mode
);
517 void (*free_context
)(GLcontext
*ctx
);
518 void (*emit_query_finish
)(radeonContextPtr radeon
);
519 void (*update_scissor
)(GLcontext
*ctx
);
523 #define RADEON_CONTEXT(glctx) ((radeonContextPtr)(ctx->DriverCtx))
525 static inline __DRIdrawablePrivate
* radeon_get_drawable(radeonContextPtr radeon
)
527 return radeon
->dri
.context
->driDrawablePriv
;
530 static inline __DRIdrawablePrivate
* radeon_get_readable(radeonContextPtr radeon
)
532 return radeon
->dri
.context
->driReadablePriv
;
536 * This function takes a float and packs it into a uint32_t
538 static INLINE
uint32_t radeonPackFloat32(float fl
)
549 /* This is probably wrong for some values, I need to test this
550 * some more. Range checking would be a good idea also..
552 * But it works for most things. I'll fix it later if someone
553 * else with a better clue doesn't
555 static INLINE
uint32_t radeonPackFloat24(float f
)
559 uint32_t float24
= 0;
564 mantissa
= frexpf(f
, &exponent
);
568 float24
|= (1 << 23);
569 mantissa
= mantissa
* -1.0;
571 /* Handle exponent, bias of 63 */
573 float24
|= (exponent
<< 16);
574 /* Kill 7 LSB of mantissa */
575 float24
|= (radeonPackFloat32(mantissa
) & 0x7FFFFF) >> 7;
580 GLboolean
radeonInitContext(radeonContextPtr radeon
,
581 struct dd_function_table
* functions
,
582 const __GLcontextModes
* glVisual
,
583 __DRIcontextPrivate
* driContextPriv
,
584 void *sharedContextPrivate
);
586 void radeonCleanupContext(radeonContextPtr radeon
);
587 GLboolean
radeonUnbindContext(__DRIcontextPrivate
* driContextPriv
);
588 void radeon_update_renderbuffers(__DRIcontext
*context
, __DRIdrawable
*drawable
);
589 GLboolean
radeonMakeCurrent(__DRIcontextPrivate
* driContextPriv
,
590 __DRIdrawablePrivate
* driDrawPriv
,
591 __DRIdrawablePrivate
* driReadPriv
);
592 extern void radeonDestroyContext(__DRIcontextPrivate
* driContextPriv
);