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Merge remote branch 'origin/mesa_7_7_branch'
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_cs_legacy.c
1 /*
2 * Copyright © 2008 Nicolai Haehnle
3 * Copyright © 2008 Jérôme Glisse
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26 /*
27 * Authors:
28 * Aapo Tahkola <aet@rasterburn.org>
29 * Nicolai Haehnle <prefect_@gmx.net>
30 * Jérôme Glisse <glisse@freedesktop.org>
31 */
32 #include <errno.h>
33
34 #include "radeon_bocs_wrapper.h"
35 #include "radeon_common.h"
36
37 struct cs_manager_legacy {
38 struct radeon_cs_manager base;
39 struct radeon_context *ctx;
40 /* hack for scratch stuff */
41 uint32_t pending_age;
42 uint32_t pending_count;
43
44
45 };
46
47 struct cs_reloc_legacy {
48 struct radeon_cs_reloc base;
49 uint32_t cindices;
50 uint32_t *indices;
51 };
52
53
54 static struct radeon_cs *cs_create(struct radeon_cs_manager *csm,
55 uint32_t ndw)
56 {
57 struct radeon_cs *cs;
58
59 cs = (struct radeon_cs*)calloc(1, sizeof(struct radeon_cs));
60 if (cs == NULL) {
61 return NULL;
62 }
63 cs->csm = csm;
64 cs->ndw = (ndw + 0x3FF) & (~0x3FF);
65 cs->packets = (uint32_t*)malloc(4*cs->ndw);
66 if (cs->packets == NULL) {
67 free(cs);
68 return NULL;
69 }
70 cs->relocs_total_size = 0;
71 return cs;
72 }
73
74 static int cs_write_reloc(struct radeon_cs *cs,
75 struct radeon_bo *bo,
76 uint32_t read_domain,
77 uint32_t write_domain,
78 uint32_t flags)
79 {
80 struct cs_reloc_legacy *relocs;
81 int i;
82
83 relocs = (struct cs_reloc_legacy *)cs->relocs;
84 /* check domains */
85 if ((read_domain && write_domain) || (!read_domain && !write_domain)) {
86 /* in one CS a bo can only be in read or write domain but not
87 * in read & write domain at the same sime
88 */
89 return -EINVAL;
90 }
91 if (read_domain == RADEON_GEM_DOMAIN_CPU) {
92 return -EINVAL;
93 }
94 if (write_domain == RADEON_GEM_DOMAIN_CPU) {
95 return -EINVAL;
96 }
97 /* check if bo is already referenced */
98 for(i = 0; i < cs->crelocs; i++) {
99 uint32_t *indices;
100
101 if (relocs[i].base.bo->handle == bo->handle) {
102 /* Check domains must be in read or write. As we check already
103 * checked that in argument one of the read or write domain was
104 * set we only need to check that if previous reloc as the read
105 * domain set then the read_domain should also be set for this
106 * new relocation.
107 */
108 if (relocs[i].base.read_domain && !read_domain) {
109 return -EINVAL;
110 }
111 if (relocs[i].base.write_domain && !write_domain) {
112 return -EINVAL;
113 }
114 relocs[i].base.read_domain |= read_domain;
115 relocs[i].base.write_domain |= write_domain;
116 /* save indice */
117 relocs[i].cindices++;
118 indices = (uint32_t*)realloc(relocs[i].indices,
119 relocs[i].cindices * 4);
120 if (indices == NULL) {
121 relocs[i].cindices -= 1;
122 return -ENOMEM;
123 }
124 relocs[i].indices = indices;
125 relocs[i].indices[relocs[i].cindices - 1] = cs->cdw - 1;
126 return 0;
127 }
128 }
129 /* add bo to reloc */
130 relocs = (struct cs_reloc_legacy*)
131 realloc(cs->relocs,
132 sizeof(struct cs_reloc_legacy) * (cs->crelocs + 1));
133 if (relocs == NULL) {
134 return -ENOMEM;
135 }
136 cs->relocs = relocs;
137 relocs[cs->crelocs].base.bo = bo;
138 relocs[cs->crelocs].base.read_domain = read_domain;
139 relocs[cs->crelocs].base.write_domain = write_domain;
140 relocs[cs->crelocs].base.flags = flags;
141 relocs[cs->crelocs].indices = (uint32_t*)malloc(4);
142 if (relocs[cs->crelocs].indices == NULL) {
143 return -ENOMEM;
144 }
145 relocs[cs->crelocs].indices[0] = cs->cdw - 1;
146 relocs[cs->crelocs].cindices = 1;
147 cs->relocs_total_size += radeon_bo_legacy_relocs_size(bo);
148 cs->crelocs++;
149 radeon_bo_ref(bo);
150 return 0;
151 }
152
153 static int cs_begin(struct radeon_cs *cs,
154 uint32_t ndw,
155 const char *file,
156 const char *func,
157 int line)
158 {
159 if (cs->section) {
160 fprintf(stderr, "CS already in a section(%s,%s,%d)\n",
161 cs->section_file, cs->section_func, cs->section_line);
162 fprintf(stderr, "CS can't start section(%s,%s,%d)\n",
163 file, func, line);
164 return -EPIPE;
165 }
166 cs->section = 1;
167 cs->section_ndw = ndw;
168 cs->section_cdw = 0;
169 cs->section_file = file;
170 cs->section_func = func;
171 cs->section_line = line;
172
173
174 if (cs->cdw + ndw > cs->ndw) {
175 uint32_t tmp, *ptr;
176 int num = (ndw > 0x3FF) ? ndw : 0x3FF;
177
178 tmp = (cs->cdw + 1 + num) & (~num);
179 ptr = (uint32_t*)realloc(cs->packets, 4 * tmp);
180 if (ptr == NULL) {
181 return -ENOMEM;
182 }
183 cs->packets = ptr;
184 cs->ndw = tmp;
185 }
186
187 return 0;
188 }
189
190 static int cs_end(struct radeon_cs *cs,
191 const char *file,
192 const char *func,
193 int line)
194
195 {
196 if (!cs->section) {
197 fprintf(stderr, "CS no section to end at (%s,%s,%d)\n",
198 file, func, line);
199 return -EPIPE;
200 }
201 cs->section = 0;
202 if (cs->section_ndw != cs->section_cdw) {
203 fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n",
204 cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw);
205 fprintf(stderr, "CS section end at (%s,%s,%d)\n",
206 file, func, line);
207 return -EPIPE;
208 }
209 return 0;
210 }
211
212 static int cs_process_relocs(struct radeon_cs *cs)
213 {
214 struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm;
215 struct cs_reloc_legacy *relocs;
216 int i, j, r;
217
218 csm = (struct cs_manager_legacy*)cs->csm;
219 relocs = (struct cs_reloc_legacy *)cs->relocs;
220 restart:
221 for (i = 0; i < cs->crelocs; i++)
222 {
223 for (j = 0; j < relocs[i].cindices; j++)
224 {
225 uint32_t soffset, eoffset;
226
227 r = radeon_bo_legacy_validate(relocs[i].base.bo,
228 &soffset, &eoffset);
229 if (r == -EAGAIN)
230 {
231 goto restart;
232 }
233 if (r)
234 {
235 fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
236 relocs[i].base.bo, soffset, eoffset);
237 return r;
238 }
239 cs->packets[relocs[i].indices[j]] += soffset;
240 if (cs->packets[relocs[i].indices[j]] >= eoffset)
241 {
242 /* radeon_bo_debug(relocs[i].base.bo, 12); */
243 fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
244 relocs[i].base.bo, soffset, eoffset);
245 fprintf(stderr, "above end: %p 0x%08X 0x%08X\n",
246 relocs[i].base.bo,
247 cs->packets[relocs[i].indices[j]],
248 eoffset);
249 exit(0);
250 return -EINVAL;
251 }
252 }
253 }
254 return 0;
255 }
256
257 static int cs_set_age(struct radeon_cs *cs)
258 {
259 struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm;
260 struct cs_reloc_legacy *relocs;
261 int i;
262
263 relocs = (struct cs_reloc_legacy *)cs->relocs;
264 for (i = 0; i < cs->crelocs; i++) {
265 radeon_bo_legacy_pending(relocs[i].base.bo, csm->pending_age);
266 radeon_bo_unref(relocs[i].base.bo);
267 }
268 return 0;
269 }
270
271 static int cs_emit(struct radeon_cs *cs)
272 {
273 struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm;
274 drm_radeon_cmd_buffer_t cmd;
275 drm_r300_cmd_header_t age;
276 uint64_t ull;
277 int r;
278
279 csm->ctx->vtbl.emit_cs_header(cs, csm->ctx);
280
281 /* append buffer age */
282 if ( IS_R300_CLASS(csm->ctx->radeonScreen) )
283 {
284 age.scratch.cmd_type = R300_CMD_SCRATCH;
285 /* Scratch register 2 corresponds to what radeonGetAge polls */
286 csm->pending_age = 0;
287 csm->pending_count = 1;
288 ull = (uint64_t) (intptr_t) &csm->pending_age;
289 age.scratch.reg = 2;
290 age.scratch.n_bufs = 1;
291 age.scratch.flags = 0;
292 radeon_cs_write_dword(cs, age.u);
293 radeon_cs_write_qword(cs, ull);
294 radeon_cs_write_dword(cs, 0);
295 }
296
297 r = cs_process_relocs(cs);
298 if (r) {
299 return 0;
300 }
301
302 cmd.buf = (char *)cs->packets;
303 cmd.bufsz = cs->cdw * 4;
304 if (csm->ctx->state.scissor.enabled) {
305 cmd.nbox = csm->ctx->state.scissor.numClipRects;
306 cmd.boxes = (drm_clip_rect_t *) csm->ctx->state.scissor.pClipRects;
307 } else {
308 cmd.nbox = csm->ctx->numClipRects;
309 cmd.boxes = (drm_clip_rect_t *) csm->ctx->pClipRects;
310 }
311
312 //dump_cmdbuf(cs);
313
314 r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd));
315 if (r) {
316 return r;
317 }
318 if ((!IS_R300_CLASS(csm->ctx->radeonScreen)) &&
319 (!IS_R600_CLASS(csm->ctx->radeonScreen))) { /* +r6/r7 : No irq for r6/r7 yet. */
320 drm_radeon_irq_emit_t emit_cmd;
321 emit_cmd.irq_seq = (int*)&csm->pending_age;
322 r = drmCommandWrite(cs->csm->fd, DRM_RADEON_IRQ_EMIT, &emit_cmd, sizeof(emit_cmd));
323 if (r) {
324 return r;
325 }
326 }
327 cs_set_age(cs);
328
329 cs->csm->read_used = 0;
330 cs->csm->vram_write_used = 0;
331 cs->csm->gart_write_used = 0;
332 return 0;
333 }
334
335 static void inline cs_free_reloc(void *relocs_p, int crelocs)
336 {
337 struct cs_reloc_legacy *relocs = relocs_p;
338 int i;
339 if (!relocs_p)
340 return;
341 for (i = 0; i < crelocs; i++)
342 free(relocs[i].indices);
343 }
344
345 static int cs_destroy(struct radeon_cs *cs)
346 {
347 cs_free_reloc(cs->relocs, cs->crelocs);
348 free(cs->relocs);
349 free(cs->packets);
350 free(cs);
351 return 0;
352 }
353
354 static int cs_erase(struct radeon_cs *cs)
355 {
356 cs_free_reloc(cs->relocs, cs->crelocs);
357 free(cs->relocs);
358 cs->relocs_total_size = 0;
359 cs->relocs = NULL;
360 cs->crelocs = 0;
361 cs->cdw = 0;
362 cs->section = 0;
363 return 0;
364 }
365
366 static int cs_need_flush(struct radeon_cs *cs)
367 {
368 /* this function used to flush when the BO usage got to
369 * a certain size, now the higher levels handle this better */
370 return 0;
371 }
372
373 static void cs_print(struct radeon_cs *cs, FILE *file)
374 {
375 }
376
377 static struct radeon_cs_funcs radeon_cs_legacy_funcs = {
378 cs_create,
379 cs_write_reloc,
380 cs_begin,
381 cs_end,
382 cs_emit,
383 cs_destroy,
384 cs_erase,
385 cs_need_flush,
386 cs_print,
387 };
388
389 struct radeon_cs_manager *radeon_cs_manager_legacy_ctor(struct radeon_context *ctx)
390 {
391 struct cs_manager_legacy *csm;
392
393 csm = (struct cs_manager_legacy*)
394 calloc(1, sizeof(struct cs_manager_legacy));
395 if (csm == NULL) {
396 return NULL;
397 }
398 csm->base.funcs = &radeon_cs_legacy_funcs;
399 csm->base.fd = ctx->dri.fd;
400 csm->ctx = ctx;
401 csm->pending_age = 1;
402 return (struct radeon_cs_manager*)csm;
403 }
404
405 void radeon_cs_manager_legacy_dtor(struct radeon_cs_manager *csm)
406 {
407 free(csm);
408 }
409