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make: Remove duplicate occurence of driverfuncs.c
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_cs_legacy.c
1 /*
2 * Copyright © 2008 Nicolai Haehnle
3 * Copyright © 2008 Jérôme Glisse
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26 /*
27 * Authors:
28 * Aapo Tahkola <aet@rasterburn.org>
29 * Nicolai Haehnle <prefect_@gmx.net>
30 * Jérôme Glisse <glisse@freedesktop.org>
31 */
32 #include <errno.h>
33 #include <unistd.h>
34 #include <stdint.h>
35 #include "drm.h"
36 #include "radeon_drm.h"
37
38 #include "radeon_bocs_wrapper.h"
39 #include "radeon_common.h"
40 #ifdef HAVE_LIBDRM_RADEON
41 #include "radeon_cs_int.h"
42 #else
43 #include "radeon_cs_int_drm.h"
44 #endif
45 struct cs_manager_legacy {
46 struct radeon_cs_manager base;
47 struct radeon_context *ctx;
48 /* hack for scratch stuff */
49 uint32_t pending_age;
50 uint32_t pending_count;
51
52
53 };
54
55 struct cs_reloc_legacy {
56 struct radeon_cs_reloc base;
57 uint32_t cindices;
58 uint32_t *indices;
59 };
60
61
62 static struct radeon_cs_int *cs_create(struct radeon_cs_manager *csm,
63 uint32_t ndw)
64 {
65 struct radeon_cs_int *csi;
66
67 csi = (struct radeon_cs_int*)calloc(1, sizeof(struct radeon_cs_int));
68 if (csi == NULL) {
69 return NULL;
70 }
71 csi->csm = csm;
72 csi->ndw = (ndw + 0x3FF) & (~0x3FF);
73 csi->packets = (uint32_t*)malloc(4*csi->ndw);
74 if (csi->packets == NULL) {
75 free(csi);
76 return NULL;
77 }
78 csi->relocs_total_size = 0;
79 return csi;
80 }
81
82 static int cs_write_reloc(struct radeon_cs_int *cs,
83 struct radeon_bo *bo,
84 uint32_t read_domain,
85 uint32_t write_domain,
86 uint32_t flags)
87 {
88 struct cs_reloc_legacy *relocs;
89 int i;
90
91 relocs = (struct cs_reloc_legacy *)cs->relocs;
92 /* check domains */
93 if ((read_domain && write_domain) || (!read_domain && !write_domain)) {
94 /* in one CS a bo can only be in read or write domain but not
95 * in read & write domain at the same sime
96 */
97 return -EINVAL;
98 }
99 if (read_domain == RADEON_GEM_DOMAIN_CPU) {
100 return -EINVAL;
101 }
102 if (write_domain == RADEON_GEM_DOMAIN_CPU) {
103 return -EINVAL;
104 }
105 /* check if bo is already referenced */
106 for(i = 0; i < cs->crelocs; i++) {
107 uint32_t *indices;
108
109 if (relocs[i].base.bo->handle == bo->handle) {
110 /* Check domains must be in read or write. As we check already
111 * checked that in argument one of the read or write domain was
112 * set we only need to check that if previous reloc as the read
113 * domain set then the read_domain should also be set for this
114 * new relocation.
115 */
116 if (relocs[i].base.read_domain && !read_domain) {
117 return -EINVAL;
118 }
119 if (relocs[i].base.write_domain && !write_domain) {
120 return -EINVAL;
121 }
122 relocs[i].base.read_domain |= read_domain;
123 relocs[i].base.write_domain |= write_domain;
124 /* save indice */
125 relocs[i].cindices++;
126 indices = (uint32_t*)realloc(relocs[i].indices,
127 relocs[i].cindices * 4);
128 if (indices == NULL) {
129 relocs[i].cindices -= 1;
130 return -ENOMEM;
131 }
132 relocs[i].indices = indices;
133 relocs[i].indices[relocs[i].cindices - 1] = cs->cdw - 1;
134 return 0;
135 }
136 }
137 /* add bo to reloc */
138 relocs = (struct cs_reloc_legacy*)
139 realloc(cs->relocs,
140 sizeof(struct cs_reloc_legacy) * (cs->crelocs + 1));
141 if (relocs == NULL) {
142 return -ENOMEM;
143 }
144 cs->relocs = relocs;
145 relocs[cs->crelocs].base.bo = bo;
146 relocs[cs->crelocs].base.read_domain = read_domain;
147 relocs[cs->crelocs].base.write_domain = write_domain;
148 relocs[cs->crelocs].base.flags = flags;
149 relocs[cs->crelocs].indices = (uint32_t*)malloc(4);
150 if (relocs[cs->crelocs].indices == NULL) {
151 return -ENOMEM;
152 }
153 relocs[cs->crelocs].indices[0] = cs->cdw - 1;
154 relocs[cs->crelocs].cindices = 1;
155 cs->relocs_total_size += radeon_bo_legacy_relocs_size(bo);
156 cs->crelocs++;
157 radeon_bo_ref(bo);
158 return 0;
159 }
160
161 static int cs_begin(struct radeon_cs_int *cs,
162 uint32_t ndw,
163 const char *file,
164 const char *func,
165 int line)
166 {
167 if (cs->section_ndw) {
168 fprintf(stderr, "CS already in a section(%s,%s,%d)\n",
169 cs->section_file, cs->section_func, cs->section_line);
170 fprintf(stderr, "CS can't start section(%s,%s,%d)\n",
171 file, func, line);
172 return -EPIPE;
173 }
174 cs->section_ndw = ndw;
175 cs->section_cdw = 0;
176 cs->section_file = file;
177 cs->section_func = func;
178 cs->section_line = line;
179
180
181 if (cs->cdw + ndw > cs->ndw) {
182 uint32_t tmp, *ptr;
183
184 tmp = (cs->cdw + ndw + 0x3ff) & (~0x3ff);
185 ptr = (uint32_t*)realloc(cs->packets, 4 * tmp);
186 if (ptr == NULL) {
187 return -ENOMEM;
188 }
189 cs->packets = ptr;
190 cs->ndw = tmp;
191 }
192
193 return 0;
194 }
195
196 static int cs_end(struct radeon_cs_int *cs,
197 const char *file,
198 const char *func,
199 int line)
200
201 {
202 if (!cs->section_ndw) {
203 fprintf(stderr, "CS no section to end at (%s,%s,%d)\n",
204 file, func, line);
205 return -EPIPE;
206 }
207 if (cs->section_ndw != cs->section_cdw) {
208 fprintf(stderr, "CS section size missmatch start at (%s,%s,%d) %d vs %d\n",
209 cs->section_file, cs->section_func, cs->section_line, cs->section_ndw, cs->section_cdw);
210 fprintf(stderr, "CS section end at (%s,%s,%d)\n",
211 file, func, line);
212 return -EPIPE;
213 }
214 cs->section_ndw = 0;
215
216 return 0;
217 }
218
219 static int cs_process_relocs(struct radeon_cs_int *cs)
220 {
221 struct cs_reloc_legacy *relocs;
222 int i, j, r;
223
224 relocs = (struct cs_reloc_legacy *)cs->relocs;
225 restart:
226 for (i = 0; i < cs->crelocs; i++)
227 {
228 for (j = 0; j < relocs[i].cindices; j++)
229 {
230 uint32_t soffset, eoffset;
231
232 r = radeon_bo_legacy_validate(relocs[i].base.bo,
233 &soffset, &eoffset);
234 if (r == -EAGAIN)
235 {
236 goto restart;
237 }
238 if (r)
239 {
240 fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
241 relocs[i].base.bo, soffset, eoffset);
242 return r;
243 }
244 cs->packets[relocs[i].indices[j]] += soffset;
245 if (cs->packets[relocs[i].indices[j]] >= eoffset)
246 {
247 /* radeon_bo_debug(relocs[i].base.bo, 12); */
248 fprintf(stderr, "validated %p [0x%08X, 0x%08X]\n",
249 relocs[i].base.bo, soffset, eoffset);
250 fprintf(stderr, "above end: %p 0x%08X 0x%08X\n",
251 relocs[i].base.bo,
252 cs->packets[relocs[i].indices[j]],
253 eoffset);
254 exit(0);
255 return -EINVAL;
256 }
257 }
258 }
259 return 0;
260 }
261
262 static int cs_set_age(struct radeon_cs_int *cs)
263 {
264 struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm;
265 struct cs_reloc_legacy *relocs;
266 int i;
267
268 relocs = (struct cs_reloc_legacy *)cs->relocs;
269 for (i = 0; i < cs->crelocs; i++) {
270 radeon_bo_legacy_pending(relocs[i].base.bo, csm->pending_age);
271 radeon_bo_unref(relocs[i].base.bo);
272 }
273 return 0;
274 }
275
276 static int cs_emit(struct radeon_cs_int *cs)
277 {
278 struct cs_manager_legacy *csm = (struct cs_manager_legacy*)cs->csm;
279 drm_radeon_cmd_buffer_t cmd;
280 drm_r300_cmd_header_t age;
281 uint64_t ull;
282 int r;
283
284 csm->ctx->vtbl.emit_cs_header((struct radeon_cs *)cs, csm->ctx);
285
286 /* append buffer age */
287 if ( IS_R300_CLASS(csm->ctx->radeonScreen) )
288 {
289 age.scratch.cmd_type = R300_CMD_SCRATCH;
290 /* Scratch register 2 corresponds to what radeonGetAge polls */
291 csm->pending_age = 0;
292 csm->pending_count = 1;
293 ull = (uint64_t) (intptr_t) &csm->pending_age;
294 age.scratch.reg = 2;
295 age.scratch.n_bufs = 1;
296 age.scratch.flags = 0;
297 radeon_cs_write_dword((struct radeon_cs *)cs, age.u);
298 radeon_cs_write_qword((struct radeon_cs *)cs, ull);
299 radeon_cs_write_dword((struct radeon_cs *)cs, 0);
300 }
301
302 r = cs_process_relocs(cs);
303 if (r) {
304 return 0;
305 }
306
307 cmd.buf = (char *)cs->packets;
308 cmd.bufsz = cs->cdw * 4;
309 if (csm->ctx->state.scissor.enabled) {
310 cmd.nbox = csm->ctx->state.scissor.numClipRects;
311 cmd.boxes = (drm_clip_rect_t *) csm->ctx->state.scissor.pClipRects;
312 } else {
313 cmd.nbox = csm->ctx->numClipRects;
314 cmd.boxes = (drm_clip_rect_t *) csm->ctx->pClipRects;
315 }
316
317 //dump_cmdbuf(cs);
318
319 r = drmCommandWrite(cs->csm->fd, DRM_RADEON_CMDBUF, &cmd, sizeof(cmd));
320 if (r) {
321 return r;
322 }
323 if ((!IS_R300_CLASS(csm->ctx->radeonScreen)) &&
324 (!IS_R600_CLASS(csm->ctx->radeonScreen))) { /* +r6/r7 : No irq for r6/r7 yet. */
325 drm_radeon_irq_emit_t emit_cmd;
326 emit_cmd.irq_seq = (int*)&csm->pending_age;
327 r = drmCommandWriteRead(cs->csm->fd, DRM_RADEON_IRQ_EMIT, &emit_cmd, sizeof(emit_cmd));
328 if (r) {
329 return r;
330 }
331 }
332 cs_set_age(cs);
333
334 cs->csm->read_used = 0;
335 cs->csm->vram_write_used = 0;
336 cs->csm->gart_write_used = 0;
337 return 0;
338 }
339
340 static void inline cs_free_reloc(void *relocs_p, int crelocs)
341 {
342 struct cs_reloc_legacy *relocs = relocs_p;
343 int i;
344 if (!relocs_p)
345 return;
346 for (i = 0; i < crelocs; i++)
347 free(relocs[i].indices);
348 }
349
350 static int cs_destroy(struct radeon_cs_int *cs)
351 {
352 cs_free_reloc(cs->relocs, cs->crelocs);
353 free(cs->relocs);
354 free(cs->packets);
355 free(cs);
356 return 0;
357 }
358
359 static int cs_erase(struct radeon_cs_int *cs)
360 {
361 cs_free_reloc(cs->relocs, cs->crelocs);
362 free(cs->relocs);
363 cs->relocs_total_size = 0;
364 cs->relocs = NULL;
365 cs->crelocs = 0;
366 cs->cdw = 0;
367 cs->section_ndw = 0;
368 return 0;
369 }
370
371 static int cs_need_flush(struct radeon_cs_int *cs)
372 {
373 /* this function used to flush when the BO usage got to
374 * a certain size, now the higher levels handle this better */
375 return 0;
376 }
377
378 static void cs_print(struct radeon_cs_int *cs, FILE *file)
379 {
380 }
381
382 static struct radeon_cs_funcs radeon_cs_legacy_funcs = {
383 cs_create,
384 cs_write_reloc,
385 cs_begin,
386 cs_end,
387 cs_emit,
388 cs_destroy,
389 cs_erase,
390 cs_need_flush,
391 cs_print,
392 };
393
394 struct radeon_cs_manager *radeon_cs_manager_legacy_ctor(struct radeon_context *ctx)
395 {
396 struct cs_manager_legacy *csm;
397
398 csm = (struct cs_manager_legacy*)
399 calloc(1, sizeof(struct cs_manager_legacy));
400 if (csm == NULL) {
401 return NULL;
402 }
403 csm->base.funcs = &radeon_cs_legacy_funcs;
404 csm->base.fd = ctx->dri.fd;
405 csm->ctx = ctx;
406 csm->pending_age = 1;
407 return (struct radeon_cs_manager*)csm;
408 }
409
410 void radeon_cs_manager_legacy_dtor(struct radeon_cs_manager *csm)
411 {
412 free(csm);
413 }
414