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Drop GLcontext typedef and use struct gl_context instead
[mesa.git] / src / mesa / drivers / dri / radeon / radeon_cs_space_drm.c
1 /*
2 * Copyright © 2009 Red Hat Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 */
26 /*
27 */
28 #include <assert.h>
29 #include <errno.h>
30 #include <stdlib.h>
31 #include "radeon_bocs_wrapper.h"
32 #include "radeon_bo_int_drm.h"
33 #include "radeon_cs_int_drm.h"
34
35 struct rad_sizes {
36 int32_t op_read;
37 int32_t op_gart_write;
38 int32_t op_vram_write;
39 };
40
41 static inline int radeon_cs_setup_bo(struct radeon_cs_space_check *sc, struct rad_sizes *sizes)
42 {
43 uint32_t read_domains, write_domain;
44 struct radeon_bo_int *bo;
45
46 bo = sc->bo;
47 sc->new_accounted = 0;
48 read_domains = sc->read_domains;
49 write_domain = sc->write_domain;
50
51 /* legacy needs a static check */
52 if (radeon_bo_is_static((struct radeon_bo *)sc->bo)) {
53 bo->space_accounted = sc->new_accounted = (read_domains << 16) | write_domain;
54 return 0;
55 }
56
57 /* already accounted this bo */
58 if (write_domain && (write_domain == bo->space_accounted)) {
59 sc->new_accounted = bo->space_accounted;
60 return 0;
61 }
62 if (read_domains && ((read_domains << 16) == bo->space_accounted)) {
63 sc->new_accounted = bo->space_accounted;
64 return 0;
65 }
66
67 if (bo->space_accounted == 0) {
68 if (write_domain == RADEON_GEM_DOMAIN_VRAM)
69 sizes->op_vram_write += bo->size;
70 else if (write_domain == RADEON_GEM_DOMAIN_GTT)
71 sizes->op_gart_write += bo->size;
72 else
73 sizes->op_read += bo->size;
74 sc->new_accounted = (read_domains << 16) | write_domain;
75 } else {
76 uint16_t old_read, old_write;
77
78 old_read = bo->space_accounted >> 16;
79 old_write = bo->space_accounted & 0xffff;
80
81 if (write_domain && (old_read & write_domain)) {
82 sc->new_accounted = write_domain;
83 /* moving from read to a write domain */
84 if (write_domain == RADEON_GEM_DOMAIN_VRAM) {
85 sizes->op_read -= bo->size;
86 sizes->op_vram_write += bo->size;
87 } else if (write_domain == RADEON_GEM_DOMAIN_GTT) {
88 sizes->op_read -= bo->size;
89 sizes->op_gart_write += bo->size;
90 }
91 } else if (read_domains & old_write) {
92 sc->new_accounted = bo->space_accounted & 0xffff;
93 } else {
94 /* rewrite the domains */
95 if (write_domain != old_write)
96 fprintf(stderr,"WRITE DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, write_domain, old_write);
97 if (read_domains != old_read)
98 fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_read);
99 return RADEON_CS_SPACE_FLUSH;
100 }
101 }
102 return 0;
103 }
104
105 static int radeon_cs_do_space_check(struct radeon_cs_int *cs, struct radeon_cs_space_check *new_tmp)
106 {
107 struct radeon_cs_manager *csm = cs->csm;
108 int i;
109 struct radeon_bo_int *bo;
110 struct rad_sizes sizes;
111 int ret;
112
113 /* check the totals for this operation */
114
115 if (cs->bo_count == 0 && !new_tmp)
116 return 0;
117
118 memset(&sizes, 0, sizeof(struct rad_sizes));
119
120 /* prepare */
121 for (i = 0; i < cs->bo_count; i++) {
122 ret = radeon_cs_setup_bo(&cs->bos[i], &sizes);
123 if (ret)
124 return ret;
125 }
126
127 if (new_tmp) {
128 ret = radeon_cs_setup_bo(new_tmp, &sizes);
129 if (ret)
130 return ret;
131 }
132
133 if (sizes.op_read < 0)
134 sizes.op_read = 0;
135
136 /* check sizes - operation first */
137 if ((sizes.op_read + sizes.op_gart_write > csm->gart_limit) ||
138 (sizes.op_vram_write > csm->vram_limit)) {
139 return RADEON_CS_SPACE_OP_TO_BIG;
140 }
141
142 if (((csm->vram_write_used + sizes.op_vram_write) > csm->vram_limit) ||
143 ((csm->read_used + csm->gart_write_used + sizes.op_gart_write + sizes.op_read) > csm->gart_limit)) {
144 return RADEON_CS_SPACE_FLUSH;
145 }
146
147 csm->gart_write_used += sizes.op_gart_write;
148 csm->vram_write_used += sizes.op_vram_write;
149 csm->read_used += sizes.op_read;
150 /* commit */
151 for (i = 0; i < cs->bo_count; i++) {
152 bo = cs->bos[i].bo;
153 bo->space_accounted = cs->bos[i].new_accounted;
154 }
155 if (new_tmp)
156 new_tmp->bo->space_accounted = new_tmp->new_accounted;
157
158 return RADEON_CS_SPACE_OK;
159 }
160
161 void radeon_cs_space_add_persistent_bo(struct radeon_cs *cs, struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain)
162 {
163 struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
164 struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
165 int i;
166 for (i = 0; i < csi->bo_count; i++) {
167 if (csi->bos[i].bo == boi &&
168 csi->bos[i].read_domains == read_domains &&
169 csi->bos[i].write_domain == write_domain)
170 return;
171 }
172 radeon_bo_ref(bo);
173 i = csi->bo_count;
174 csi->bos[i].bo = boi;
175 csi->bos[i].read_domains = read_domains;
176 csi->bos[i].write_domain = write_domain;
177 csi->bos[i].new_accounted = 0;
178 csi->bo_count++;
179
180 assert(csi->bo_count < MAX_SPACE_BOS);
181 }
182
183 static int radeon_cs_check_space_internal(struct radeon_cs_int *cs,
184 struct radeon_cs_space_check *tmp_bo)
185 {
186 int ret;
187 int flushed = 0;
188
189 again:
190 ret = radeon_cs_do_space_check(cs, tmp_bo);
191 if (ret == RADEON_CS_SPACE_OP_TO_BIG)
192 return -1;
193 if (ret == RADEON_CS_SPACE_FLUSH) {
194 (*cs->space_flush_fn)(cs->space_flush_data);
195 if (flushed)
196 return -1;
197 flushed = 1;
198 goto again;
199 }
200 return 0;
201 }
202
203 int radeon_cs_space_check_with_bo(struct radeon_cs *cs,
204 struct radeon_bo *bo,
205 uint32_t read_domains, uint32_t write_domain)
206 {
207 struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
208 struct radeon_bo_int *boi = (struct radeon_bo_int *)bo;
209 struct radeon_cs_space_check temp_bo;
210
211 int ret = 0;
212
213 if (bo) {
214 temp_bo.bo = boi;
215 temp_bo.read_domains = read_domains;
216 temp_bo.write_domain = write_domain;
217 temp_bo.new_accounted = 0;
218 }
219
220 ret = radeon_cs_check_space_internal(csi, bo ? &temp_bo : NULL);
221 return ret;
222 }
223
224 int radeon_cs_space_check(struct radeon_cs *cs)
225 {
226 struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
227 return radeon_cs_check_space_internal(csi, NULL);
228 }
229
230 void radeon_cs_space_reset_bos(struct radeon_cs *cs)
231 {
232 struct radeon_cs_int *csi = (struct radeon_cs_int *)cs;
233 int i;
234 for (i = 0; i < csi->bo_count; i++) {
235 radeon_bo_unref((struct radeon_bo *)csi->bos[i].bo);
236 csi->bos[i].bo = NULL;
237 csi->bos[i].read_domains = 0;
238 csi->bos[i].write_domain = 0;
239 csi->bos[i].new_accounted = 0;
240 }
241 csi->bo_count = 0;
242 }
243
244