2 * Copyright (C) 2009 Maciej Cencora.
3 * Copyright (C) 2008 Nicolai Haehnle.
7 * Permission is hereby granted, free of charge, to any person obtaining
8 * a copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sublicense, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial
17 * portions of the Software.
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
22 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
23 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
24 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
25 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "radeon_mipmap_tree.h"
34 #include "main/simple_list.h"
35 #include "main/texcompress.h"
36 #include "main/teximage.h"
37 #include "main/texobj.h"
38 #include "radeon_texture.h"
40 static GLuint
radeon_compressed_texture_size(GLcontext
*ctx
,
41 GLsizei width
, GLsizei height
, GLsizei depth
,
44 GLuint size
= _mesa_format_image_size(mesaFormat
, width
, height
, depth
);
46 if (mesaFormat
== MESA_FORMAT_RGB_DXT1
||
47 mesaFormat
== MESA_FORMAT_RGBA_DXT1
) {
48 if (width
+ 3 < 8) /* width one block */
50 else if (width
+ 3 < 16)
53 /* DXT3/5, 16 bytes per block */
54 // WARN_ONCE("DXT 3/5 suffers from multitexturing problems!\n");
63 * Compute sizes and fill in offset and blit information for the given
64 * image (determined by \p face and \p level).
66 * \param curOffset points to the offset at which the image is to be stored
67 * and is updated by this function according to the size of the image.
69 static void compute_tex_image_offset(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
,
70 GLuint face
, GLuint level
, GLuint
* curOffset
)
72 radeon_mipmap_level
*lvl
= &mt
->levels
[level
];
75 /* Find image size in bytes */
76 if (_mesa_is_format_compressed(mt
->mesaFormat
)) {
77 /* TODO: Is this correct? Need test cases for compressed textures! */
78 row_align
= rmesa
->texture_compressed_row_align
- 1;
79 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) + row_align
) & ~row_align
;
80 lvl
->size
= radeon_compressed_texture_size(rmesa
->glCtx
, lvl
->width
, lvl
->height
, lvl
->depth
, mt
->mesaFormat
);
81 } else if (mt
->target
== GL_TEXTURE_RECTANGLE_NV
) {
82 row_align
= rmesa
->texture_rect_row_align
- 1;
83 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) + row_align
) & ~row_align
;
84 lvl
->size
= lvl
->rowstride
* lvl
->height
;
85 } else if (mt
->tilebits
& RADEON_TXO_MICRO_TILE
) {
86 /* tile pattern is 16 bytes x2. mipmaps stay 32 byte aligned,
87 * though the actual offset may be different (if texture is less than
88 * 32 bytes width) to the untiled case */
89 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) * 2 + 31) & ~31;
90 lvl
->size
= lvl
->rowstride
* ((lvl
->height
+ 1) / 2) * lvl
->depth
;
92 row_align
= rmesa
->texture_row_align
- 1;
93 lvl
->rowstride
= (_mesa_format_row_stride(mt
->mesaFormat
, lvl
->width
) + row_align
) & ~row_align
;
94 lvl
->size
= lvl
->rowstride
* lvl
->height
* lvl
->depth
;
96 assert(lvl
->size
> 0);
98 /* All images are aligned to a 32-byte offset */
99 *curOffset
= (*curOffset
+ 0x1f) & ~0x1f;
100 lvl
->faces
[face
].offset
= *curOffset
;
101 *curOffset
+= lvl
->size
;
103 if (RADEON_DEBUG
& RADEON_TEXTURE
)
105 "level %d, face %d: rs:%d %dx%d at %d\n",
106 level
, face
, lvl
->rowstride
, lvl
->width
, lvl
->height
, lvl
->faces
[face
].offset
);
109 static GLuint
minify(GLuint size
, GLuint levels
)
111 size
= size
>> levels
;
118 static void calculate_miptree_layout_r100(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
)
124 assert(mt
->numLevels
<= rmesa
->glCtx
->Const
.MaxTextureLevels
);
127 for(face
= 0; face
< mt
->faces
; face
++) {
129 for(i
= 0; i
< mt
->numLevels
; i
++) {
130 mt
->levels
[i
].width
= minify(mt
->width0
, i
);
131 mt
->levels
[i
].height
= minify(mt
->height0
, i
);
132 mt
->levels
[i
].depth
= minify(mt
->depth0
, i
);
133 compute_tex_image_offset(rmesa
, mt
, face
, i
, &curOffset
);
137 /* Note the required size in memory */
138 mt
->totalsize
= (curOffset
+ RADEON_OFFSET_MASK
) & ~RADEON_OFFSET_MASK
;
141 static void calculate_miptree_layout_r300(radeonContextPtr rmesa
, radeon_mipmap_tree
*mt
)
146 assert(mt
->numLevels
<= rmesa
->glCtx
->Const
.MaxTextureLevels
);
149 for(i
= 0; i
< mt
->numLevels
; i
++) {
152 mt
->levels
[i
].width
= minify(mt
->width0
, i
);
153 mt
->levels
[i
].height
= minify(mt
->height0
, i
);
154 mt
->levels
[i
].depth
= minify(mt
->depth0
, i
);
156 for(face
= 0; face
< mt
->faces
; face
++)
157 compute_tex_image_offset(rmesa
, mt
, face
, i
, &curOffset
);
160 /* Note the required size in memory */
161 mt
->totalsize
= (curOffset
+ RADEON_OFFSET_MASK
) & ~RADEON_OFFSET_MASK
;
165 * Create a new mipmap tree, calculate its layout and allocate memory.
167 static radeon_mipmap_tree
* radeon_miptree_create(radeonContextPtr rmesa
,
168 GLenum target
, gl_format mesaFormat
, GLuint baseLevel
, GLuint numLevels
,
169 GLuint width0
, GLuint height0
, GLuint depth0
, GLuint tilebits
)
171 radeon_mipmap_tree
*mt
= CALLOC_STRUCT(_radeon_mipmap_tree
);
173 mt
->mesaFormat
= mesaFormat
;
176 mt
->faces
= (target
== GL_TEXTURE_CUBE_MAP
) ? 6 : 1;
177 mt
->baseLevel
= baseLevel
;
178 mt
->numLevels
= numLevels
;
180 mt
->height0
= height0
;
182 mt
->tilebits
= tilebits
;
184 if (rmesa
->radeonScreen
->chip_family
>= CHIP_FAMILY_R300
)
185 calculate_miptree_layout_r300(rmesa
, mt
);
187 calculate_miptree_layout_r100(rmesa
, mt
);
189 mt
->bo
= radeon_bo_open(rmesa
->radeonScreen
->bom
,
190 0, mt
->totalsize
, 1024,
191 RADEON_GEM_DOMAIN_VRAM
,
197 void radeon_miptree_reference(radeon_mipmap_tree
*mt
, radeon_mipmap_tree
**ptr
)
202 assert(mt
->refcount
> 0);
207 void radeon_miptree_unreference(radeon_mipmap_tree
**ptr
)
209 radeon_mipmap_tree
*mt
= *ptr
;
213 assert(mt
->refcount
> 0);
217 radeon_bo_unref(mt
->bo
);
225 * Calculate min and max LOD for the given texture object.
226 * @param[in] tObj texture object whose LOD values to calculate
227 * @param[out] pminLod minimal LOD
228 * @param[out] pmaxLod maximal LOD
230 static void calculate_min_max_lod(struct gl_texture_object
*tObj
,
231 unsigned *pminLod
, unsigned *pmaxLod
)
234 /* Yes, this looks overly complicated, but it's all needed.
236 switch (tObj
->Target
) {
240 case GL_TEXTURE_CUBE_MAP
:
241 if (tObj
->MinFilter
== GL_NEAREST
|| tObj
->MinFilter
== GL_LINEAR
) {
242 /* GL_NEAREST and GL_LINEAR only care about GL_TEXTURE_BASE_LEVEL.
244 minLod
= maxLod
= tObj
->BaseLevel
;
246 minLod
= tObj
->BaseLevel
+ (GLint
)(tObj
->MinLod
);
247 minLod
= MAX2(minLod
, tObj
->BaseLevel
);
248 minLod
= MIN2(minLod
, tObj
->MaxLevel
);
249 maxLod
= tObj
->BaseLevel
+ (GLint
)(tObj
->MaxLod
+ 0.5);
250 maxLod
= MIN2(maxLod
, tObj
->MaxLevel
);
251 maxLod
= MIN2(maxLod
, tObj
->Image
[0][minLod
]->MaxLog2
+ minLod
);
252 maxLod
= MAX2(maxLod
, minLod
); /* need at least one level */
255 case GL_TEXTURE_RECTANGLE_NV
:
256 case GL_TEXTURE_4D_SGIS
:
263 /* save these values */
269 * Checks whether the given miptree can hold the given texture image at the
270 * given face and level.
272 GLboolean
radeon_miptree_matches_image(radeon_mipmap_tree
*mt
,
273 struct gl_texture_image
*texImage
, GLuint face
, GLuint mtLevel
)
275 radeon_mipmap_level
*lvl
;
277 if (face
>= mt
->faces
|| mtLevel
> mt
->numLevels
)
280 if (texImage
->TexFormat
!= mt
->mesaFormat
)
283 lvl
= &mt
->levels
[mtLevel
];
284 if (lvl
->width
!= texImage
->Width
||
285 lvl
->height
!= texImage
->Height
||
286 lvl
->depth
!= texImage
->Depth
)
293 * Checks whether the given miptree has the right format to store the given texture object.
295 static GLboolean
radeon_miptree_matches_texture(radeon_mipmap_tree
*mt
, struct gl_texture_object
*texObj
)
297 struct gl_texture_image
*firstImage
;
299 radeon_mipmap_level
*mtBaseLevel
;
301 if (texObj
->BaseLevel
< mt
->baseLevel
)
304 mtBaseLevel
= &mt
->levels
[texObj
->BaseLevel
- mt
->baseLevel
];
305 firstImage
= texObj
->Image
[0][texObj
->BaseLevel
];
306 numLevels
= MIN2(texObj
->MaxLevel
- texObj
->BaseLevel
+ 1, firstImage
->MaxLog2
+ 1);
308 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
309 fprintf(stderr
, "Checking if miptree %p matches texObj %p\n", mt
, texObj
);
310 fprintf(stderr
, "target %d vs %d\n", mt
->target
, texObj
->Target
);
311 fprintf(stderr
, "format %d vs %d\n", mt
->mesaFormat
, firstImage
->TexFormat
);
312 fprintf(stderr
, "numLevels %d vs %d\n", mt
->numLevels
, numLevels
);
313 fprintf(stderr
, "width0 %d vs %d\n", mtBaseLevel
->width
, firstImage
->Width
);
314 fprintf(stderr
, "height0 %d vs %d\n", mtBaseLevel
->height
, firstImage
->Height
);
315 fprintf(stderr
, "depth0 %d vs %d\n", mtBaseLevel
->depth
, firstImage
->Depth
);
316 if (mt
->target
== texObj
->Target
&&
317 mt
->mesaFormat
== firstImage
->TexFormat
&&
318 mt
->numLevels
>= numLevels
&&
319 mtBaseLevel
->width
== firstImage
->Width
&&
320 mtBaseLevel
->height
== firstImage
->Height
&&
321 mtBaseLevel
->depth
== firstImage
->Depth
) {
322 fprintf(stderr
, "MATCHED\n");
324 fprintf(stderr
, "NOT MATCHED\n");
328 return (mt
->target
== texObj
->Target
&&
329 mt
->mesaFormat
== firstImage
->TexFormat
&&
330 mt
->numLevels
>= numLevels
&&
331 mtBaseLevel
->width
== firstImage
->Width
&&
332 mtBaseLevel
->height
== firstImage
->Height
&&
333 mtBaseLevel
->depth
== firstImage
->Depth
);
337 * Try to allocate a mipmap tree for the given texture object.
338 * @param[in] rmesa radeon context
339 * @param[in] t radeon texture object
341 void radeon_try_alloc_miptree(radeonContextPtr rmesa
, radeonTexObj
*t
)
343 struct gl_texture_object
*texObj
= &t
->base
;
344 struct gl_texture_image
*texImg
= texObj
->Image
[0][texObj
->BaseLevel
];
352 numLevels
= MIN2(texObj
->MaxLevel
- texObj
->BaseLevel
+ 1, texImg
->MaxLog2
+ 1);
354 t
->mt
= radeon_miptree_create(rmesa
, t
->base
.Target
,
355 texImg
->TexFormat
, texObj
->BaseLevel
,
356 numLevels
, texImg
->Width
, texImg
->Height
,
357 texImg
->Depth
, t
->tile_bits
);
360 /* Although we use the image_offset[] array to store relative offsets
361 * to cube faces, Mesa doesn't know anything about this and expects
362 * each cube face to be treated as a separate image.
364 * These functions present that view to mesa:
367 radeon_miptree_depth_offsets(radeon_mipmap_tree
*mt
, GLuint level
, GLuint
*offsets
)
369 if (mt
->target
!= GL_TEXTURE_3D
|| mt
->faces
== 1) {
373 for (i
= 0; i
< 6; i
++) {
374 offsets
[i
] = mt
->levels
[level
].faces
[i
].offset
;
380 radeon_miptree_image_offset(radeon_mipmap_tree
*mt
,
381 GLuint face
, GLuint level
)
383 if (mt
->target
== GL_TEXTURE_CUBE_MAP_ARB
)
384 return (mt
->levels
[level
].faces
[face
].offset
);
386 return mt
->levels
[level
].faces
[0].offset
;
390 * Convert radeon miptree texture level to GL texture level
391 * @param[in] tObj texture object whom level is to be converted
392 * @param[in] level radeon miptree texture level
393 * @return GL texture level
395 unsigned radeon_miptree_level_to_gl_level(struct gl_texture_object
*tObj
, unsigned level
)
397 return level
+ tObj
->BaseLevel
;
401 * Convert GL texture level to radeon miptree texture level
402 * @param[in] tObj texture object whom level is to be converted
403 * @param[in] level GL texture level
404 * @return radeon miptree texture level
406 unsigned radeon_gl_level_to_miptree_level(struct gl_texture_object
*tObj
, unsigned level
)
408 return level
- tObj
->BaseLevel
;
412 * Ensure that the given image is stored in the given miptree from now on.
414 static void migrate_image_to_miptree(radeon_mipmap_tree
*mt
,
415 radeon_texture_image
*image
,
416 int face
, int mtLevel
)
418 radeon_mipmap_level
*dstlvl
= &mt
->levels
[mtLevel
];
421 assert(image
->mt
!= mt
);
422 assert(dstlvl
->width
== image
->base
.Width
);
423 assert(dstlvl
->height
== image
->base
.Height
);
424 assert(dstlvl
->depth
== image
->base
.Depth
);
426 radeon_bo_map(mt
->bo
, GL_TRUE
);
427 dest
= mt
->bo
->ptr
+ dstlvl
->faces
[face
].offset
;
430 /* Format etc. should match, so we really just need a memcpy().
431 * In fact, that memcpy() could be done by the hardware in many
432 * cases, provided that we have a proper memory manager.
434 assert(mt
->mesaFormat
== image
->base
.TexFormat
);
436 radeon_mipmap_level
*srclvl
= &image
->mt
->levels
[image
->mtlevel
];
438 assert(srclvl
->size
== dstlvl
->size
);
439 assert(srclvl
->rowstride
== dstlvl
->rowstride
);
441 radeon_bo_map(image
->mt
->bo
, GL_FALSE
);
444 image
->mt
->bo
->ptr
+ srclvl
->faces
[face
].offset
,
446 radeon_bo_unmap(image
->mt
->bo
);
448 radeon_miptree_unreference(&image
->mt
);
450 /* need to confirm this value is correct */
451 if (_mesa_is_format_compressed(image
->base
.TexFormat
)) {
452 unsigned size
= _mesa_format_image_size(image
->base
.TexFormat
,
456 memcpy(dest
, image
->base
.Data
, size
);
458 uint32_t srcrowstride
;
461 height
= image
->base
.Height
* image
->base
.Depth
;
462 srcrowstride
= image
->base
.Width
* _mesa_get_format_bytes(image
->base
.TexFormat
);
463 copy_rows(dest
, dstlvl
->rowstride
, image
->base
.Data
, srcrowstride
,
464 height
, srcrowstride
);
467 _mesa_free_texmemory(image
->base
.Data
);
468 image
->base
.Data
= 0;
471 radeon_bo_unmap(mt
->bo
);
473 radeon_miptree_reference(mt
, &image
->mt
);
474 image
->mtface
= face
;
475 image
->mtlevel
= mtLevel
;
479 * Filter matching miptrees, and select one with the most of data.
480 * @param[in] texObj radeon texture object
481 * @param[in] firstLevel first texture level to check
482 * @param[in] lastLevel last texture level to check
484 static radeon_mipmap_tree
* get_biggest_matching_miptree(radeonTexObj
*texObj
,
488 const unsigned numLevels
= lastLevel
- firstLevel
;
489 unsigned *mtSizes
= calloc(numLevels
, sizeof(unsigned));
490 radeon_mipmap_tree
**mts
= calloc(numLevels
, sizeof(radeon_mipmap_tree
*));
491 unsigned mtCount
= 0;
492 unsigned maxMtIndex
= 0;
494 for (unsigned level
= firstLevel
; level
<= lastLevel
; ++level
) {
495 radeon_texture_image
*img
= get_radeon_texture_image(texObj
->base
.Image
[0][level
]);
497 // TODO: why this hack??
501 if (!img
->mt
|| !radeon_miptree_matches_texture(img
->mt
, &texObj
->base
))
504 for (int i
= 0; i
< mtCount
; ++i
) {
505 if (mts
[i
] == img
->mt
) {
507 mtSizes
[i
] += img
->mt
->levels
[img
->mtlevel
].size
;
513 mtSizes
[mtCount
] += img
->mt
->levels
[img
->mtlevel
].size
;
514 mts
[mtCount
++] = img
->mt
;
523 for (int i
= 1; i
< mtCount
; ++i
) {
524 if (mtSizes
[i
] > mtSizes
[maxMtIndex
]) {
529 return mts
[maxMtIndex
];
533 * Validate texture mipmap tree.
534 * If individual images are stored in different mipmap trees
535 * use the mipmap tree that has the most of the correct data.
537 int radeon_validate_texture_miptree(GLcontext
* ctx
, struct gl_texture_object
*texObj
)
539 radeonContextPtr rmesa
= RADEON_CONTEXT(ctx
);
540 radeonTexObj
*t
= radeon_tex_obj(texObj
);
542 if (t
->validated
|| t
->image_override
) {
546 if (texObj
->Image
[0][texObj
->BaseLevel
]->Border
> 0)
549 _mesa_test_texobj_completeness(rmesa
->glCtx
, texObj
);
550 if (!texObj
->_Complete
) {
554 calculate_min_max_lod(&t
->base
, &t
->minLod
, &t
->maxLod
);
556 if (RADEON_DEBUG
& RADEON_TEXTURE
)
557 fprintf(stderr
, "%s: Validating texture %p now, minLod = %d, maxLod = %d\n",
558 __FUNCTION__
, texObj
,t
->minLod
, t
->maxLod
);
560 radeon_mipmap_tree
*dst_miptree
;
561 dst_miptree
= get_biggest_matching_miptree(t
, t
->minLod
, t
->maxLod
);
564 radeon_miptree_unreference(&t
->mt
);
565 radeon_try_alloc_miptree(rmesa
, t
);
569 const unsigned faces
= texObj
->Target
== GL_TEXTURE_CUBE_MAP
? 6 : 1;
570 unsigned face
, level
;
571 radeon_texture_image
*img
;
572 /* Validate only the levels that will actually be used during rendering */
573 for (face
= 0; face
< faces
; ++face
) {
574 for (level
= t
->minLod
; level
<= t
->maxLod
; ++level
) {
575 img
= get_radeon_texture_image(texObj
->Image
[face
][level
]);
577 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
578 fprintf(stderr
, "Checking image level %d, face %d, mt %p ... ", level
, face
, img
->mt
);
581 if (img
->mt
!= dst_miptree
) {
582 if (RADEON_DEBUG
& RADEON_TEXTURE
) {
583 fprintf(stderr
, "MIGRATING\n");
585 migrate_image_to_miptree(dst_miptree
, img
, face
, radeon_gl_level_to_miptree_level(texObj
, level
));
586 } else if (RADEON_DEBUG
& RADEON_TEXTURE
) {
587 fprintf(stderr
, "OK\n");
592 t
->validated
= GL_TRUE
;
597 uint32_t get_base_teximage_offset(radeonTexObj
*texObj
)
602 return radeon_miptree_image_offset(texObj
->mt
, 0, texObj
->minLod
);